Analog Devices ADSP-2173BST-80, ADSP-2173BS-80, ADSP-2171KST-133, ADSP-2171KST-104, ADSP-2171KS-133 Datasheet
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EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
SHIFTER
MAC
ALU
MEMORY
SERIAL PORTS
SPORT 0
SPORT 1
FLAGS
DATA
ADDRESS
GENERATORS
DAG 1
DAG 2
PROGRAM
SEQUENCER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
DATA MEMORY DATA
TIMER
PROGRAM MEMORY DATA
DATA
MEMORY
2K x 16
PROGRAM
ROM
8K x 24
PROGRAM
RAM
2K x 24
POWERDOWN
CONTROL
LOGIC
HOST
INTERFACE
PORT
ADSP-2100 BASE
ARCHITECTURE
DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipulation Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP-
2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTION
The ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applications. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
The ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a program sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and onchip program and data memory.
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared),
biased rounding, and global interrupt masking, for increased
flexibility. The ADSP-217x also has a Bus Grant Hang Logic
BGH) feature.
(
The ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. The ADSP-2172 provides an additional 8K words (24-bit) of program ROM. Powerdown circuitry is also provided to meet the low power needs of
battery operated portable equipment. The ADSP-217x is available in 128-pin TQFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-217x’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-217x can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
This takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the host interface port
• decrement timer
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
ADSP-2171/ADSP-2172/ADSP-2173
Development System
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardwaresystem development, supports
the ADSP-217x. The System Builder provides a high-level
method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-217x assembly source
code. The Runtime Library includes over 100 ANSI-standard
mathematical and DSP-specific functions.
EZ-Tools, low cost, easy-to-use hardware tools, also support the
ADSP-217x.
®
The ADSP-217x EZ-ICE
Emulator aids in the hardware debugging of ADSP-217x systems. The emulator consists of hardware, host computer resident software, the emulator probe, and
the pin adaptor. The emulator performs a full range of emulation functions including stand-alone operation or operation in
the target, setting up to 20 breakpoints, single-step or full-speed
operation in the target, examining and altering registers and
memory values, and PC upload/download functions. If you plan
to use the emulator, you should consider the emulator’s restrictions (differences between emulator and processor operation).
®
The EZ-LAB
Evaluation Board is a PC plug-in card, but it can
operate in stand-alone mode. The evaluation board/system development board executes EPROM-based or downloaded programs. Modular Analog Front End daughter cards with different
codecs will be made available.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
Additional Information
This data sheet provides a general overview of ADSP-217x
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the Development
System and ADSP-217x programmer’s reference information,
refer to the ADSP-2100 Family Assembler Tools & Simulator
Manual.
ARCHITECTURE OVERVIEW
Figure 1 is an overall block diagram of the ADSP-217x. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-217x executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
DATA
ADDRESS
GENERATOR
#1
INPUT REGS
ALU
OUTPUT REGS
DATA
ADDRESS
GENERATOR
#2
INPUT REGS
OUTPUT REGS
MAC
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
16
R BUS
PROGRAM ROM
8K X 24
PROGRAM SRAM
2K X 24
CONTROL
LOGIC
PMA BUS
DMA BUS
PMD BUS
DMD BUS
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
14
14
24
BUS
EXCHANGE
16
INPUT REGS
SHIFTER
OUTPUT REGS
Figure 1. ADSP-217x Block Diagram
DATA
SRAM
2K X 16
COMPANDING
CIRCUITRY
ADDRESS
GENERATOR
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
5
BOOT
TIMER
POWER DOWN
CONTROL
LOGIC
FLAGS
MUX
MUX
CONTROL
REGISTERS
2
3
EXTERNAL
ADDRESS
14
EXTERNAL
24
HIP
HIP
BUS
DATA
BUS
11
HIP
DATA
BUS
16
–2–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus.
Program memory can store both instructions and data, permitting the ADSP-217x to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP217x can fetch an operand from on-chip program memory and
the next instruction in the same cycle.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of external buses with bus
request/grant signals (
Mode) allows the ADSP-217x to continue running from internal memory. Normal execution mode requires the processor to
halt while buses are granted.
In addition to the address and data bus for external memory
connection, the ADSP-217x has a configurable 8- or 16-bit
Host Interface Port (HIP) for easy connection to a host processor. The HIP is made up of 16 data/address pins and 11 control
pins. The HIP is extremely flexible and provides a simple interface to a variety of host processors. For example, the Motorola
68000 series, the Intel 80C51 series and the Analog Devices’
ADSP-2101 can be easily connected to the HIP. The host processor can initialize the ASDP-217x’s on-chip memory through
the HIP.
The ADSP-217x can respond to eleven interrupts. There can be
up to three external interrupts, configured as edge or level sensitive, and eight internal interrupts generated by the Timer, the
Serial Ports (“SPORTs”), the HIP, the powerdown circuitry,
and software. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
Boot circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
seven wait states are automatically generated. This allows, for
example, a 30 ns ADSP-217x to use an external 200 ns
EPROM as boot memory. Multiple programs can be selected
BR and BG). One execution mode (Go
and loaded from the EPROM with no additional hardware. The
on-chip program memory can also be initialized through the
HIP.
The ADSP-217x features three general-purpose flag outputs
whose states can be simultaneously changed through software.
You can use these outputs to signal an event to an external
device. In addition, the data input and output pins on SPORT1
can be alternatively configured as an input flag and an output
flag.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycles, where n-l is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
The ADSP-217x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSP-217x assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Serial Ports
The ADSP-217x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-217x
SPORTs. Refer to the ADSP-2100 Family User’s Manual for
further details.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their own
serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
REV. A
–3–
ADSP-2171/ADSP-2172/ADSP-2173
Pin Description
The ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I. ADSP-217x Pin List
Pin #
Group of Input/
Name Pins Output Function
Address 14 O Address output for program,
data and boot memory spaces
Data 24 I/O Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
RESET 1 I Processor reset input
IRQ2 1 I External interrupt request #2
BR 1 I External bus request input
BG 1 O External bus grant output
BGH 1 O External bus grant hang output
PMS 1 O External program memory select
DMS 1 O External data memory select
BMS 1 O Boot memory select
RD 1 O External memory read enable
WR 1 O External memory write enable
MMAP 1 I Memory map select
CLKIN,
XTAL 2 I External clock or quartz crystal
input
CLKOUT 1 O Processor clock output
HSEL 1 I HIP select input
HACK 1 O HIP acknowledge output
HSIZE 1 8/16 bit host select input
0 = 16-bit; 1 = 8-bit
BMODE 1 I Boot mode select input
0 = EPROM/data bus; 1 = HIP
HMD0 1 I Bus strobe select input
0 = RD, WR; 1 = RW, DS
HMD1 1 I HIP address/data mode select
input 0 = separate; 1 =
multiplexed
HRD/HRW 1 I HIP read strobe/read/write
select input
HWR/HDS 1 I HIP write strobe/host data
strobe select input
HD15–0/
HAD15-0 16 I/O HIP data/data and address
HA2/ALE 1 I Host address 2/Address latch
enable input
HA1–0/
Unused 2 I Host addresses 1 and 0 inputs
SPORT0 5 I/O Serial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT1 5 I/O Serial port 1 I/O pins
or
IRQ1 (TFS1) 1 I External interrupt request #1
IRQ0 (RFS1) 1 I External interrupt request #0
SCLK1 1 O Programmable clock output
FO (DT1) 1 O Flag Output pin
FI (DR1) 1 I Flag Input pin
FL2–0 3 O General purpose flag output
pins
V
DD
GND 11 Ground pins
PWD 1 I Powerdown pin
PWDACK 1 O Powerdown acknowledge pin
Host Interface Port
The ADSP-217x host interface port is a parallel I/O port that allows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped peripheral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow communication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
• HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
• BMODE (when MMAP = 0) determines whether the ADSP217x boots from the host processor (through the HIP) or external EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
Tying these pins to appropriate values configures the ADSP217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional information refer to the ADSP-2100 Family User’s Manual.
HIP Operation
The HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed using either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
6 Power supply pins
–4–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-
pins,
cated pin; SPORT1 may be reconfigured for
IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are internally prioritized and individually maskable (except powerdown and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external interrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking precedence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
Table II. Interrupt Priority & Interrupt Vector Addresses
Interrupt Vector
Source of Interrupt Address (Hex)
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Powerdown (Nonmaskable) 002C
IRQ2 0004
HIP Write 0008
HIP Read 000C
SPORT0 Transmit 0010
SPORT0 Receive 0014
Software Interrupt 1 0018
Software Interrupt 0 001C
SPORT1 Transmit or
SPORT1 Receive or
IRQ1 0020
IRQ0 0024
Timer 0028 (Lowest Priority)
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enabled.
ICNTL
43210
0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1 = enable, 0 = disable
INTERRUPT FORCE
SPORT0 Transmit
SPORT0 Receive
IRQ2
Software 1
Software 0
Timer
1 = edge
0 = level
IMASK
101112131415 9876543210
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IFC
9876543210101112131415
0000000000000 000
Figure 2. Interrupt Registers
1 = enable, 0 = disable0000000000000000
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
INTERRUPT CLEAR
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
REV. A
–5–
ADSP-2171/ADSP-2172/ADSP-2173
LOW POWER OPERATION
The ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Powerdown
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
Powerdown
The ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hardware or software control. Here is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
• Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100 µA in some modes.
• Quick recovery from powerdown. The processor begins executing instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 100 CLKIN cycle startup.
• Powerdown is initiated by either the powerdown pin (
or the software powerdown force bit.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
powerdown state.
RESET pin also can be used to terminate powerdown,
• The
and the host software reset feature can be used to terminate
powerdown under certain conditions.
• Powerdown acknowledge pin indicates when the processor has
entered powerdown.
Idle
When the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during IDLE, further
reducing power consumption. The reduced clock frequency, a
PWD)
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 3 shows a basic system configuration with the ADSP217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be supported. Programmable wait state generation allows the processor
to interface easily to slow memories. The ADSP-217x also provides one external interrupt and two serial ports or three external interrupts and one serial port.
Clock Signals
The ADSP-217x can be clocked by either a crystal or by a TTLcompatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation. The only exception is while the processor is in the Powerdown State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this powerdown feature.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
–6–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
CLOCK OR
CRYSTAL
CLKIN
CLKOUT
RESET
IRQ2
BR
BG
MMAP
3
FL2-0
A
PROGRAM
(OPTIONAL)
NOTE:
THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS.
THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512.
24
D
MEMORY
XTAL
CS
OE
WE
PWD
PWDACK
RD WR
6
97
V
GND
DD
ADSP-217x
ADDRESSPMS DMS
14
AD
DATA MEMORY
OE
PERIPHERALS
WE
(OPTIONAL)
DATA
24
D
16
4
HOST
MODE
23-8
&
CS
16
HIP
SERIAL
PORT 0
SERIAL
PORT 1
BMS
HIP CONTROL
HIP DATA/ADDR
SCLK
RFS
TFS
DT
DR
SCLK
RFS or IRQ0
TFS or IRQ1
DT or FO
DR or FI
D
23-22
14
2
A
BOOT MEMORY
OE
D
15-8
8
D
e.g., EPROM
27C64
27C128
27C256
27C512
HOST
PROCESSOR
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
CS
Figure 3. ADSP-217x Basic System Configuration
Because the ADSP-217x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
CLKIN CLKOUT
ADSP-217x
XTAL
Figure 4. External Crystal Connections
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
Reset
The RESET signal initiates a master reset of the ADSP-217x.
RESET signal must be asserted during the power-up se-
The
quence to assure proper initialization.
RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the
any subsequent resets, the
mum pulse width specification, t
The
RESET input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET signal should be held low. On
RESET signal must meet the mini-
.
RSP
RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT register. When
RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000.
REV. A
–7–
ADSP-2171/ADSP-2172/ADSP-2173
Program Memory Interface
The on-chip program memory address bus (PMA) and the onchip program memory data bus (PMD) are multiplexed with
on-chip DMA and DMD buses, creating a single external data
bus and a single external address bus. The 14-bit address bus
directly addresses up to 16K words. 10K words of memory for
ADSP-217x with optional 8K ROM and 2K words of memory
for the non-ROM version are on-chip. The data bus is bidirectional and 24 bits wide to external program memory. Program
memory may contain code and data.
The program memory data lines are bidirectional. The program
memory select (
memory and can be used as a chip select signal. The write (
PMS) signal indicates access to the program
WR)
signal indicates a write operation and is used as a write strobe.
The read (
RD) signal indicates a read operation and is used as a
read strobe or output enable signal.
The ADSP-217x writes data from its 16-bit registers to the 24-
bit program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are
placed in the PX register.
Program Memory Maps
ADSP-217x
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 5 shows the different configurations. When MMAP = 0, internal RAM occupies 2K words beginning at address 0x0000. In this configuration, the boot
loading sequence (described in “Boot Memory Interface”) is automatically initiated when
2K
INTERNAL RAM
BOOTED
8K
INTERNAL ROM
(ROMENABLE = 1)
OR
8K
EXTERNAL
(ROMENABLE = 0)
6K
EXTERNAL
MMAP = 0
BMODE = 0 or 1
0000
07FF
0800
27FF
2800
3FFF
RESET is released.
2K
EXTERNAL
8K
INTERNAL ROM
(ROMENABLE = 1)
OR
8K
EXTERNAL
(ROMENABLE = 0)
4K
EXTERNAL
2K
INTERNAL RAM
MMAP = 1
BMODE = 0
0000
07FF
0800
27FF
2800
37FF
3800
3FFF
2K
INTERNAL RAM
NOT BOOTED
8K
INTERNAL ROM
(ROMENABLE
DEFAULTS
TO 1
DURING RESET)
6K
EXTERNAL
MMAP = 1
BMODE = 1
0000
07FF
0800
27FF
2800
3FFF
Figure 5. ADSP-217x Memory Maps
When MMAP = 1, words of external program memory begin at
address 0x0000 and internal RAM is located in the upper 2K
words, beginning at address 0x3800. In this configuration, program memory is not loaded although it can be written to and
read from under program control.
The optional ROM always resides at locations PM[0x0800]
through PM[0x27FF] regardless of the state of the MMAP pin.
The ROM is enabled by setting the ROMENABLE bit in the
Data Memory Wait State control register, DM[0x3FFE]. When
the ROMENABLE bit is set to 1, addressing program memory
in this range will access the on-chip ROM. When set to zero,
addressing program memory in this range will access external
program memory. The ROMENABLE bit is set to 0 on chip reset unless MMAP and BMODE = 1.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
Boot Memory Interface
The ADSP-217x can load on-chip memory from external boot
memory space. The boot memory space consists of 64K by 8-bit
space, divided into eight separate 8K by 8-bit pages. Three bits
in the system control register select which page is loaded by the
boot memory interface. Another bit in the system control register allows the user to force a boot loading sequence under software control. Boot loading from page 0 after
RESET is initiated
automatically if MMAP = 0.
The boot memory interface can generate 0 to 7 wait states; it
defaults to 7 wait states after
RESET. This allows the ADSP217x to boot from a single low cost EPROM such as a 27C256.
Program memory is booted one byte at a time and converted to
24-bit program memory words.
BMS and RD signals are used to select and to strobe the
The
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8–D15. To accommodate addressing up to eight
pages of boot memory, the two MSBs of the data bus are used
in the boot memory interface as the two MSBs of the boot space
address.
The ADSP-2100 Family Assembler and Linker support the creation of programs and data structures requiring multiple boot
pages during execution.
RD and WR must always be qualified by PMS, DMS, or BMS
to ensure the correct program, data, or boot memory accessing.
HIP Booting
The ADSP-217x can also boot programs through its Host Interface Port. If BMODE = 1 and MMAP = 0, the ADSP-217x
boots from the HIP. If BMODE = 0, the ADSP-217x boots
through the data bus (in the same way as the ADSP-2101), as
described above in “Boot Memory Interface.” For additional information about HIP booting, refer to the ADSP-2100 Family
User’s Manual, Chapter 7, “Host Interface Port.”
The ADSP-2100 Family Development Software includes a utility program called the HIP Splitter. This utility allows the creation of programs that can be booted via the ADSP-217x’s HIP,
in a similar fashion as EPROM-bootable programs generated by
the PROM Splitter utility.
–8–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
3BFF
3C00
37FF
3800
DATA MEMORY
12K
EXTERNAL
3FFF
0000
2FFF
3000
1K
RESERVED
MEMORY MAPPED
REGISTERS/
RESERVED
2K
INTERNAL
DATA RAM
03FF
0400
07FF
0800
WAIT STATES
DWAIT 2
(10K EXTERNAL)
3FFF
0000
2FFF
3000
NO WAIT
STATES
DWAIT 0
(1K EXTERNAL)
DWAIT 1
(1K EXTERNAL)
Stand-Alone ROM Execution
When the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
Table III. Boot Summary Table
BMODE = 0 BMODE = 1
MMAP = 0 Boot from EPROM, Boot from HIP, then
then execution starts execution starts at
at internal RAM internal RAM location
location 0x0000 0x0000
MMAP = 1 No booting, execution Stand-Alone Mode,
starts at external memory execution starts at
location 0x0000 internal ROM location
0x0800
Ordering Procedure for ADSP-2172 Processors
To place an order for a custom ROM-coded ADSP-2172 processor, you must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-2172 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-production ROM Products.
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering charges (NRE) associated with ROM product
development.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks are
identical, and recalculates the checksums for the .EXE file entered into the ROM Manager System. The checksum data, in the
form of a ROM memory map, a hard copy of the .EXE file, and a
ROM Data Verification Form are returned to you for inspection.
A signed ROM Verification Form and a purchase order for production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum
order quantity.
REV. A
Upon completion of the prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
Data Memory Interface
The data memory address (DMA) bus is 14 bits wide. The bidirectional external data bus is 24 bits wide, with the upper 16
bits (D8–D23) used for data memory data (DMD) transfers.
The data memory select (
DMS) signal indicates access to the
data memory and can be used as a chip select signal. The write
WR) signal indicates a write operation and can be used as a
(
write strobe. The read (
RD) signal indicates a read operation
and can be used as a read strobe or output enable signal.
The ADSP-217x supports memory-mapped I/O, with the pe-
ripherals memory mapped into the data or program memory address spaces and accessed by the processor in the same manner.
Data Memory Map
The on-chip data memory RAM resides in the 2K words of data
memory beginning at address 0x3000, as shown in Figure 6. In
addition, data memory locations from 0x3800 to the end of data
memory at 0x3FFF are reserved. Control registers for the system, timer, wait state configuration, host interface port, and serial port operations are located in this region of memory.
Figure 6. ADSP-217x Data Memory Map
The remaining 12K of data memory is external. External data
memory is divided into three zones, each associated with its own
wait state generator. By mapping peripherals into different
zones, you can accommodate peripherals with different wait
state requirements. All zones default to 7 wait states after
RESET. For compatibility with other ADSP-2100 Family processors, bit definitions for DWAIT 3 and DWAIT4 are shown
in the Data Memory Wait State Control Register, but they are
not used by the ADSP-217x.
–9–
ADSP-2171/ADSP-2172/ADSP-2173
Bus Request & Bus Grant
The ADSP-217x can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (
BR) signal. If the
ADSP-217x is not performing an external memory access, then
it responds to the active
BR input in the following processor
cycle by:
• three-stating the data and address buses and the
PMS, DMS,
BMS, RD, WR output drivers,
• asserting the bus grant (
BG) signal, and
• halting program execution.
If the Go Mode is enabled, the ADSP-217x will not halt pro-
gram execution until it encounters an instruction that requires
an external memory access.
If the ADSP-217x is performing an external memory access
when the external device asserts the
three-state the memory interfaces or assert the
BR signal, then it will not
BG signal until
the processor cycle after the access completes, which can be up
to eight cycles later depending on the number of wait states.
The instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses.
When the
BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when
The new Bus Grant Hang logic and associated
RESET is active.
BGH pin allow
the ADSP-217x to operate in a multiprocessor environment
with a minimal number of “wasted” processor cycles. The bus
grant hang pin is asserted when the ADSP-217x desires a cycle,
but cannot execute it because the bus is granted to some other
processor. With the
BGH signal, the other processor(s) in the
system can be alerted that the ADSP-217x is hung and release
the bus by deasserting bus request. Once the bus is released the
ADSP-217x executes the external access and deasserts
BGH.
This is a signal to the other processors that external memory is
now available.
ADSP-217X REGISTERS
Figure 7 summarizes all the registers in the ADSP-217x. Some
registers store values. For example, AX0 stores an ALU operand; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example, ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the numbers of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except for IMASK, ICNTL and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory; that is, registers are accessed by
reading and writing data memory locations rather than register
names. The particular data memory address is shown with each
memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeterminate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
AX0
DAG 1
I0
I1
I2
I3
PROGRAM SEQUENCER
ICNTL
SSTAT
M0
M1
M2
M3
ALU
DAG 2
L0
L1
L2
L3
M4
I4
M5
I5
M6
I6
M7
I7
AY1AY0AX1
MX0 MX1 MY0 MY1
AFAR
MR0 MR1 MFMR2
CNTR
OWRCNTR
L4
L5
COUNT
STACK
L6
4 X 14
L7
MAC
IFC
IMASK
MSTAT
ASTAT
STATUS
STACK
12 X 25
SI SE SB
SHIFTER
SR0 SR1
LOOP
STACK
4 X 18
PC
STACK
16 X 14
14
14
24
16
PMA BUS
DMA BUS
PMD BUS
DMD BUS
0x3FFF
SYSTEM CONTROL
0x3FFE
DM WAIT CONTROL
PX
TX0
RX0
0x3FFA-0x3FF3
CONTROL REGISTERS
SPORT 0
PROGRAM
ROM
8K X 24
PROGRAM
SRAM
2K X 24
RX1 TX1
0x3FF2-0x3FEF
CONTROL REGISTERS
SPORT 1
DATA
SRAM
2K X 16
0x3FFD
0x3FFC
0x3FFB
TIMER
TPERIOD
TCOUNT
TSCALE
HOST
INTERFACE
PORT
0x3FE0-0x3FE5
0x3FE6-0x3FE7
0x3FE8
POWERDOWN
DATA
STATUS
HMASK
FLAGS
CONTROL
LOGIC
Figure 7. ADSP-217x Registers Control Register
–10–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
ASTAT
76543210
00000000
AZ ALU Result Zero
AN ALU Result Negative
AV ALU Overflow
AC ALU Carry
AS ALU X Input Sign
AQ ALU Quotient
MV MAC Overflow
SS Shifter Input Sign
MSTAT
6543210
0000000
SSTAT (Read-Only)
76543210
10101010
PC Stack Empty
PC Stack Overflow
Count Stack Empty
Count Stack Overflow
Status Stack Empty
Status Stack Overflow
Loop Stack Empty
Loop Stack Overflow
Data Register Bank Select
0 = primary, 1 = secondary
Bit Reverse Mode Enable (DAG1)
ALU Overflow Latch Mode Enable
AR Saturation Mode Enable
MAC Result Placement
0 = fractional, 1 = integer
Timer Enable
Go Mode Enable
1514131211109876543210
SPORT0 Enable
1 = enabled, 0 = disabled
SPORT1 Enable
1 = enabled, 0 = disabled
SPORT1 Configure
1 = serial port
0 = FI, FO, IRQ0, IRQ1, SCLK
1514131211109876543210
System Control Register
0x3FFF
1010000011111000
BWAIT
BPAGE
Boot Page Select
BFORCE
Boot Force Bit
Boot Wait States
Timer Registers
TPERIOD Period Register
TCOUNT Counter Register
00000000
TSCALE Scaling Register
PWAIT
Program Memory
Wait States
0x3FFD
0x3FFC
0x3FFB
REV. A
Control Registers
–11–
ADSP-2171/ADSP-2172/ADSP-2173
ROM Enable/Data Memory Wait State
1514131211109876543210
DWAIT4 DWAIT0DWAIT1DWAIT2DWAIT3
ROM enable
1 = enable
0 = disable
Control Register
0x3FFE
1111111011111111
SPORT0 Multichannel Receive Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
0x3FFA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x3FF9
1514131211109876543210
1514131211109876543210
Multichannel Enable MCE
Internal Serial Clock Generation ISCLK
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Multichannel Frame Delay MFD
Only If Multichannel Mode Enabled
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
ITFS Internal Transmit Frame Sync Enable
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Only If Multichannel Mode Enabled)
SPORT0 Multichannel Transmit Word Enable Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
SPORT0 Control Register
0x3FF6
0000000000000000
1 = Channel Enabled
0 = Channel Ignored
0x3FF8
0x3FF7
SLEN Serial Word Length
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
Only If Multichannel Mode Enabled)
IRFS Internal Receive Frame Sync Enable
Control Registers
–12–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
SPORT0 SCLKDIV
Serial Clock Divide Modulus
0x3FF5
1514131211109876543210
SPORT0 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF4
1514131211109876543210
SPORT0 Autobuffer Control Register
0x3FF3
1514131211109876543210
000000
CLKOUT Disable Control Bit
CLKODIS
BIASRND
MAC Biased Rounding Control Bit
TIREG
Transmit Autobuffer I Register
TMREG
Transmit Autobuffer M Register
Flag Out (Read Only)
Internal Serial Clock Generation ISCLK
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
ITFS Internal Transmit Frame Sync Enable
RBUF
Receive Autobuffering Enable
TBUF
Transmit Autobuffering Enable
RMREG
Receive Autobuffer M Register
RIREG
Receive Autobuffer I Register
SPORT1 Control Register
0x3FF2
1514131211109876543210
000000000000000
SLEN Serial Word Length
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
IRFS Internal Receive Frame Sync Enable
REV. A
Control Registers
–13–
ADSP-2171/ADSP-2172/ADSP-2173
SPORT1 SCLKDIV
Serial Clock Divide Modulus
0x3FF1
1514131211109876543210
SPORT1 Autobuffer Control Register
1514131211109876543210
000000
XTALDIS
XTAL Pin Drive Disable
during Powerdown
1 = disabled, 0 = enabled
(disable XTAL pin when no external
crystal connected)
XTALDELAY
4096 Cycle Delay Enable
1 = delay, 0 = no delay
PDFORCE
Powerdown Force
PUCR
Powerup Context Reset Enable
1 = soft reset (context clear),
0 = resume execution
SPORT1 RFSDIV
Receive Frame Sync Divide Modulus
0x3FF0
1514131211109876543210
0x3FEF
RBUF
Receive Autobuffer Enable
TBUF
Transmit Autobuffer Enable
RMREG
Receive M Register
RIREG
Receive I Register
TMREG
Transmit M Register
TIREG
Transmit I Register
HIP Data Registers
HDR5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDR4
HDR3
HDR2
HDR1
HDR0
0x3FE5
0x3FE4
0x3FE3
0x3FE2
0x3FE1
0x3FE0
HMASK Register
0x3FE8
1514131211109876543210
0000000000000000
Host HDR5
Read
Host HDR4
Read
Host HDR3
Read
Host HDR2
Read
Host HDR1
Read
Host HDR0
Read
Interrupt Enables
1 = Enable
0 = Disable
Control Registers
Host HDR0
Write
Host HDR1
Write
Host HDR2
Write
Host HDR3
Write
Host HDR4
Write
Host HDR5
Write
–14–
REV. A
ADSP-2171/ADSP-2172/ADSP-2173
HSR6
0x3FE6
1514131211109876543210
0000000000000000
2171 HDR5 Write
2171 HDR4 Write
2171 HDR3 Write
2171 HDR2 Write
2171 HDR1 Write
2171 HDR0 Write
Overwrite Mode
Software Reset
Host HDR0 Write
Host HDR1 Write
Host HDR2 Write
Host HDR3 Write
Host HDR4 Write
Host HDR5 Write
HSR7
0x3FE7
1514131211109876543210
0000000000000001
2171 HDR0 Write
2171 HDR1 Write
2171 HDR2 Write
2171 HDR3 Write
2171 HDR4 Write
2171 HDR5 Write
Control Registers
Biased Rounding
A new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
MR value before RND biased RND result unbiased RND result
00-0000-8000 00-0001-8000 00-0000-8000
00-0001-8000 00-0002-8000 00-0002-8000
00-0000-8001 00-0001-8001 00-0001-8001
00-0001-8001 00-0002-8001 00-0002-8001
00-0000-7FFF 00-0000-7FFF 00-0000-7FFF
00-0001-7FFF 00-0001-7FFF 00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit specified algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
INSTRUCTION SET DESCRIPTION
The ADSP-217x assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be relocated to utilize internal memory and conform to the ADSP217x’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle.
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference.
REV. A
–15–
ADSP-2171/ADSP-2172/ADSP-2173
Example Code
The following example is a code fragment that performs the
filter tap update for an adaptive (least-mean-squared algorithm)
filter. Notice that the computations in the instructions are
written like algebraic equations.
MF=MX0*MY1 (RND), MX0=DM (I2,M1); /* MF=error*beta */
MR=MX0*MF (RND), AY0=PM (I6,MS);
DO adapt UNTIL CE;
AR=MR1 + AY0, MX0=DM (I2,M1), AY0=PM (I6,M7);
adapt:
Interrupt Enable
The ADSP-217x supports an interrupt enable instruction. Interrupts are enabled by default at reset. The instruction source
code is specified as follows:
Syntax: ENA INTS;
Description: Executing the ENA INTS instruction allows all
Interrupt Disable
The ADSP-217x supports an interrupt disable instruction. The
instruction source code is specified as follows:
Syntax: DIS INTS;
Description: Reset enables interrupt servicing. Executing the
PM(I6,M6) =AR, MR=MX0*MF (RND);
MODIFY (I2, M3); /* Point to oldest data */
MODIFY (I6, M7); /* Point to start of data */
unmasked interrupts to be serviced again.
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
–16–
REV. A
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