Analog Devices ADSP-2164, ADSP-2166, ADSP-2165, ADSP-2163, ADSP-2161 Datasheet
a
SERIAL PORTS
SPORT 1SPORT 0
MEMORY
TIMER
SHIFTERMACALU
ARITHMETIC UNITS
DAG 2
DAG 1
DATA ADDRESS
GENERATORS
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUS
PROGRAM
MEMORY
DATA
MEMORY
DATA MEMORY DATA
DATA MEMORY ADDRESS
PROGRAM MEMORY ADDRESS
PROGRAM MEMORY DATA
PROGRAM
SEQUENCER
ADSP-2100 CORE
DSP Microcomputers with ROM
ADSP-216x
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus and Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction
Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
GENERAL DESCRIPTION
The ADSP-216x Family processors are single-chip microcomputers␣ optimized␣ for␣ digital␣ signal␣ processing␣ (DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architecture—computation units, data address generators and program
sequencer—with features such as␣ on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164 Custom ROM-programmed DSPs:
ADSP-2165/ADSP-2166 ROM-programmed ADSP-216x
processors with power-down and
larger on-chip memories (12K Pro-
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
gram Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
FUNCTIONAL BLOCK DIAGRAM
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x processors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can␣ perform␣ all of␣ the␣ following
operations:
•
␣ Generate the next program address
•
␣ Fetch the next instruction
•
␣ Perform one or two data moves
•
␣ Update one or two data address pointers
•
␣ Perform a computation
•
␣ Receive and transmit data via one or two serial ports
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire application program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
ADSP-216x
TABLE OF CONTENTS
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Procedure for ADSP-216x ROM Processors . . . . 10
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 14
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 15
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 15
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS–
␣ ␣ (ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 16
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 17
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 18
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 19
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 19
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TIMING PARAMETERS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 21
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 21
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 22
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . 23
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 24
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TIMING PARAMETERS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 28
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 28
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 29
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . . 30
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 31
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PIN CONFIGURATIONS
68-Lead PLCC (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 35
80-Lead MQFP (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 36
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
80-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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ADSP-216x
Table I. ADSP-216x ROM-Programmed Processor Features
Feature 2161 2162 2163 2164 2165 2166
Data Memory (RAM) 1/2K 1/2K 1/2K 1/2K 4K 4K
Program Memory (ROM) 8K 8K 4K 4K 12K 12K
Program Memory (RAM) 1K 1K
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Supply Voltage 5 V 3.3 V 5 V 3.3 V 5 V 3.3 V
Speed Grades (Instruction Cycle Time)
10.24 MHz (97.6 ns)
13.00 MHz (76.9 ns)
16.67 MHz (60 ns)
20.00 MHz (50 ns)
25 MHz (40 ns)
Packages
68-Lead PLCC
80-Lead MQFP
Temperature Grades
K Commercial, 0°C to +70°C
B Industrial, –40°C to +85°C
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Development Tools
The ADSP-216x processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Development Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-216x
processors. The ANSI C compiler generates ADSP-216x assembly source code, while the runtime C library provides ANSIstandard and custom DSP library routines. The ADSP-216x
assembler produces object code modules that the linker combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
®
EZ-ICE
systems by providing a full range of emulation functions such
as modification of memory and register values and execution
breakpoints. EZ-LAB
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information are available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Information
This data sheet provides a general overview of ADSP-216x
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, Third Edition, available from Analog Devices.
in-circuit emulators allow debugging of ADSP-21xx
®
demonstration boards are complete DSP
ARCHITECTURE OVERVIEW
Figure 1 shows a block diagram of the ADSP-216x architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract operations. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The
shifter can be used to efficiently implement numeric format control
including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-216x executes looped code with zero
overhead—no explicit jump instructions are required to maintain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) onchip memory.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
REV. 0
–3–
ADSP-216x
DATA
ADDRESS
GENERATOR
#1
INPUT REGS
OUTPUT REGS
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#2
PMA BUS
14
PMA BUS
14
PMA BUS
24
PMA BUS
16
INPUT REGS
ALU MAC SHIFTER
OUTPUT REGS
PROGRAM
SEQUENCER
16
R BUS
INPUT REGS
OUTPUT REGS
BUS
EXCHANGE
16
PROGRAM
MEMORY
SRAM
& ROM
24
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
Figure 1. ADSP-216x Block Diagram
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS and PMS signals indicate which memory space
is using the external buses.
Program memory can store both instructions and data, permitting the ADSP-216x to fetch two operands in a single cycle,
one from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
One bus grant execution mode (GO Mode) allows the ADSP216x to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-216x processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2161 to use a 200 ns EPROM as
DATA
MEMORY
SRAM
16
PMA BUS
DMA BUS
PMD BUS
DMD BUS
COMPANDING
CIRCUITRY
BOOT
ADDRESS
GENERATOR
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
55
TIMER
MUX
MUX
14
EXTERNAL
ADDRESS
BUS
24
EXTERNAL
DATA
BUS
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-216x processors include two synchronous serial
ports (SPORTs) for serial communications and multiprocessor
communication. All of the ADSP-216x processors have two
serial ports (SPORT0, SPORT1).
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of operation are available. Each SPORT can generate an internal programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name Function
SCLK Serial Clock (I/O)
RFS Receive Frame Synchronization (I/O)
TFS Transmit Frame Synchronization (I/O)
DR Serial Data Receive
DT Serial Data Transmit
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ADSP-216x
The ADSP-216x serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals internally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulsewidths and
timings.
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and µ-law companding according to CCITT recommen-
dation G.711.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0 provides a multichannel interface to selectively receive or transmit a
24-word or 32-word, time-division multiplexed serial bit stream;
this feature is especially useful for T1 or CEPT interfaces, or as
a network communication scheme for multiple processors.
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
Interrupts
The ADSP-216x’s interrupt controller lets the processor respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1 and IRQ2, are provided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-216x also supports internal interrupts from the timer and
the serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities for each ADSP-216x
processor are shown in Table II.
Table II.␣ Interrupt Vector Addresses and Priority
Interrupt
ADSP-216x Interrupt Source Vector Address
RESET Startup 0x0000
IRQ2 or Power-Down 0x0004 (High Priority)
SPORT0 Transmit 0x0008
SPORT0 Receive 0x000C
SPORT1 Transmit or IRQ1 0x0010
SPORT1 Receive or IRQ0 0x0014
Timer 0x0018 (Low Priority)
The ADSP-216x uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instructions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an additional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on Bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only register that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the interrupt instruction is executed.
Pin Definitions
Pin Function Descriptions show pin definitions for the ADSP216x processors. Any inputs not used must be tied to V
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-216x with two
serial I/O devices, an optional external program and data
memory. A total of 12K words of data memory and 15K words
of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-216x processors also provide either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock Signals
The ADSP-216x processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-216x processors include an on-chip oscillator circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallelresonant, fundamental frequency, microprocessor-grade crystal
should be used.
DD
.
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–5–
ADSP-216x
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
CLKIN CLKOUT
ADSP-216x
XTAL
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 t
cycles will ensure that the PLL has locked (this does
CK
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
Figure 2. External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET signal initiates a complete reset of the ADSP-216x.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
held low. On any subsequent resets, the RESET signal must
meet the minimum pulsewidth specification, t
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the chip
is configured for booting, with MMAP = 0). The first instruction is
then fetched from internal program memory location 0x0000.
not require this stabilization time.
PIN FUNCTION DESCRIPTIONS
Pin # of Input/
Name(s) Pins Output Function
Address 14 O Address outputs for program, data and boot memory.
Data
1
24 I/O Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
RESET 1 I Processor Reset Input
IRQ2 1 I External Interrupt Request #2
BR
2
1 I External Bus Request Input
BG 1 O External Bus Grant Output
PMS 1 O External Program Memory Select
DMS 1 O External Data Memory Select
BMS 1 O Boot Memory Select
RD 1 O External Memory Read Enable
WR 1 O External Memory Write Enable
MMAP 1 I Memory Map Select Input
CLKIN, XTAL 2 I External Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
V
DD
Power Supply Pins
GND Ground Pins
SPORT0 5 I/O Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
SPORT1 5 I/O Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
or Interrupts and Flags:
IRQ0 (RFS1) 1 I External Interrupt Request #0
IRQ1 (TFS1) 1 I External Interrupt Request #1
FI (DR1) 1 I Flag Input Pin
FO (DT1) 1 O Flag Output Pin
PWDACK
PWDFLAG
3
3
1 O Indicates when the processor has entered power-down.
1 I Low-to-High Transition of the Power-Down Flag. Input pin can
be used to terminate power-down.
NOTES
1
Unused data bus lines may be left floating.
2
BR must be tied high (to VDD) if not used.
3
Only on ADSP-2165/ADSP-2166.
RSP
DD
.
is
–6–
REV. 0
ADSP-216x
0x0000
2K
EXTERNAL
MMAP = 0
12K 3 24
INTERNAL
ROM
10K 3 24
INTERNAL
ROM
1K 3 24 RAM
RESERVED
2K 3 24
EXTERNAL
2K 3 24
INTERNAL
ROM
1K 3 24 RAM
RESERVED
MMAP = 1
0x2FFF
0x3000
0x33FF
0x3400
0x37FF
0x3800
0x3FFF
0x0000
0x2FFF
0x3000
0x33FF
0x3400
0x37FF
0x3800
0x3FFF
0x07FF
0x0800
MMAP = 0
8K
INTERNAL
ROM
RESERVED
MMAP = 1
0x0000
0x1FF0
0x1FFF
0x2000
0x3FFF
2K
EXTERNAL
RESERVED
0x0000
0x1FF0
0x1FFF
0x2000
0x3FFF
6K
INTERNAL
ROM
6K
EXTERNAL
2K
INTERNAL
ROM
0x7FFF
0x0800
0x37FF
0x3800
8K
EXTERNAL
CLOCK OR
CRYSTAL
34
CLKIN XTAL CLKOUT V
RESET
IRQ2
OE
WE
ADSP-216x
ADDRESS DATA
RW
BR
BG
MMAP
PMS RD DMS BMS
AD
CS
PROGRAM
MEMORY
(OPTIONAL)
DD
14
AD
OE
WE
DATA
MEMORY
&
PERIPHERALS
GND
SERIAL
PORT 0
SERIAL
PORT 1
24
D23-8
16
CS
SCLK
RFS
TFS
DT
DR
SCLK
RFS OR IRQ0
TFS OR IRQ1
DT OR FO
DR OR FI
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
Figure 3. Basic System Configuration
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
The external address bus is 14 bits wide. For the ADSP-216x,
these lines can directly address up to 16K words, of which 2K
are on-chip.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The ADSP-216x processors write data from their 16-bit registers to 24-bit program memory using the PX register to provide
the lower eight bits. When the processor reads 16-bit data from
24-bit program memory to a 16-bit data register, the lower eight
bits are placed in the PX register.
The program memory interface can generate 0 to 7 wait states for
external memory devices; default is to 7 wait states after RESET.
Program Memory Maps
Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 4 shows the program memory
map for the ADSP-2165/ADSP-2166. Figures 5 and 6 show the
program memory maps for the ADSP-2161/ADSP-2162 and
ADSP-2163/ADSP-2164, respectively.
REV. 0
–7–
ADSP-2165/ADSP-2166
When MMAP = 0, on-chip program memory ROM occupies
12K words beginning at address 0x0000. Internal program
memory RAM occupies 1K words beginning at address 0x3000.
Off-chip program memory uses the 2K words beginning at
address 0x3800. The ADSP-2165/ADSP-2166 does not support
boot memory.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 10K words of on-chip program memory
ROM at 0x800 to 0x2FFF, and the remainder 2K words of
program memory ROM is at 0x3800 to 0x3FFF. Internal program memory RAM occupies 1K words at address 0x300 to
0x33FF.
Figure 4. ADSP-2165/ADSP-2166 Program Memory Maps
ADSP-2161/ADSP-2162
When MMAP = 0, on-chip program memory ROM occupies
8K words beginning at address 0x0000. Off-chip program
memory uses the remaining 8K words beginning at address
0x2000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 6K words of on-chip program memory ROM
are at 0x0800 to 0x1FF0, and the remainder 2K words of program memory ROM is at 0x3800 to 0x3FFF. An additional 6K
of off-chip program memory is at 0x2000 to 0x37FF.
Figure 5. ADSP-2161/ADSP-2162 Program Memory Maps
ADSP-216x
0x0000
4K 3 16
MEMORY-MAPPED
REGISTERS
& RESERVED
0x0800
ADDRESS (HEX)
4K 3 16 INTERNAL
6K EXTERNAL
DWAIT2
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
0x0400
0x2000
0x3000
0x3FFF
EXTERNAL
RAM
INTERNAL
RAM
0x0000
512
ADSP-2161/62/63/64
0x0800
ADDRESS (HEX)
10K EXTERNAL
DWAIT2
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
0x0400
0x3000
0x3C00
0x3FFF
EXTERNAL
RAM
INTERNAL
RAM
1K EXTERNAL
DWAIT3
1K EXTERNAL
DWAIT4
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
0x3A00
0x3800
0x3400
ADSP-2163/ADSP-2164
When MMAP = 0, on-chip program memory ROM occupies
4K words beginning at address 0x0000. Off-chip program
memory uses the remaining 12K words beginning at address
0x1000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 2K words of on-chip program memory ROM
is at 0x0800 to 0x0FF0, and the remainder 2K words of program memory ROM is at 0x3800 to 0x3FFF. An additional
10K of off-chip program memory is at 0x1000 to 0x37FF.
Figure 6. ADSP-2163/ADSP-2164 Program Memory Maps
Data Memory Interface
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-216x processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
Data Memory Map
For the ADSP-2165/ADSP-2166, on-chip data memory RAM
resides in the 4K words beginning at address 0x2000, as shown
in Figure 7. Data memory locations from 0x3000 to the end of
data memory at 0x3FFF are reserved. Control and status registers for the system, timer, wait-state configuration, and serial port
operations are located in this region of memory.
The remaining 8K of data memory is located off-chip. This
external data memory is divided into three zones, each associated with its own wait-state generator. This allows slower peripherals to be memory-mapped into data memory for which
wait states are specified. By mapping peripherals into different
zones, you can accommodate peripherals with different waitstate requirements. All zones default to 7 wait states after
RESET.
INTERNAL
RESERVED
EXTERNAL
MMAP = 0
4K
ROM
12K
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
2K
EXTERNAL
2K
INTERNAL
ROM
RESERVED
10K
EXTERNAL
2K
INTERNAL
ROM
MMAP = 1
0x0000
0x07FF
0x0800
0x0FF0
0x0FFF
0x1000
0x37FF
0x3800
0x3FFF
Figure 7. ADSP-2165/ADSP-2166 Data Memory Map
ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, onchip data memory RAM resides in the 512 words beginning at
address 0x3800, also shown in Figure 8. Data memory locations
from 0x3A00 to the end of data memory at 0x3FFF are reserved.
Control and status registers for the system, timer, wait-state
configuration, and serial port operations are located in this
region of memory.
Figure 8. ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state requirements. All zones default to seven wait states after RESET.
–8–
REV. 0
ADSP-216x
Bus Interface
The ADSP-216x processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-216x is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
• Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and halting program
execution.
If the Go mode is set, however, the ADSP-216x will not halt
program execution until it encounters an instruction that
requires an external memory access.
If the ADSP-216x is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depending on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus between two memory accesses if an instruction
requires more than one external memory access.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active. If this feature is
not used, the BR input should be tied high (to V
POWER-DOWN
The ADSP-2165/ADSP-2166 processors have a low power
feature that lets the processor enter a very low power dormant
state through hardware or software control. A list of powerdown features follows:
• Processor registers and on-chip memory contents are maintained during power-down.
• Power-down mode holds the processor in CMOS standby
with a maximum current of less than 100 µA in some modes.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating.
• Support for crystal operation includes disabling the oscillator
to save power. (The processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabilize).
• When power-down mode is enabled, powering down of the
processor can be initiated either by externally generated
IRQ2 interrupt or by using the IRQ2 force bit in the IFC
register.
• Power-Down Acknowledge Pin (PWDACK) indicates when
the processor has entered power-down.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
DD
).
• Low-to-high transition of the power-down flag input pin
(PWDFLAG) can be used to terminate power-down.
• The RESET pin also can also be used to terminate
power-down.
Power-Down Control
Several parameters of power-down operation can be controlled
through control bits of the “power-down/sportl autobuffer control register.” This control register is memory-mapped at location 0x3FEF and the power-down control bits are as follows:
bit[15] xtal: xtal pin disable during power-down
1 = disabled, 0 = enable (default)
bit[14] pwdflag: (read only )
when pwdena = 1, the value of bit [14] pwdflag is equal to the
status of the pwdflag input pin.
when pwdena = 0, the value of bit [14] pwdflag is equal to 0.
bit[13] pwdena: power-down enable
1 = enable, 0 = disable (default)
if pwdena is set to 0, then the output pin PWDACK is driven
low and the input pin PWDFLAG is disabled
Note: It is not recommended that power-down enable be set or
cleared during an IRQ2 interrupt.
bit[12] pucr: power-up context reset
1 = soft reset, 0 = resume execution (default)
Entering Power-Down
The power-down sequence is defined as follows:
• Enable power-down logic by setting the pwdena bit in the
power-down/sportl autobuffer control register.
Note: In order to power-down, the PWDENA bit must be set
before the IRQ2 interrupt is initiated.
• Initiate the power-down sequence by generating an IRQ2
interrupt either externally or by software use of the IFC
register.
• The processor vectors to the IRQ2 interrupt vector located at
0x0004.
• Any number of housekeeping instructions, starting at location 0x0004 can be executed prior to the processor entering
the power-down mode.
• The processor enters the power-down mode when the processor executes an IDLE instruction while executing the
IRQ2 interrupt routine.
Notes:
• If an RTI instruction is executed before the processor encounter an IDLE instruction, then the processor returns
from the IRQ2 interrupt and the power-down sequence is
aborted.
• The user can differentiate between a “normal” IRQ2 interrupt and a “power-down” IRQ2 interrupt by resetting the
PWDFLAG pin and checking the status of this pin by testing
the PWDFLAG bit in the power-down/SPORT1 autobuffer
control register located at DM[0x3FEF].
REV. 0
–9–
ADSP-216x
Exiting Power-Down
The power-down mode can be exited with the use of the
PWDFLAG or RESET pin. Applying a low-to-high transition to
the PWDFLAG pin takes the processor out of power-down
mode. In this case, a delay of 4096 cycles is automatically induced by the processor. Also, depending on the status of the
power-up context reset bit (pucr), the processor either
1) continues to execute instructions following the IDLE instruction that caused the power-down. A RTI instruction is required to pass control back to the main routine (pucr = 0)
or
2) resumes operation from power-down by clearing the PC,
STATUS, LOOP and CNTR stack. The IMASK and
ASTAT registers are set to 0 and the SSTAT goes to 0x55.
The processor then starts executing instructions from the
address zero (pucr = 1).
In the case where the power-down mode is exited by asserting
the RESET pin, the processor state is reset and instruction are
executed from address 0x0000. The RESET pin in this case
must be held low long enough for the external crystal (if any)
and the on-chip PLL to stabilize and lock.
Low Power IDLE Instruction
The IDLE instruction places the ADSP-216x processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. Typically this next instruction will be a JUMP
back to the IDLE instruction. This implements a low power
standby loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
IDLE n;
where n = 16, 32, 64 or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an enabled interrupt, the processor will stay in the IDLE state for up
to a maximum of n CLKIN cycles, where n is the divisor specified in the instruction, before resuming normal operation.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is increased
by n, the clock divisor. When an enabled interrupt is received,
the ADSP-216x will remain in the IDLE state for up to a maximum of n CLKIN cycles (where n = 16, 32, 64 or 128) before
resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
ADSP-216x Prototyping
You can prototype your ADSP-216x system with either ADSP2101 or ADSP-2103 RAM-based processors. When code is fully
developed and debugged, it can be submitted to Analog Devices
for conversion into an ADSP-216x ROM product.
The ADSP-2101 EZ-ICE emulator can be used for development
of ADSP-216x systems. For the 3.3 V ADSP-2162/ADSP-2164
and ADSP-2166, a voltage converter interface board provides
3.3 V emulation.
Additional overlay memory is used for emulation of ADSP2161/ADSP-2162 systems. It should be noted that due to the
use of off-chip overlay memory to emulate the ADSP-2161/
ADSP-2162, a performance loss may be experienced when both
executing instructions and fetching program memory data from
the off-chip overlay memory in the same cycle. This can be
overcome by locating program memory data in on-chip memory.
Ordering Procedure for ADSP-216x ROM Processors
To place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP2166 processor, you must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Preproduction ROM Products
2. Return the forms to Analog Devices along with two copies of the
Memory Image File (.EXE file) of your ROM code. The files must
be supplied on two 3.5" or 5.25" floppy disks for the IBM PC
(DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being manufactured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
–10–
REV. 0
ADSP-216x
Instruction Set
The ADSP-216x assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
Every instruction assembles into a single 24-bit word and executes
in a single cycle. The instructions encompass a wide variety of
instruction types along with a high degree of operational
ALU Instructions
parallelism. There are five basic categories of instructions: data
move instructions, computational instructions, multifunction
instructions, program flow control instructions and miscellaneous instructions. Multifunction instructions perform one or
two data moves and a computation.
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
[IF cond] AR|AF = xop + yop [+ C] ; Add/Add with Carry
= xop – yop [+ C– 1] ; Subtract X – Y/Subtract X – Y with Borrow
= yop – xop [+ C– 1] ; Subtract Y – X/Subtract Y – X with Borrow
= xop AND yop ; AND
= xop OR yop ; OR
= xop XOR yop ; XOR
= PASS xop ; Pass, Clear
= – xop ; Negate
= NOT xop ; NOT
= ABS xop ; Absolute Value
= yop + 1 ; Increment
= yop – 1 ; Decrement
= DIVS yop, xop ; Divide
= DIVQ xop ;
MAC Instructions
[IF cond] MR|MF = xop * yop ; Multiply
= MR + xop
= MR – xop
yop ; Multiply/Accumulate
*
yop ; Multiply/Subtract
*
= MR ; Transfer MR
=0 ; Clear
IF MV SAT MR ; Conditional MR Saturation
Shifter Instructions
[IF cond] SR = [SR OR] ASHIFT xop ; Arithmetic Shift
[IF cond] SR = [SR OR] LSHIFT xop ; Logical Shift
SR = [SR OR] ASHIFT xop BY <exp>; Arithmetic Shift Immediate
SR = [SR OR] LSHIFT xop BY <exp>; Logical Shift Immediate
[IF cond] SE = EXP xop ; Derive Exponent
[IF cond] SB = EXPADJ xop ; Block Exponent Adjust
[IF cond] SR = [SR OR] NORM xop ; Normalize
Data Move Instructions
reg = reg ; Register-to-Register Move
reg = <data> ; Load Register Immediate
reg = DM (<addr>) ; Data Memory Read (Direct Address)
dreg = DM (Ix , My) ; Data Memory Read (Indirect Address)
dreg = PM (Ix , My) ; Program Memory Read (Indirect Address)
DM (<addr>) = reg ; Data Memory Write (Direct Address)
DM (Ix , My) = dreg ; Data Memory Write (Indirect Address)
PM (Ix , My) = dreg ; Program Memory Write (Indirect Address)
Multifunction Instructions
<ALU>|<MAC>|<SHIFT> , dreg = dreg ; Computation with Register-to-Register Move
<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ; Computation with Memory Read
<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ; Computation with Memory Read
DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ; Computation with Memory Write
PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ; Computation with Memory Write
dreg = DM (Ix , My) , dreg = PM (Ix , My) ; Data & Program Memory Read
<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ; ALU/MAC with Data & Program Memory Read
REV. 0
–11–
ADSP-216x
Program Flow Instructions
DO <addr> [UNTIL term] ; Do Until Loop
[IF cond] JUMP (Ix) ; Jump
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ; Call Subroutine
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN JUMP <addr>; Jump/Call on Flag In Pin
IF [NOT ] FLAG_IN CALL <addr>;
[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ; Modify Flag Out Pin
[IF cond] RTS ; Return from Subroutine
[IF cond] RTI ; Return from Interrupt Service Routine
IDLE [(n)] ; Idle
Miscellaneous Instructions
NOP ; No Operation
MODIFY (Ix , My); Modify Address Register
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ; Stack Control
ENA|DIS SEC_REG [, ...] ; Mode Control
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
Notation Conventions
Ix Index registers for indirect addressing
My Modify registers for indirect addressing
<data> Immediate data value
<addr> Immediate address value
<exp> Exponent (shift value) in shift immediate instructions (8-bit signed number)
<ALU> Any ALU instruction (except divide)
<MAC> Any multiply-accumulate instruction
<SHIFT> Any shift instruction (except shift immediate)
cond Condition code for conditional instruction
term Termination code for DO UNTIL loop
dreg Data register (of ALU, MAC, or Shifter)
reg Any register (including dregs)
; A semicolon terminates the instruction
, Commas separate multiple operations of a single instruction
[ ] Optional part of instruction
[, ...] Optional, multiple operations of an instruction
option1 | option2 List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0*MY1(RND), MX0=DM(I2,M1); {MF=error*beta}
MR=MX0*MF(RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt: PM(I6,M6)=AR, MR=MX0*MF(RND);
MODIFY(I2,M3); {Point to oldest data}
MODIFY(I6,M7); {Point to start of data}
–12–
REV. 0
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