Analog Devices AD9224ARS, AD9224-EB Datasheet

Complete 12-Bit, 40 MSPS

FEATURES Monolithic 12-Bit, 40 MSPS A/D Converter Low Power Dissipation: 415 mW Single +5 V Supply No Missing Codes Guaranteed Differential Nonlinearity Error: ⴞ0.33 LSB Complete On-Chip Sample-and-Hold Amplifier and

Voltage Reference Signal-to-Noise and Distortion Ratio: 68.3 dB Spurious-Free Dynamic Range: 81 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SSOP Package Compatible with 3 V Logic

PRODUCT DESCRIPTION

The AD9224 is a monolithic, single supply, 12-bit, 40 MSPS, analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9224 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 40 MSPS data rates, and guarantees no missing codes over the full operating temperature range.

The AD9224 combines a low cost high speed CMOS process and a novel architecture to achieve the resolution and speed of existing bipolar implementations at a fraction of the power consumption and cost.

The input of the AD9224 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications. The dynamic performance is excellent.

The sample-and-hold (SHA) amplifier is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate.

The AD9224’s wideband input, combined with the power and cost savings over previously available monolithics, is suitable for applications in communications, imaging and medical ultrasound.

The AD9224 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.

Monolithic A/D Converter

AD9224

FUNCTIONAL BLOCK DIAGRAM

AVDD

MDAC2

GAIN = 4

A/DA/D

DIGITAL CORRECTION LOGIC

OUTPUT BUFFERS

AVSS

VINA VINB

CML CAPT CAPB

VREF

SENSE

SHA

MODE

SELECT

MDAC1

GAIN = 16

REFCOM

CLK

A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow.

PRODUCT HIGHLIGHTS

The AD9224 is fabricated on a very cost effective CMOS process. High speed precision analog circuits are now combined with high density logic circuits.

The AD9224 offers a complete single-chip sampling 12-bit, 40 MSPS analog-to-digital conversion function in 28-lead SSOP package.

Low Power—The AD9224 at 415 mW consumes a fraction of the power of presently available in existing monolithic solutions.

On-Board Sample-and-Hold (SHA)—The versatile SHA input can be configured for either single-ended or differential inputs.

Out of Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9224’s input range.

Single Supply—The AD9224 uses a single +5 V power supply simplifying system power supply design. It also features a separate digital driver supply line to accommodate 3 V and 5 V logic families.

Pin Compatibility—The AD9224 is pin compatible with the AD9220, AD9221, AD9223 and AD9225 ADCs.

DRVDD

MDAC3

GAIN = 4

A/D

AD9224

DRVSS

A/D

OTR BIT 1

(MSB) BIT 12

(LSB)

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

AD9224–SPECIFICATIONS

DC SPECIFICATIONS

(AVDD = +5 V, DRVDD = +3 V, f

= 40 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T

SAMPLE

MIN

to T

unless otherwise noted)

MAX

Parameter Min Typ Max Units

RESOLUTION 12 Bits

MAX CONVERSION RATE 40 MHz

INPUT REFERRED NOISE

VREF = 1.0 V 0.35 LSB rms VREF = 2.0 V 0.17 LSB rms

ACCURACY

Integral Nonlinearity (INL) ±1.5 ±2.5 LSB Differential Nonlinearity (DNL) ±0.33 ±1.0 LSB

No Missing Codes Guaranteed 12 Bits

Zero Error (@ +25°C) ±0.12 ±0.3 % FSR Gain Error (@ +25°C) Gain Error (@ +25°C)

±0.3 ±2.2 % FSR ±0.4 ±1.6 % FSR

TEMPERATURE DRIFT

Zero Error ±2 ppm/°C

Gain Error Gain Error

±26 ppm/°C ±0.4 ppm/°C

POWER SUPPLY REJECTION

AVDD

(+5 V ± 0.25 V) ±0.07 ±0.24 % FSR

ANALOG INPUT

Input Span (VREF = 1 V) 2 V p-p

(VREF = 2 V) 4 V p-p Input (VINA or VINB) Range 0 AVDD V Input Capacitance 10 pF

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) 1.0 V

Output Voltage Tolerance (1 V Mode) ±5 ±17 mV

Output Voltage (2.0 V Mode) 2.0 V

Output Voltage Tolerance (2.0 V Mode) ±10 ±35 mV

Output Current (Available for External Loads) 1.0 mA Load Regulation

±1.0 ±3.4 mV

REFERENCE INPUT RESISTANCE 5 kΩ

POWER SUPPLIES

Supply Voltages

AVDD 4.75 5 5.25 V (±5% AVDD DRVDD 2.85 5.25 V (±5% DRVDD

Operating)

Supply Current

IAVDD 82 87 mA (2 V Internal VREF) IDRVDD 4.3 5 mA (2 V Internal VREF)

POWER CONSUMPTION 415 445 mW (1 V Internal Ref)

425 450 mW (2 V Internal Ref)

NOTES

Includes internal voltage reference error.

Excludes internal voltage reference error.

Load regulation with 1 mA load current (in addition to that required by the AD9224).

Specifications subject to change without notice.

–2–

REV. A

AD9224

AC SPECIFICATIONS

Parameter Min Typ Max Units

SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)

= 2.5 MHz 65 68.3 dB

INPUT

= 10 MHz 63.5 68.0 dB

INPUT

SIGNAL-TO-NOISE RATIO (SNR)

= 2.5 MHz 65.3 69.1 dB

INPUT

= 10 MHz 64.6 68.4 dB

INPUT

TOTAL HARMONIC DISTORTION (THD)

= 2.5 MHz –80 –71 dB

INPUT

= 10 MHz –78 –67.4 dB

INPUT

SPURIOUS FREE DYNAMIC RANGE

= 2.5 MHz 71.1 81 dB

INPUT

= 10 MHz 67.9 79 dB

INPUT

Full Power Bandwidth 120 MHz Small Signal Bandwidth 120 MHz Aperture Delay 1ns Aperture Jitter 4 ps rms

Specifications subject to change without notice.

(AVDD = +5 V, DRVDD = +3 V, f

= 40 MSPS, VREF = 2.0 V, T

SAMPLE

MIN

to T

, Differential Input unless otherwise noted)

MAX

DIGITAL SPECIFICATIONS

(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)

Parameters Symbol Min Typ Max Units

LOGIC INPUTS

High Level Input Voltage V Low Level Input Voltage V High Level Input Current (V Low Level Input Current (V

= DRVDD) I

= 0 V) I

Input Capacitance C

+3.5 V

+1.0 V

–10 +10 µA –10 +10 µA

5pF

LOGIC OUTPUTS (With DRVDD = 5 V)

High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I Output Capacitance C

= 50 µA) V

= 0.5 mA) V

= 1.6 mA) V

= 50 µA) V

OUT

+4.5 V +2.4 V

+0.4 V +0.1 V

5pF

LOGIC OUTPUTS (With DRVDD = 3 V)

High Level Output Voltage (I High Level Output Voltage (I Low Level Output Voltage (I Low Level Output Voltage (I

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

= 50 µA) V

= 0.5 mA) V

= 1.6 mA) V

= 50 µA) V

to T

MIN

MAX

+2.95 V +2.80 V

with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF)

+0.4 V +0.05 V

Parameters Symbol Min Typ Max Units

Clock Period CLOCK Pulsewidth High CLOCK Pulsewidth Low t Output Delay t

25 ns

12.37 ns

12.37 ns 13 ns

Pipeline Delay (Latency) 3 Clock Cycles

NOTES

The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.

For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.

Specifications subject to change without notice.

–3–REV. A

AD9224

ABSOLUTE MAXIMUM RATINGS*

With

Pin Name Respect to Min Max Units

AVDD AVSS –0.3 +6.5 V DRVDD DRVSS –0.3 +6.5 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –6.5 +6.5 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V VINA, VINB AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD SENSE AVSS –0.3 AVDD CAPB, CAPT AVSS –0.3 AVDD

+ 0.3 V + 0.3 V + 0.3 V

Junction Temperature +150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ANALOG

INPUT

CLOCK

DATA

OUTPUT

DATA 1

Figure 1. Timing Diagram

PIN CONFIGURATION

28-Lead SSOP

CLK

(LSB) BIT 12

BIT 11 BIT 10

BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

(MSB) BIT 1

OTR

1 2 3 4 5 6

AD9224

TOP VIEW

(Not to Scale)

9 10 11 12 13 14

DRVDD

DRVSS

AVDD

AVSS

VINB

VINA

CML

CAPT

CAPB

REFCOM (AVSS)

VREF

SENSE

AVSS

AVDD

PIN FUNCTION DESCRIPTIONS

Pin Number Name Description

1 CLK Clock Input Pin 2 BIT 12 Least Significant Data Bit (LSB) 3–12 BIT 11–2 Data Output Bit 13 BIT 1 Most Significant Data Bit (MSB) 14 OTR Out of Range 15, 26 AVDD +5 V Analog Supply 16, 25 AVSS Analog Ground 17 SENSE Reference Select 18 VREF Input Span Select (Reference I/O) 19 REFCOM Reference Common

(AVSS) 20 CAPB Noise Reduction Pin 21 CAPT Noise Reduction Pin 22 CML Common-Mode Level (Midsupply) 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) 27 DRVSS Digital Output Driver Ground 28 DRVDD +3 V to +5 V Digital Output

Driver Supply

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9224ARS –40°C to +85°C 28-Lead Shrink Small Outline (SSOP) RS-28

AD9224-EB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.

WARNING!

Although the AD9224 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

ESD SENSITIVE DEVICE

REV. A

AD9224

DEFINITIONS OF SPECIFICATION INTEGRAL NONLINEARITY (INL)

INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges.

ZERO ERROR

The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.

GAIN ERROR

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the

maximum change from the initial (+25°C) value to the value at

or T

MIN

POWER SUPPLY REJECTION

MAX

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

–5–REV. A

AD9224

Typical Performance Characteristics

1.00

0.75

0.50

0.25

0.00

DNL – LSB

–0.25

–0.50

–0.75

–1.00

SINAD – dB

Title

CODE

Figure 2.␣ Typical DNL

–0.5dB

–6.0dB

–20.0dB

4095511 1022 1533 2044 2555 3066 3577

(AVDD, DVDD = +5 V, FS = 40 MHz [50% duty cycle] unless otherwise noted.)

2.00

1.50

1.00

0.50

0.00

INL – LSB

–0.50

–1.00

–1.50

–2.00

SINAD – dB

CODE

Figure 5. Typical INL

–0.5dB

–6.0dB

–20.0dB

4095511 1022 1533 2044 2555 3066 3577

INPUT FREQUENCY – MHz

7065605550454035302520151050.5

Figure 3. SINAD vs. Input Frequency (Input Span =

4.0 V p-p, V

–40

–45

–50

–55

–60

–65

THD – dB

–70

–75

–80

–85

0.5

= 2.5 V Differential Input)

–20.0dB

–0.5dB

–6.0dB

INPUT FREQUENCY – MHz

6551015202530354045505560

Figure 4.␣ THD vs. Input Frequency (Input Span =

4.0 V p-p, V

= 2.5 V Differential Input)

0.5 10 20 30 40 7050 60 INPUT FREQUENCY – MHz

Figure 6. SINAD vs. Input Frequency (Input Span =

2.0 V p-p, V

–20

–30

–40

–50

–60

THD – dB

–70

–80

–90

= 2.5 V Differential Input)

0.5 INPUT FREQUENCY – MHz

–20.0dB

–0.5dB

–5.0dB

705 10152025303540 5055606545

Figure 7.␣ THD vs. Input Frequency (Input Span =

2.0 V p-p, V

= 2.5 V Differential Input)

–6–

REV. A

AD9224

SNR/SFDR

0 –0.5 –60

SFDR

SNR

–20 –40

INPUT AMPLITUDE

Figure 8. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 20 MHz, Input Span = 4.0 V p-p, V

+SNR/–THD

= 2.5 V Differential Input)

SNR

THD

INPUT FREQUENCY

2520151050.5

Figure 9. +SNR/–THD vs. Input Frequency (Input Span =

4.0 V p-p, V

= 2.5 V Single-Ended Input)

THD – dB

SAMPLE RATE – MHz

5040302010

Figure 11. THD vs. Sample Rate (AIN = –0.5 dB, VCM = 2.5 V Input Span = 4.0 V p-p, V

+SNR/–THD

151050.5 25 30 70

= 2.5 V Differential Input)

THD

SNR

35 40 45 50 55 60 65

INPUT FREQUENCY

Figure 12. +SNR/–THD vs. Input Frequency (FS = 32 MHz, Input Span = 4.0 V p-p, V

= 2.5 V Differential Input)

167819

HITS

2093

BIN

2857

N+1NN–1

Figure 10.␣ “Grounded-Input” Histogram (Input Span = 2 V p-p)

–7–REV. A

AD9224

INTRODUCTION

The AD9224 is a high performance, complete single-supply 12bit ADC. The analog input range of the AD9224 is highly flexible allowing for both single-ended or differential inputs of varying amplitudes that can be ac or dc coupled.

It utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a costeffective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D.

The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9224 can be configured to interface with +5 V or +3.3 V logic families.

The AD9224 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized.

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 13 is a simplified model of the AD9224. It highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF.

VINA

VINB

AD9224

CORE

+VREF

A/D

CORE

–VREF

converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation,

= VINA – VINB (1)

CORE

defines the output of the differential input stage and provides the input to the A/D core.

The voltage, V

–VREF ≤ V

, must satisfy the condition,

CORE

≤ VREF (2)

CORE

where VREF is the voltage at the VREF pin.

While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, an additional limitation is placed on the inputs by the power supply voltages of the AD9224. The power supplies bound the valid operating range for VINA and VINB. The condition,

AVSS – 0.3 V < VINA < AVDD + 0.3 V AVSS – 0.3 V < VINB < AVDD + 0.3 V

(3)

where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. The range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3.

For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9224, see Table IV.

Refer to Table I and Table II at the end of this section for a summary of both the various analog input and reference configurations.

ANALOG INPUT OPERATION

Figure 14 shows the equivalent analog input of the AD9224 which consists of a differential sample-and-hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or commonmode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Note also, that the analog inputs, VINA and VINB, are interchangeable, with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion.

VINA

VINB

PAR

–

PAR

Figure 13. Equivalent Functional Input Circuit

The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the

–8–

Figure 14. Simplified Input Circuit

The AD9224 has a wide input range. The input peaks may be moved to AVDD or AVSS before performance is compromised. This allows for much greater flexibility when selecting singleended drive schemes. Op amps and ac coupling clamps can be set to available reference levels rather than be dictated by what the ADC “needs.”

REV. A

+ 16 hidden pages