ANALOG DEVICES AD9222 Service Manual

Serial LVDS 1.8 V A/D Converter

AD9222

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

SERIAL

LVDS

REF

SELECT

AD9222

AGND

VIN – A

VIN + A

VIN – B

VIN + B

VIN – D

VIN + D

VIN – C

VIN + C

SENSE

VREF

AVDD DRVDD

12

PDWN

REFT REFB

D – A

D + A

D – B

D + B

D – D

D + D

D – C

D + C

FCO –

FCO +

DCO + DCO –

CLK+

DRGND

CLK–

SERIAL PORT

INTERFACE

CSB

SCLK/

DTP

SDIO/

ODM

RBIAS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

DATA RATE

MULTIPLIER

0.5V

SERIAL

LVDS

VIN – E

VIN + E

VIN – F

VIN + F

VIN – H

VIN + H

VIN – G

VIN + G

12

D – E

D + E

D – F

D + F

D – H

D + H

D – G

D + G

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

ADC

05967-001

Data Sheet

FEATURES

8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical),

INL = ±0.4 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range

1.8 V supply operation Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

Octal, 12-Bit, 40/50/65 MSPS

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment

GENERAL DESCRIPTION

The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog D evices.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI).

The AD9222 is available in an RoHS compliant, 64-l ea d L F CS P. I t i s specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small,

2. Low power of 114 mW/channel at 65 MSPS.

3. Ease of Use. A data clock output (DCO) is provided that

4. User Flexibility. The SPI control offers a wide range of

5. Pin-Compatible Family. This includes the AD9212 (10-bit)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

Figure 1.

space-saving package.

operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation.

flexible features to meet specific system requirements.

and AD9252 (14-bit).

www.analog.com

AD9222 Data Sheet

REVISION HISTORY

12/11—Rev E to Rev. F

Changes to Figure 86 ...................................................................... 41

Changes to Ordering Guide .......................................................... 59

11/11—Rev. D to Rev. E

Changes to Output Signals Section .............................................. 41

Changes to Figure 86 ...................................................................... 41

Changes to Ordering Guide .......................................................... 60

4/10—Rev. C to Rev. D

Changes to Address 16 in Table 16 ............................................... 38

Updated Outline Dimensions ....................................................... 59

Changes to Ordering Guide .......................................................... 59

1/10—Rev. B to Rev. C

Updated Outline Dimensions ....................................................... 59

Changes to Ordering Guide .......................................................... 60

7/09—Rev. A to Rev. B

Changes to Figure 5 ........................................................................ 10

Changes to Figure 61 and Figure 62 ............................................. 23

Changes to Figure 79 and Figure 80 ............................................. 31

Updated Outline Dimensions ....................................................... 59

Changes to Ordering Guide .......................................................... 59

8/07—Rev. 0 to Rev. A

Added 65 MSPS Models .................................................... Universal

Changes to Features .......................................................................... 1

Changes to Product Highlights ....................................................... 1

Analog Input Considerations ................................................... 21

Clock Input Considerations ...................................................... 24

Serial Port Interface (SPI) .............................................................. 33

Hardware Interface ..................................................................... 34

Memory Map .................................................................................. 36

Reading the Memory Map Table .............................................. 36

Reserved Locations .................................................................... 36

Default Values ............................................................................. 36

Logic Levels ................................................................................. 36

Evaluation Board ............................................................................ 40

Power Supplies ............................................................................ 40

Input Signals................................................................................ 40

Output Signals ............................................................................ 40

Default Operation and Jumper Selection Settings ................. 41

Alternative Analog Input Drive Configuration...................... 42

Outline Dimensions ....................................................................... 59

Ordering Guide .......................................................................... 59

Changes to Figure 2 to Figure 4 ....................................................... 7

Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30, Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44,

Figure 46, Figure 48, and Figure 51 .............................................. 15

Added Figure 56 and Figure 58 .................................................... 22

Added Figure 70 ............................................................................. 25

Added Figure 72 ............................................................................. 26

Added Figure 74 ............................................................................. 27

Added Figure 76 and Figure 78 .................................................... 28

Changes to Digital Outputs and Timing Section ....................... 28

Changes to Table 9 Endnote .......................................................... 29

Added Table 10 ............................................................................... 30

Changes to RBIAS Pin Section ..................................................... 31

Deleted Figure 56 and Figure 57................................................... 27

Changes to Table 15 ....................................................................... 35

Change to Input Signals Section ................................................... 40

Change to Output Signals Section................................................ 40

Changes to Figure 86 ...................................................................... 40

Changes to Default Operation and Jumper Selection

Settings Section ............................................................................... 41

Changes to Alternative Analog Input Configuration Section ......... 42

Added Figure 88 and Figure 89 .................................................... 42

Change to Figure 92 ....................................................................... 45

Changes to Table 1 7 ....................................................................... 54

Updated Outline Dimensions ....................................................... 59

Changes to Ordering Guide .......................................................... 60

9/06—Revision 0: Initial Version

Rev. F | Page 2 of 60

Data Sheet AD9222

AD9222-40

AD9222-50

AD9222-65

RESOLUTION

12

Bits

Differential Input Capacitance

Full 7 7 7 pF

(Including Output Drivers)

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed

Offset Error Full ±1 ±8 ±1 ±8 ±1 ±8 mV

Offset Matching Full ±3 ±8 ±3 ±8 ±3 ±8 mV

Gain Error Full ±0.4 ±1.2 ±1.5 ±2.5 ±3.5 ±5 % FS

Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.4 ±0.8 % FS

Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 ±0.25 ±0.6 LSB

Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 ±0.4 ±1 LSB

TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ±2 ppm/°C

Gain Error Full ±17 ±17 ±17 ppm/°C

Reference Voltage (1 V Mode) Full ±21 ±21 ±21 ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 ±2 ±30 mV

Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 3 mV

Input Resistance Full 6 6 6 kΩ

ANALOG INPUTS

Differential Input Voltage Range

(VREF = 1 V)

Common-Mode Voltage Full AVDD/2 AVDD/2 AVDD/2 V

Full 2 2 2 V p-p

Analog Bandwidth, Full Power Full 325 325 325 MHz

POWER SUPPLY

AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

IAVDD Full 338 348.5 357.5 367.5 450 470 mA

IDRVDD Full 51 53.6 53.5 56.2 56.6 60.5 mA

Total Power Dissipation

Power-Down Dissipation Full 2 11 2 11 2 11 mW

Standby Dissipation2 Full 83 89 100 mW

CROSSTALK Full −90 −90 −90 dB CROSSTALK (Overrange Condition)3 Full −90 −90 −90 dB

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This can be controlled via SPI.

3

Overrange condition is specific with 6 dB of the full-scale input range.

Full 700 722 740 760 910 950.5 mW

Rev. F | Page 3 of 60

AD9222 Data Sheet

fIN = 2.4 MHz

Full 70.0

70.0

69.5 dB

fIN = 19.7 MHz

Full

73

85 73

84 70.5

80 dBc

fIN = 35 MHz

Full −92

−92

−90 dBc

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9222-40 AD9222-50 AD9222-65 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz Full 70.3 70.4 70.3 dB fIN = 19.7 MHz Full 69.5 70.3 69.5 70.3 68.5 70.0 dB fIN = 35 MHz Full 69.9 70.0 69.8 dB fIN = 70 MHz Full 68.8 69.0 69.5 dB

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 19.7 MHz Full 68.7 70.0 68.5 70.0 66.8 69.4 dB fIN = 35 MHz Full 69.5 69.8 69.3 dB fIN = 70 MHz Full 68.0 68.5 69 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full 11.38 11.4 11.4 Bits fIN = 19.7 MHz Full 11.25 11.38 11.25 11.38 11.1 11.34 Bits fIN = 35 MHz Full 11.32 11.33 11.30 Bits fIN = 70 MHz Full 11.14 11.17 11.25 Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full 85 85 83 dBc

fIN = 35 MHz Full 80 83 80 dBc fIN = 70 MHz Full 76 77 75 dBc

WORST HARMONIC (Second or Third)

fIN = 2.4 MHz Full −85 −85 −83 dBc fIN = 19.7 MHz Full −85 −74 −84 −73 −80 −70.5 dBc fIN = 35 MHz Full −80 −83 −80 dBc fIN = 70 MHz Full −76 −77 −75 dBc

WORST OTHER (Excluding Second or Third)

fIN = 2.4 MHz Full −92 −92 −90 dBc fIN = 19.7 MHz Full −92 −80 −92 −80 −90 −80 dBc

fIN = 70 MHz Full −90 −90 −85 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS f

= 15 MHz, f

IN1

f

= 70 MHz, f

IN1

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

= 16 MHz 25°C 80.0 80.0 80.0 dBc

IN2

= 71 MHz 25°C 77.0 77.0 75.0 dBc

IN2

Rev. F | Page 4 of 60

Data Sheet AD9222

Differential Input Voltage2

Full

250

mV p-p

LOGIC INPUT (SDIO/ODM)

DIGITAL OUTPUTS (D + x, D − x),

Output Offset Voltage (VOS)

Full

1.125

1.375

1.125

1.375

1.125

1.375

V

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9222-40 AD9222-50 AD9222-65

Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL

Input Common-Mode Voltage Full 1.2 1.2 1.2 V

Input Resistance (Differential) 25°C 20 20 20 kΩ

Input Capacitance 25°C 1.5 1.5 1.5 pF

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 0.3 V

Input Resistance 25°C 30 30 30 kΩ

Input Capacitance 25°C 0.5 0.5 0.5 pF

LOGIC INPUT (CSB)

Logic 1 Voltage Full 1.2 3.6 1.2 3.6 1.2 3.6 V

Logic 0 Voltage Full 0 0.3 0.3 0.3 V

Input Resistance 25°C 70 70 70 kΩ

Input Capacitance 25°C 0.5 0.5 0.5 pF

Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V

Logic 0 Voltage Full 0 0.3 0 0.3 0 0.3 V

Input Resistance 25°C 30 30 30 kΩ

Input Capacitance 25°C 2 2 2 pF

LOGIC OUTPUT (SDIO/ODM)3

Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 1.79 V

Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 0.05 V

(ANSI-644)1

Logic Compliance LVDS LVDS LVDS

Differential Output Voltage (VOD) Full 247 454 247 454 247 454 mV

Output Coding (Default)

DIGITAL OUTPUTS (D + x, D − x),

(Low Power, Reduced Signal

1

Option)

Offset binary Offset binary Offset binary

Logic Compliance LVDS LVDS LVDS

Differential Output Voltage (VOD) Full 150 250 150 250 150 250 mV

Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 1.10 1.30 V

Output Coding (Default)

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This is specified for LVDS and LVPECL only.

3

This is specified for 13 SDIO pins sharing the same connection.

Offset binary Offset binary Offset binary

Rev. F | Page 5 of 60

AD9222 Data Sheet

CLOCK2

Maximum Clock Rate

Full

40

50

65

MSPS

Minimum Clock Rate

Full

10

MSPS

Aperture Delay (tA)

25°C 750

750

750 ps

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9222-40 AD9222-50 AD9222-65 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit

Clock Pulse Width High (tEH) Full 12.5 10.0 7.5 ns Clock Pulse Width Low (tEL) Full 12.5 10.0 7.5 ns

OUTPUT PARAMETERS

Propagation Delay (tPD) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 300 300 ps Fall Time (tF) (20% to 80%) Full 300 300 300 ps FCO Propagati on Delay (t DCO Propagation Delay (t

DCO to Data De lay (t

DCO to FCO Delay (t

Data to Data Skew

(t

DATA-MAX

Wake-Up Time (Standby) 25°C 600 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 375 μs Pipeline Latency Full 8 8 8 CLK

APERTURE

2, 3

) Full 1.5 2.3 3.1 1.5 2.3 3.1 1.5 2.3 3.1 ns

FCO

)4 Full t

CPD

)4 Full (t

DATA

)4 Full (t

FRAME

SAMPLE

− 300

SAMPLE

− 300

/24)

(t (t

(t

FCO

SAMPLE

+

t

/24) /24) (t

SAMPLE

/24)

+ 300

/24) (t

SAMPLE

/24)

+ 300

(t

SAMPLE

− 300 (t

SAMPLE

− 300

/24)

(t (t

(t

FCO

SAMPLE

+

t

/24) /24) (t

SAMPLE

/24)

+ 300

/24) (t

SAMPLE

/24)

+ 300

(t

SAMPLE

− 300 (t

SAMPLE

− 300

/24)

(t (t

(t

FCO

SAMPLE

+

Full ±50 ±200 ±50 ±200 ±50 ±200 ps

− t

)

DATA-MIN

/24) /24) (t

/24) (t

ns

/24)

SAMPLE

ps

+ 300

/24)

SAMPLE

ps

+ 300

cycles

Aperture Uncertainty (Jitter) 25°C <1 <1 <1 ps

Out-of-Range Recovery Time 25°C 1 1 1 CLK

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

This can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR4 material.

4

t

/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

SAMPLE

rms

cycles

Rev. F | Page 6 of 60

Data Sheet AD9222

DCO–

DCO+

D – x

D + x

FCO–

FCO+

CLK–

CLK+

MSB N – 9

D10

N – 9D9N – 9D8N – 9D7N – 9D6N – 9D5N – 9D4N – 9D3N – 9D2N – 9D1N – 9D0N – 9

D10

N – 8

MSB N – 8

N – 1

N

t

DATA

t

FRAME

t

FCO

t

PD

t

CPD

t

EH

t

A

t

EL

05967-002

VIN ± x

DCO+

DCO–

CLK+

FCO+

FCO–

D – x

D + x

CL

K–

MSB

N – 9

N – 1

N

D8

N – 9D7N – 9

D5

N – 9

t

DATA

t

FRAME

t

FCO

t

PD

D4

N – 9

D6

N – 9

D8

N – 8D7N – 8

D5

N – 8

D6

N – 8

D3

N – 9

D1

N – 9

MSB N – 8

D0

N – 9

D2

N – 9

t

CPD

t

EH

t

A

t

EL

05967-003

VIN ± x

TIMING DIAGRAMS

Figure 2. 12-Bit Data Serial Stream, MSB First (Default)

Figure 3. 10-Bit Data Serial Stream, MSB First

Rev. F | Page 7 of 60

AD9222 Data Sheet

DCO–

DCO+

D – x

D + x

FCO–

FCO+

VIN ± x

CLK–

CLK+

LSB N – 9

D0

N – 9D1N – 9D2N – 9D3N – 9D4N – 9D5N – 9D6N – 9D7N – 9D8N – 9D9N – 9

D10

N – 9

D0

N – 8

LSB N – 8

N – 1

t

A

N

t

DATA

t

FRAME

t

FCO

t

PD

t

CPD

t

EH

t

EL

05967-004

Figure 4. 12-Bit Data Serial Stream, LSB First

Rev. F | Page 8 of 60

Data Sheet AD9222

Digital Outputs

DRGND

−0.3 V to +2.0 V

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

Respect To Rating

ELECTRICAL

AVDD AGND −0.3 V to +2.0 V

DRVDD DRGND −0.3 V to +2.0 V

AGND DRGND −0.3 V to +0.3 V

AVDD DRVDD −2.0 V to +2.0 V

(D + x, D − x, DCO+,

DCO−, FCO+, FCO−) CLK+, CLK− AGND −0.3 V to +3.9 V VIN + x, VIN − x AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

−40°C to +85°C

Range (Ambient) Maximum Junction

150°C

Temperature Lead Temperature

300°C

(Soldering, 10 sec) Storage Temperature

−65°C to +150°C

Range (Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

1

θ

JA

JB

θJC

0.0 17.7°C/W

1.0 15.5°C/W 8.7°C/W 0.6°C/W

2.5 13.9°C/W

1

θ

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

JA

soldered to PCB.

ESD CAUTION

Rev. F | Page 9 of 60

AD9222 Data Sheet

05967-005

PIN 1 INDIC

ATOR

171819202122232425262728293031

32

D – G

D + G

D – F

D + F

D – E

D + E

DCO–

DCO+

FCO–

FCO+

D – D

D + D

D – C

D + C

D – B

D + B

646362616059585756

55545352515049

VIN + F

VIN – F

AVDD

VIN – E

VIN + E

AVDD

REFT

REFB

VREF

SENSE

RBIAS

VIN + D

VIN – D

AVDD

VIN – C

VIN + C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

AVDD VIN + G VIN – G

AVDD VIN – H VIN + H

AVDD

CLK–

CLK+

AVDD

AVDD DRGND DRVDD

D – H D + H

AVDD VIN + B VIN – B AVDD VIN – A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP A

VDD DRGND DRVDD D + A D – A

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

AD9222

TOP VIEW

(Not to S cale)

EXPOSED PADDLE, PIN 0 (BOTTO M OF PACKAGE )

NOTES

1. THE EXP OSED PAD MUST BE CONNECTED TO ANALOG GROUND

20

D + F

ADC F Digital Output True

25

FCO−

Frame Clock Digital Output Complement

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. 64-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0 AGND Analog Ground (Exposed Paddle) 1, 4, 7, 8, 11,

AVDD 1.8 V Analog Supply 12, 37, 42, 45, 48, 51, 59, 62

13, 36 DRGND Digital Output Driver Ground 14, 35 DRVDD 1.8 V Digital Output Driver Supply 2 VIN + G ADC G Analog Input True 3 VIN − G ADC G Analog Input Complement 5 VIN − H ADC H Analog Input Complement 6 VIN + H ADC H Analog Input True 9 CLK− Input Clock Complement 10 CLK+ Input Clock True 15 D − H ADC H Digital Output Complement 16 D + H ADC H Digital Output True 17 D − G ADC G Digital Output Complement 18 D + G ADC G Digital Output True 19 D − F ADC F Digital Output Complement

21 D − E ADC E Digital Output Complement 22 D + E ADC E Digital Output True 23 DCO− Data Clock Digital Output Complement 24 DCO+ Data Clock Digital Output True

26 FCO+ Frame Clock Digital Output True 27 D − D ADC D Digital Output Complement 28 D + D ADC D Digital Output True 29 D − C ADC C Digital Output Complement 30 D + C ADC C Digital Output True 31 D − B ADC B Digital Output Complement 32 D + B ADC B Digital Output True

Rev. F | Page 10 of 60

Data Sheet AD9222

40

CSB

Chip Select Bar

63

VIN − F

ADC F Analog Input Complement

Pin No. Mnemonic Description

33 D − A ADC A Digital Output Complement 34 D + A ADC A Digital Output True 38 SCLK/DTP Serial Clock/Digital Test Pattern 39 SDIO/ODM Serial Data Input-Output/Output Driver Mode

41 PDWN Power Down 43 VIN + A ADC A Analog Input True 44 VIN − A ADC A Analog Input Complement 46 VIN − B ADC B Analog Input Complement 47 VIN + B ADC B Analog Input True 49 VIN + C ADC C Analog Input True 50 VIN − C ADC C Analog Input Complement 52 VIN − D ADC D Analog Input Complement 53 VIN + D ADC D Analog Input True 54 RBIAS External Resistor to Set the Internal ADC Core Bias Current 55 SENSE Reference Mode Selection 56 VREF Voltage Reference Input/Output 57 REFB Differential Reference (Negative) 58 REFT Differential Reference (Positive) 60 VIN + E ADC E Analog Input True 61 VIN − E ADC E Analog Input Complement

64 VIN + F ADC F Analog Input True

Rev. F | Page 11 of 60

AD9222 Data Sheet

VIN ± x

05967-006

10Ω

10kΩ

CLK–

10Ω

1.25V

CLK+

05967-007

SDIO/ODM

350Ω

30kΩ

05967-008

DRVDD

DRGND

D– D+

V

05967-009

SCLK/DTP AND PDWN

30kΩ

1kΩ

05967-010

100Ω

RBIAS

05967-011

EQUIVALENT CIRCUITS

Figure 6. Equivalent Analog Input Circuit

Figure 7. Equivalent Clock Input Circuit

Figure 9. Equivalent Digital Output Circuit

Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit

Figure 8. Equivalent SDIO/ODM Input Circuit

Figure 11. Equivalent RBIAS Circuit

Rev. F | Page 12 of 60

Data Sheet AD9222

CSB

70kΩ

1kΩ

AVDD

05967-012

SENSE

1kΩ

05967-013

VREF

6kΩ

05967-014

Figure 12. Equivalent CSB Input Circuit

Figure 14. Equivalent VREF Circuit

Figure 13. Equivalent SENSE Circuit

Rev. F | Page 13 of 60

AD9222 Data Sheet

05967-015

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–120

0

0 20

–100

–80

–60

–40

–20

2

4 6 8 10

12 14 16 18

AIN = –0.5dBF S SNR = 70.79dB ENOB = 11.47 BITS SFDR = 84.71dBc

05967-016

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–120

0

0 20

–100

–80

–60

–40

–20

2 4 6 8 10 12 14 16 18

AIN = –0.5dBF S SNR = 70.32dB ENOB = 11.39 BITS SFDR = 84.28dBc

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBF S SNR = 70.72dB ENOB = 11.45 BITS SFDR = 85.79dBc

05967-017

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBF S SNR = 70.35dB ENOB = 11.40 BITS SFDR = 83.86dBc

05967-018

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBF S SNR = 70.02dB ENOB = 11.45 BITS SFDR = 86.3dBc

05967-019

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBF S SNR = 69.25dB ENOB = 11.21 BITS SFDR = 72.85dBc

05967-020

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. Single-Tone 32k FFT with f

= 2.3 MHz, AD9222-40

IN

Figure 16. Single-Tone 32k FFT with fIN = 19.7 MHz, AD9222-40

Figure 18. Single-Tone 32k FFT with f

= 35 MHz, AD9222-50

IN

Figure 19. Single-Tone 32k FFT with f

= 70 MHz, AD9222-50

IN

Figure 17. Single-Tone 32k FFT with f

= 2.3 MHz, AD9222-50

IN

Rev. F | Page 14 of 60

Figure 20. Single-Tone 32k FFT with f

= 120 MHz, AD9222-50

IN

Data Sheet AD9222

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBFS SNR = 70.21dB ENOB = 11.31

BITS

SFDR = 82.37dBc

05967-085

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBFS SNR = 69.8dB ENO

B = 11.22 BITS

SFDR = 80.61dBc

05967-086

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBFS SNR = 69.65dB E

NOB = 11.07 BITS

SFDR = 74.79dBc

05967-087

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN = –0.5dBFS SNR =

68.67dB ENOB = 10.79 BITS SFDR = 71.49dBc

05967-088

100

90

95

85

80

75

70

65

60

10 5045403530252015

SNR/SFDR (dB)

ENCODE (MSPS)

2V p-p, SFDR

2V p-p, SNR

05967-021

90

85

80

75

70

65

60

10 5045403530252015

SNR/SFDR (dB)

ENCODE (MSPS)

2V p-p, SFDR

2V p-p, SNR

05967-022

Figure 21. Single-Tone 32k FFT with f

Figure 22. Single-Tone 32k FFT with f

= 2.3 MHz, AD9222-65

IN

= 35 MHz, AD9222-65

IN

Figure 24. Single-Tone 32k FFT with f

= 120 MHz, AD9222-65

IN

Figure 25. SNR/SFDR vs. f

, fIN = 2.61 MHz, AD9222-50

SAMPLE

Figure 23. Single-Tone 32k FFT with fIN = 70 MHz, AD9222-65

Figure 26. SNR/SFDR vs. f

, fIN = 20.1 MHz, AD9222-50

SAMPLE

Rev. F | Page 15 of 60

AD9222 Data Sheet

SNR/SFDR (dB)

ENCODE (MSPS)

60

65

70

75

80

85

90

95

100

10 15 20 25 30 35 40 45 50 55 60 65

2V p-p, SFDR

2V p-p, SNR

05967-089

SNR/SFDR (dB)

ENCODE (MSPS)

60

65

70

75

80

85

90

10 15 20 25 30 35 40 45 50 55 60 65

2V p-p, SFDR

2V p-p, SNR

05967-090

100

90

80

70

60

50

40

30

20

10

0 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dB)

INPUT AMPLITUDE (dBFS)

80dB

REFERENCE

2V p-p, SFDR

2V p-p, SNR

05967-023

2V p-p, SNR

2V p-p, SFDR

SNR/SFDR (dB)

INPUT AMPLITUDE (dBFS)

0

10

20

30

40

50

60

70

80

90

–60 –50 –40 –30 –20 –10 0

80dB REFERENCE LINE

05967-091

100

90

80

70

60

50

40

30

20

10

0 –60 –50 –40 –30 –20 –10 0

SNR/SFDR (dB)

INPUT AMPLITUDE (dBFS)

80dB

REFERENCE

2V p-p, SFDR

2V p-p, SNR

05967-024

2V p-p, SNR

2V p-p, SFDR

SNR/SFDR (dB)

INPUT AMPLITUDE (dBFS)

0

10

20

30

40

50

60

70

80

90

–60 –50 –40 –30 –20 –10 0

80dB REFERENCE LINE

05967-092

Figure 27. SNR/SFDR vs. f

Figure 28. SNR/SFDR vs. f

, fIN = 2.3 MHz, AD9222-65

SAMPLE

, fIN = 19.7 MHz, AD9222-65

SAMPLE

Figure 30. SNR/SFDR vs. Analog Input Level, f

= 10.3 MHz, AD9222-65

IN

Figure 31. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-50

Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, AD9222-50

Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, AD9222-65

Rev. F | Page 16 of 60

Data Sheet AD9222

0

–120

–100

–80

–60

–40

–20

0 2 4 6 8 10 12 14 16 18 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S SFDR = 89.87dB IMD2 = 96.07dBc IMD3 = 90.16dBc

05967-025

0

–120

–100

–80

–60

–40

–20

0 2 4 6 8 10 12 14 16 18 20

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S SFDR = 77.24dB IMD2 = 91.66dBc IMD3 = 77.72dBc

05967-026

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S SFDR = 84.49dB IMD2 = 85.83dBc IMD3 = 84.54dBc

05967-027

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S SFDR = 80.42dB IMD2 = 83.92dBc IMD3 = 80.60dBc

05967-032

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S

SFDR = 79.5dB IMD2 = 80.0dBc IMD3 = 84.1dBc

05967-093

0

–120

–100

–80

–60

–40

–20

0 5 10 15 20 25 30

AMPLITUDE (dBFS)

FREQUENCY (MHz)

AIN1 AND AIN2 = –7dBF S

SFDR = 75.2dB IMD2 = 79.3dBc IMD3 = 75.1dBc

05967-094

Figure 33. Two-Tone 32k FFT with f

AD9222-40

Figure 34. Two-Tone 32k FFT with f

AD9222-40

= 15 MHz and f

IN1

= 70 MHz and f

IN1

= 16 MHz,

IN2

= 71 MHz,

IN2

Figure 36. Two-Tone 32k FFT with f

Figure 37. Two-Tone 32k FFT with f

= 70 MHz and f

IN1

= 15 MHz and f

IN1

= 71 MHz, AD9222-50

IN2

= 16 MHz, AD9222-65

IN2

Figure 35. Two-Tone 32k FFT with f

= 15 MHz and f

IN1

= 16 MHz, AD9222-50

IN2

Figure 38. Two-Tone 32k FFT with f

Rev. F | Page 17 of 60

= 70 MHz and f

IN1

= 71 MHz, AD9222-65

IN2

AD9222 Data Sheet

90

85

80

75

70

65

60

1 100010010

SNR/SFDR (dB)

ANALOG I NP UT FREQUENCY ( M Hz )

SFDR

SNR

05967-029

SNR/SFDR (dB)

FREQUENCY (MHz)

1 10 100 1000

50

55

60

65

70

75

80

85

90

2V p-p, SFDR

2V p-p, SNR

05967-095

100

90

95

85

80

75

70

65

60

–40 –20 0 20 40 60 80

SINAD/SF DR ( dB)

TEMPERATURE (°C)

2V p-p, SFDR

2V p-p, SINAD

05967-030

90

85

80

75

70

65

60

–40 –20 0 20 40 8060

SINAD/SF DR ( dB)

TEMPERATURE (°C)

2V p-p, SFDR

2V p-p, SINAD

05967-096

90

85

80

75

70

65

60

–40 –20 0 20 40 60 80

SINAD/SF DR ( dB)

TEMPERATURE (°C)

2V p-p, SFDR

2V p-p, SINAD

05967-031

90

85

80

75

70

65

60

–40 –20 0 20 40 8060

SINAD/SF DR ( dB)

TEMPERATURE (°C)

2V p-p, SFDR

2V p-p, SINAD

05967-097

Figure 39. SNR/SFDR vs. fIN, AD9222-50

Figure 40. SNR/SFDR vs. fIN, AD9222-65

Figure 42. SINAD/SFDR vs. Temperature, fIN = 2.3 MHz, AD9222-65

Figure 43. SINAD/SFDR vs. Temperature, fIN = 20.1 MHz, AD9222-50

Figure 41. SINAD/SFDR vs. Temperature, fIN = 2.61 MHz, AD9222-50

Figure 44. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, AD9222-65

Rev. F | Page 18 of 60

ANALOG DEVICES AD9222 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL IMPEDANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS