ANALOG DEVICES AD9216 Service Manual
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Rev. PrD_6
/15/
2004
10-Bit, 65/80/105 MSPS
Preliminary Technical Data
FEATURES
Integrated Dual 10-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist, AD9216-105)
SFDR = 75 dBc (to Nyquist, AD9216-105)
Low Power: 280mW at 105MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 75dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
3G, Radio Point-to-Point, LMDS, MMDS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-todigital converter. It features dual high performance sample-and
hold amplifiers and an integrated voltage reference. The
AD9216 uses a multistage differential pipelined architecture
with output error correction logic to provide 10-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 105 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well
beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 (all speed grades) and can compensate for wide
variations in the clock duty cycle, allowing the converters to
maintain excellent performance. The digital output data is
presented in either straight binary or twos complement format.
Out-of-range signals indicate an overflow condition, which can
be used with the most significant bit to determine low or high
overflow.
Dual A/D Converter
AD9216
specified over the industrial temperature range (–40°C to
+85°C).
AGND
AVDD
VIN+_A
VIN- _A
REFT_A
REFB_A
VREF
SENSE
AGND
REFT_B
REFB_B
VIN+_B
VIN-_B
SHA
+
0.5V
-
SHA
AD9216
Figure 1. Functional Block Diagram
ADC
ADC
DRVDD
10
10
DRGND
Buffers
Output Mux/
Clock
Duty Cycle
Stabilizer
Mode
Control
Buffers
Output Mux/
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit
20/40/65MSPS ADC and AD9248, dual 14-bit
20/40/65MSPS ADC.
2. Speed grade options off 105 MSPS, 80 MSPS, and
65 MSPS allow flexibility between power, cost, and
performance to suit an application.
3. Low power consumption:
AD9216-105: 105 MSPS = 280 mW
AD9216-80: 80 MSPS = 238 mW
AD9216-65: 65 MSPS = 215mW
4. The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential
operation.
5. Typical channel isolation of 75 dB @ fIN = 10 MHz.
6. The clock duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
10
10
OTR_A
D9A-D
0A
OEB_A
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
OTR_B
D10B-D
OEB_B
0B
Fabricated on an advanced CMOS process, the AD9216 is
available in a space saving 64-lead LFCSP (9x9) and is
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD9216 Preliminary Technical Data
TABLE OF CONTENTS
General Description..............................................................1
Product Highlights ................................................................1
DC Specifications (Continued) .............................................4
Switching Specifications ....................................................... 4
AC Specifications .................................................................5
Absolute Maximum Ratings ..................................................... 7
ESD Caution.........................................................................7
Terminology........................................................................ 10
Typical Performance CharacteristiC PLOTS (TBD)..............12
Equivalent Circuits ................................................................. 13
REVISION HISTORY
PrA: Initial Version
Theory of Operation............................................................13
Analog Input ....................................................................... 13
Clock Input and Considerations .......................................... 15
Power Dissipation and Standby Mode ................................ 15
Digital Outputs.................................................................... 15
Timing ................................................................................ 16
Data Format........................................................................ 16
Voltage Reference............................................................... 17
Evaluation Board Diagrams (TBD) ........................................ 19
Outline Dimensions ................................................................ 20
PrB: included specification tables, ordering guide, package and pin configuration and Theory of operation sections.
PrC: Corrected pin configuration figure (Fig3) pin naming errors , updated supply spec, corrected timing diagram and latency.
PrD: Removed 120MSPS Grade, Updated DCS,OEB_B pin descriptions, updated input referred noise, Demux Timing Diagram needs
updating
Rev. PrD Page 2 of 20 6/15/2004
Preliminary Technical Data AD9216
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 10 10 Bits
ACCURACY
No Missing Codes Guaranteed Full VI 10 10 Bits
Offset Error Full VI ±0.3 ±TBD ±0.30 ±TBD % FSR
Gain Error1 Full IV ±1.0 ±TBD ±1.0 ±TBD % FSR
Differential Nonlinearity (DNL)2 Full V ±0.5 ±0.5 LSB
25°C I ±0.5 ±TBD ±0.5 ±TBD LSB
Integral Nonlinearity (INL)2 Full V ±0.5 ±0.5 LSB
25°C I ±0.5 ±TBD ±0.5 ±TBD LSB
TEMPERATURE DRIFT
Offset Error Full V ±15 ±15 ppm/°C
Gain Error1 Full V ±30 ±30 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full V 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA Full V 0.1 0.1 mV
INPUT REFERRED NOISE
Input Span = 1 V 25°C V 0.8 0.8 LSB rms
Input Span = 2.0 V 25°C V 0.4 0.4 LSB rms
ANALOG INPUT
Input Span = 1.0 V Full IV 1 1 V p-p
Input Span = 2.0 V Full IV 2 2 V p-p
Input Capacitance3 Full V 2 2 pF
REFERENCE INPUT RESISTANCE Full V 7 7 k?
POWER SUPPLIES
Supply Voltages
AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 V
DRVDD Full IV 2.25 2.5 3.6 2.25 2.5 3.6 V
Supply Current
IAVDD2 Full V TBD/TBD TBD mA
IDRVDD2 Full V TBD/TBD TBD mA
PSRR Full V ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input4 Full V TBD/TBD TBD mW
Sine Wave Input2 Full VI 215/238 280 mW
Standby Power5 Full V 1/1 1 mW
MATCHING CHARACTERISTICS
Offset Error Full V ±0.1 ±0.1 % FSR
Gain Error Full V ±0.05 ±0.05 % FSR
1
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
Test AD9216BCP-65/80 AD9216BCP-105
Rev. PrD Page 3 of 20 6/15/2004
AD9216 Preliminary Technical Data
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parameter Temp Level Min Typ Max Min Typ Max
LOGIC INPUTS
High Level Input Voltage Full IV 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 V
High Level Input Current Full IV - 10 +10 - 10 +10 µA
Low Level Input Current Full IV - 10 +10 - 10 +10 µA
Input Capacitance Full IV 2 2 pF
LOGIC OUTPUTS1
DRVDD = 2.5V
High Level Output
Full IV 2.45 2.45 V
Voltage
Low Level Output Voltage Full IV 0.05 0.05 V
1
Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Parameter Temp Level Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Max Conversion Rate Full VI 65/80 105 MSPS
Min Conversion Rate Full V 1 1 MSPS
CLK Period Full V 15.4/12.2 9.5 ns
CLK Pulsewidth High1 Full V 6.2/5 4.2 ns
CLK Pulsewidth Low1 Full V 6.2/5 4.2 ns
DATA OUTPUT PARAMETER
Output Delay2 (tPD) Full VI 2.0 4.8 6.0 2.0 4.8 6.0 ns
Pipeline Delay (Latency) Full V 6 6 Cycles
Aperture Delay (tA) Full V 1.0 1.0 ns
Aperture Uncertainty (tJ) Full V 0.5 0.5 ps rms
Wake-Up Time3 Full V 2.5 2.5 ms
OUT-OF-RANGE RECOVERY
TIME
1
The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx).
2
Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
ANALOG
INPUT
Test AD9216BCP-65/80 AD9216BCP-105 Unit
Test AD9216BCP-65/80 AD9216BCP-105
Full V 2 2
N+1
N
N–1
N+2
t
A
N+3
N+4
N+5
N+6
N+8
N+7
CLK
DATA
OUT
Rev. PrD Page 4 of 20 6/15/2004
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N-1 N N+1
t
PD
Figure 2. Timing Diagram
Preliminary Technical Data AD9216
AC SPECIFICATIONS
Table 4. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Parameter Temp Level Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO
f
= 2.4 MHz 25°C V 58 57 dBc
INPUT
f
= 19.6 MHz Full V 58 dBc
INPUT
25°C IV TBD 58 dBc
f
= 32.5 MHz Full V 57 dBc
INPUT
25°C IV TBD 57 dBc
f
= 69 MHz Full V dBc
INPUT
25°C IV dBc
f
= 100 MHz 25°C V 57 56 dBc
INPUT
SIGNAL-TO-NOISE AND DISTORTION RATIO
f
= 2.4 MHz 25°C V 58 57 dBc
INPUT
f
= 19.6 MHz Full V 58 dBc
INPUT
25°C IV TBD 58 dBc
f
= 32.5 MHz Full V 57 dBc
INPUT
25°C IV TBD 56 dBc
f
= 69 MHz Full V dBc
INPUT
25°C IV dBc
f
= 100 MHz 25°C V 56 55 dBc
INPUT
EFFECTIVE NUMBER OF BITS (ENOB)
f
= 2.4 MHz 25°C V 9.4 9.3 Bits
INPUT
f
= 19.6 MHz Full V 9.4 Bits
INPUT
25°C I TBD 9.4 Bits
f
= 32.5 MHz Full V 9.3 Bits
INPUT
25°C I TBD 9.1 Bits
f
= 69 MHz Full V Bits
INPUT
25°C I Bits
f
= 100 MHz 25°C V 9.1 8.9 Bits
INPUT
TOTAL HARMONIC DISTORTION
f
= 2.4 MHz 25°C V -70.0 -70.0 dBc
INPUT
f
= 19.6 MHz Full V -69.0 dBc
INPUT
25°C I - 70.0 TBD dBc
f
= 32.5 MHz Full V - 69.0 dBc
INPUT
25°C I - 68.0 TBD dBc
f
= 69 MHz Full V dBc
INPUT
25°C I dBc
f
= 100 MHz 25°C V - 67.0 - 66.0 dBc
INPUT
WORST HARMONIC (2nd or 3rd)
f
= 19.6 MHz Full V -75.0 dBc
INPUT
f
= 32.5 MHz Full V - 74.0 dBc
INPUT
f
= 69 MHz Full V dBc
INPUT
SPURIOUS FREE DYNAMIC RANGE
f
= 2.4 MHz 25°C V 75.0 75.0 dBc
INPUT
f
= 19.6 MHz Full V 75.0 dBc
INPUT
25°C I TBD 75.0 dBc
f
= 32.5 MHz Full V 74.0 dBc
INPUT
25°C I TBD 74.0 dBc
f
= 69 MHz Full V dBc
INPUT
25°C I dBc
Test AD9216BCP-65/80 AD9216BCP-105
Rev. PrD Page 5 of 20 6/15/2004
AD9216 Preliminary Technical Data
f
= 100 MHz 25°C V dBc
INPUT
CROSSTALK Full V -80.0 - 80.0 dB
Specifications subject to change without notice.
Rev. PrD Page 6 of 20 6/15/2004
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