ANALOG DEVICES AD9211 Service Manual

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10-Bit, 170/200/250 MSPS

Preliminary Technical Data

FEATURES

SNR = 60 dBFs @ fIN up to 70 MHz @ 250 MSPS
ENOB of 9.7 @ f
SFDR = 80 dBc@ f
Excellent Linearity
DNL = ±0.3 LSB (Typical)
INL = ±0.5 LSB (Typical)
LVDS at 250 MSPS (ANSI-644 levels)
900 MHz Full Power Analog Bandwidth
On-Chip Reference and Track-and-Hold
Power Dissipation = 380 mW Typical @ 250 MSPS

1.25 V Input Voltage Range

1.8 V Analog Supply Operation
Output Data Format Option
Data Clock Output Provided
Clock Duty Cycle Stabilizer

APPLICATIONS

Wireless and Wired Broadband Communications
Cable Reverse Path
Communications Test Equipment
Radar and Satellite Subsystems
Power Amplifier Linearization

PRODUCT DESCRIPTION

The AD9211 is a 10-Bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 250 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete signal
conversion solution.

The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format or gray code. A data
clock output is available for proper output data timing.

up to 70 MHz @ 250 MSPS (–0.5 dBFS)

IN

up to 70 MHz @ 250 MSPS (–0.5 dBFS)

IN

1.8 V A/D Converter
AD9211

AVDD (1.8V)

AGND

AD9211

Ref

VIN+
VIN-

CLK+
CLK-

T/H

Clock
Mgmt

RESET

ADC

10-bit

Core

10

Serial Port

SCLK CSB

SDIO

Output

Staging -

LVDS

Figure 1. Functional Block Diagram

Fabricated on an advanced CMOS process, the AD9211 is
available in a 56-lead chip scale package (56 LFCSP) specified
over the industrial temperature range (–40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High Performance—Maintains 60 dB SNR @ 250 MSPS

with a 65 MHz input.

2. Low Power—Consumes only 380mW @ 250 MSPS.

3. Ease of Use—LVDS output data and output clock signal

allow interface to current FPGA technology. The on-chip
reference and sample/hold provide flexibility in system
design. Use of a single 1.8 V supply simplifies system
power supply design. Supported DDR mode reduces
number of output data traces

4. Serial Port Control - Standard serial port interface

supports various product functions such as data
formatting, enabling a clock duty cycle stabilizer, power
down, gain adjust and output test pattern generation.

Pin compatible family – 12-bit pin compatible family

5.

offered as AD9230.

DrVDD (1.8V)

DGND

(Pin 0)

10

D9-D0
(D4-D0 DDR mode)

OTR+
OTR-

DCO+

DCO-

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

www.analog.com

AD9211 Preliminary Technical Data

TABLE OF CONTENTS

AD9211–Specifications.................................................................... 3

Power Dissipation and POWER DOWN Mode .................... 16

AC Specifications.............................................................................. 4

Digital Specifications........................................................................ 5

Switching Specifications .................................................................. 6

Absolute Maximum Ratings

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Terminology .................................................................................... 10

Equivalent circuits.......................................................................... 12

Typical Performance CHARACTERISTICS ............................... 13

Theory of Operation ..................................................................14

Analog Input and Reference Overview ...................................14

Clock Input Considerations...................................................... 15

1

.......................................................... 7

Digital Outputs........................................................................... 17

Timing ......................................................................................... 17

RBIAS........................................................................................... 18

AD9211 Configuration Using the SPI..................................... 18

Hardware Interface..................................................................... 19

Reading the Memory Map Table.............................................. 19

Open Locations .......................................................................... 19

Default Values............................................................................. 19

Logic Levels................................................................................. 19

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 21

Rev. PrA | Page 2 of 21

Preliminary Technical Data AD9211

AD9211–SPECIFICATIONS

Table 1. DC SPECIFICATIONS (AVDD = 1.8 V, DRVDD = 1.8 V, T
Full Scale = 1.25 V, DCS Enabled, unless otherwise noted.)

AD9211-170/-200 AD9211-250
Parameter Temp Min Typ Max Min Typ Max Unit

RESOLUTION 10 10 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error 25°C TBD TBD mV
Gain Error 25°C TBD TBD % FS
Differential Nonlinearity (DNL) 25°C ± 0.3 ± 0.3 LSB
Full ± 0.3 ± 0.3 LSB
Integral Nonlinearity (INL) 25°C ± 0.5 ± 0.5 LSB
Full ± 0.5 ± 0.5 LSB
TEMPERATURE DRIFT
Offset Error Full TBD TBD μV/°C
Gain Error Full TBD TBD %/°C

ANALOG INPUTS (VIN+, VIN–)
Differential Input Voltage Range Full 1.25 1.25 V
Input Common-Mode Voltage Full 1.3 1.3 V
Input Resistance (differential) Full 4 4 kΩ
Input Capacitance 25°C 2 2 pF
POWER SUPPLY (LVDS Mode)
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Currents
I

(AVDD = 1.8 V) 1 Full 122/138 151 mA

ANALOG

I

(DRVDD = 1.8 V)3 Full 50/50 60 mA

DIGITAL

Power Dissipation3 Full 310/340 380 mW

Power Supply Rejection 25°C TBD TBD mV/V

1

I

and I

AVDD

Characteristics and Applications sections for I

are measured with a dc input at rated Clock rate. See Typical Performance

DRVDD

ANALOG

and I

with dynamic input vs clock rate

DRVDD

= –40°C, T

MIN

= +85°C, fIN = –0.5 dBFS, Internal Reference,

MAX

Rev. PrA | Page 3 of 21

AD9211 Preliminary Technical Data

AC SPECIFICATIONS1

Table 2. (AVDD = 1.8 V, DRVDD = 1.8 V, T
= -0.5dBFS, DCS Enabled unless otherwise noted.)

Parameter Temp Min Typ Max Min Typ Max Unit

SNR

fin=10 MHz 25°C 60 60 dB

Full 60 60 dB

fin=70 MHz 25°C 60 60 dB

Full 60 60 dB
fin=100 MHz 25°C 59 59 dB
fin=240 MHz 25°C 58 58 dB

SINAD

fin=10 MHz 25°C 60 60 dB

Full 59.5 59.5 dB

fin=70 MHz 25°C 60 60 dB

Full 59.5 59.5 dB
fin=100 MHz 25°C 58.5 58.5 dB
fin=240 MHz 25°C 57.5 57.5 dB

EFFECTIVE NUMBER OF BITS
(ENOB)

fin=10 MHz 25°C 9.6 9.6 Bits

Full 9.6 9.6 Bits

fin=70 MHz 25°C 9.6 9.6 Bits

Full 9.6 9.6 Bits
fin=100 MHz 25°C 9.4 9.4 Bits
fin=240 MHz 25°C 9.2 9.2 Bits

WORST HARMONIC (2nd or 3rd)

fin=10 MHz 25°C –80 –80 dBc

Full –80 –80 dBc

fin=70 MHz 25°C –80 –80 dBc

Full –80 –80 dBc
fin=100 MHz 25°C –78 –77 dBc
fin=240 MHz 25°C –75 –75 dBc

WORST HARMONIC (4th or
Higher)

fin=10 MHz 25°C –85 –85 dBc

Full –85 –85 dBc

fin=70 MHz 25°C –85 –85 dBc

Full –85 –85 dBc
fin=100 MHz 25°C –83 –83 dBc
fin=240 MHz 25°C –78 –78 dBc

TWO-TONE IMD2
F1, F2 @ –7 dBFS 25°C –75 –75 dBc
ANALOG INPUT BANDWIDTH 25°C 900 900 MHz

1

All ac specifications tested by driving CLK+ and CLK– differentially.

2

F1 = 28.3 MHz, F2 = 29.3 MHz.

= –40°C, T

MIN

= +85°C, fIN = –0.5 dBFS, Internal Reference, Full Scale = 1.25 V, Ain

MAX

AD9211-170/-200 AD9211-250

Rev. PrA | Page 4 of 21

Preliminary Technical Data AD9211

DIGITAL SPECIFICATIONS

Table 3 (AVDD = 1.8 V, DRVDD = 1.8 V, T

AD9211-170/-200 AD9211-250
Parameter Temp Min Typ Max Min Typ Max Unit

CLOCK INPUTS

Differential Input Voltage1 Full tbd tbd V
Common-Mode Voltage2 Full tbd tbd V
Input Resistance Full tbd tbd kΩ
Input Capacitance 25°C 4 4 pF
LOGIC INPUTS
Logic 1 Voltage Full .8 x VDD 2.0 V
Logic 0 Voltage Full .2 x AVDD 0.8 V
Logic 1 Input Current Full 10 10 μA
Logic 0 Input Current Full 10 10 μA
Input Capacitance 25°C 4 4 pF
LOGIC OUTPUTS3
VOD Differential Output Voltage Full 247 454 247 454 mV
VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V
Output Coding Twos Complement, or Binary Twos Complement, or Binary

1

All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+)– (CLK–)| > 200 mV.

2

Clock inputs’ common mode can be externally set, such that xx.xV < (Clk+ or Clk- ) < zzz V.

3

LVDS R

Termination

= 100 Ω

= –40°C, T

MIN

= +85°C, DCS Enabled unless otherwise noted.)

MAX

Rev. PrA | Page 5 of 21

AD9211 Preliminary Technical Data

SWITCHING SPECIFICATIONS

Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, T

AD9211-170/-200 AD9211-250
Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit

Maximum Conversion Rate1 Full 170/200
Minimum Conversion Rate

1

Full

CLK+ Pulsewidth High (tEH)1 Full TBD
CLK+ Pulsewidth Low (tEL)1 Full TBD
OUTPUT (LVDS)
Valid Time (tV) Full TBD TBD ns
Propagation Delay (tPD) Full 3.9 3.9 ns
Rise Time (tR) (20% to 80%) 25°C 0.4 0.4 ns
Fall Time (tF) (20% to 80%) 25°C 0.4 0.4 ns
DCO Propagation Delay (t
Data to DCO Skew (tPD– t

) Full 3.2 3.2 ns

CPD

) Full TBD TBD ns

CPD

Latency (L) Full 5 5 Cycles
Aperture Delay (tA) 25°C TBD TBD ns
Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms
Out of Range Recovery Time 25°C TBD TBD Cycles

1

All ac specifications tested by driving CLK+ and CLK– differentially.

= –40°C, T

MIN

= +85°C, DCS Enabled unless otherwise noted.)

MAX

250
40
TBD
TBD

MSPS
40 MSPS
ns
ns

AIN

CLK+
CLK–

DATA

OUT

DCO+
DCO–

N–1

t

A

N

N+L+1

N+1

L CYCLES

t

EH

t

CPD

t

EL

1/f

S

t

PD

N–L

Figure 2. Timing Diagram (L=5 Cycles)

t

V

N-L+1 N N+1 N+2

N+L

N+L+2

N+L+3

Rev. PrA | Page 6 of 21

Preliminary Technical Data AD9211

ABSOLUTE MAXIMUM RATINGS

Parameter Rating
AVDD 2.0 V
DRVDD 2.0V
Analog Inputs –0.5 V to AVDD + 0.5 V
Digital Inputs –0.5 V to DRVDD + 0.5 V
REFIN Inputs –0.5 V to AVDD + 0.5 V
Digital Output Current 20 mA
Operating Temperature –40ºC to +125°C
Storage Temperature –65ºC to +150°C
Maximum Junction

Temperature
Maximum Case Temperature 150°C
θJA 2 TBD°C/W

1Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.

2 Typical θ

with solid ground plane.

= TBD C/W (heat slug soldered) for multilayer board in still air

JA

150°C

1

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrA | Page 7 of 21