Analog Devices AD9201 Datasheet

Dual Channel, 20 MHz 10-Bit

FEATURES Complete Dual Matching ADCs Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.4 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 57.8 dB Over Nine Effective Bits Spurious-Free Dynamic Range: –73 dB No Missing Codes Guaranteed 28-Lead SSOP

PRODUCT DESCRIPTION

The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The AD9201 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz sampling rate and wide input bandwidth will cover both narrowband and spread-spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers.

Each ADC incorporates a simultaneous sampling sample-andhold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer.

The AD9201 is manufactured on an advanced low cost CMOS process, operates from a single supply from 2.7 V to 5.5 V, and consumes 215 mW of power (on 3 V supply). The AD9201 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond its 10 MHz Nyquist input frequencies.

Resolution CMOS ADC

AD9201

FUNCTIONAL BLOCK DIAGRAM

IINA IINB

IREFB IREFT

QREFB QREFT

VREF

REFSENSE

QINB QINA

AVDD AVSS

"I" ADC

REFERENCE

BUFFER

"Q" ADC

CLOCK

ASYNCHRONOUS

MULTIPLEXER

PRODUCT HIGHLIGHTS

1. Dual 10-Bit, 20 MSPS ADCs A pair of high performance 20 MSPS ADCs that are optimized for spurious free dynamic performance are provided for encoding of I and Q or diversity channel information.

2. Low Power Complete CMOS Dual ADC function consumes a low 215 mW on a single supply (on 3 V supply). The AD9201 operates on supply voltages from 2.7 V to 5.5 V.

3. On-Chip Voltage Reference The AD9201 includes an on-chip compensated bandgap voltage reference pin programmable for 1 V or 2 V.

4. On-chip analog input buffers eliminate the need for external op amps in most applications.

5. Single 10-Bit Digital Output Bus The AD9201 ADC outputs are interleaved onto a single output bus saving board space and digital pin count.

6. Small Package The AD9201 offers the complete integrated function in a compact 28-lead SSOP package.

7. Product Family The AD9201 dual ADC is pin compatible with a dual 8-bit ADC (AD9281) and has a companion dual DAC product, the AD9761 dual DAC.

DVDD DVSS

AD9201

THREE-

STATE OUTPUT BUFFER

SLEEP SELECT

DATA 10 BITS

CHIP SELECT

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

AD9201–SPECIFICATIONS

(AVDD = +3 V, DVDD = +3 V, F internal ref, differential input signal, unless otherwise noted)

= 20 MSPS, VREF = 2 V, INB = 0.5 V, T

SAMPLE

MIN

to T

Parameter Symbol Min Typ Max Units Condition

RESOLUTION 10 Bits

CONVERSION RATE F

20 MHz

DC ACCURACY

Differential Nonlinearity DNL ±0.4 LSB REFT = 1 V, REFB = 0 V

Integral Nonlinearity INL 1.2 LSB

Differential Nonlinearity (SE) DNL ±0.5 ±1 LSB REFT = 1 V, REFB = 0 V Integral Nonlinearity (SE) INL ±1.5 ±2.5 LSB

Zero-Scale Error, Offset Error E Full-Scale Error, Gain Error E

±1.5 ±3.8 % FS ±3.5 ±5.4 % FS

Gain Match ±0.5 LSB Offset Match ±5 LSB

ANALOG INPUT

Input Voltage Range AIN –0.5 AVDD/2 V Input Capacitance C Aperture Delay t Aperture Uncertainty (Jitter) t

2pF 4ns

2ps Aperture Delay Match 2 ps Input Bandwidth (–3 dB) BW

Small Signal (–20 dB) 240 MHz Full Power (0 dB) 245 MHz

INTERNAL REFERENCE

Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF

Output Voltage Tolerance (1 V Mode) ±10 mV

Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND

Output Voltage Tolerance (2 V Mode) ±15 mV Load Regulation (1 V Mode) ±28 mV 1 mA Load Current Load Regulation (2 V Mode) ±15 mV 1 mA Load Current

POWER SUPPLY

Operating Voltage AVDD 2.7 3 5.5 V AVDD – DVDD ≤ 2.3 V

DRVDD 2.7 3 5.5 V

Supply Current I

Power Consumption P

AVDD

DRVDD

71.6 mA AVDD = 3 V

0.1 mA

215 245 mW AVDD = DVDD = 3 V Power-Down 15.5 mW STBY = AVDD, Clock = AVSS Power Supply Rejection PSR 0.8 1.3 % FS

DYNAMIC PERFORMANCE

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 55.6 57.3 dB f = 10 MHz 55.8 dB

Signal-to-Noise SNR

f = 3.58 MHz 55.9 57.8 dB f = 10 MHz 56.2 dB

Total Harmonic Distortion THD

f = 3.58 MHz –69 –63.3 dB f = 10 MHz –66.3 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz –66 –73 dB f = 10 MHz –70.5 dB

Two-Tone Intermodulation Distortion

IMD –62 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 % F

= 14.3 MHz

Crosstalk Rejection 68 dB

MAX,

–2–

REV. D

Parameter Symbol Min Typ Max Units Condition

DYNAMIC PERFORMANCE (SE)

Signal-to-Noise and Distortion SINAD

f = 3.58 MHz 52.3 dB

Signal-to-Noise SNR

f = 3.58 MHz 55.5 dB

Total Harmonic Distortion THD

f = 3.58 MHz –55 dB

Spurious Free Dynamic Range SFDR

f = 3.58 MHz –58 dB

DIGITAL INPUTS

High Input Voltage V Low Input Voltage V DC Leakage Current I Input Capacitance C

2.4 V

0.3 V

±6 µA

2pF

LOGIC OUTPUT (with DVDD = 3 V)

High Level Output Voltage

= 50 µA) V

2.88 V

Low Level Output Voltage

(IOL = 1.5 mA) V

0.095 V

LOGIC OUTPUT (with DVDD = 5 V)

High Level Output Voltage

= 50 µA) V

4.5 V

Low Level Output Voltage

= 1.5 mA) V

Data Valid Delay t MUX Select Delay t Data Enable Delay t

0.4 V 11 ns 7ns 13 ns CL = 20 pF. Output Level to

90% of Final Value

Data High-Z Delay t

DHZ

13 ns

CLOCKING

Clock Pulsewidth High t Clock Pulsewidth Low t

22.5 ns

Pipeline Latency 3.0 Cycles

NOTES

AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.

IMD referred to larger of two input signals.

SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.

Specifications subject to change without notice.

AD9201

REV. D

CLOCK

INPUT

SELECT

INPUT

DATA

OUTPUT

ADC SAMPLE#1ADC SAMPLE

OUTPUT ENABLED

SAMPLE #1-3

Q CHANNEL

OUTPUT

Q CHANNEL

ADC SAMPLE #3

SAMPLE #1-1

Q CHANNEL

OUTPUT

SAMPLE #1-2

Q CHANNEL

OUTPUT

Figure 1. ADC Timing

–3–

ADC SAMPLE #4

SAMPLE #1-1 I CHANNEL OUTPUT

SAMPLE #1 Q CHANNEL OUTPUT

SAMPLE #1

I CHANNEL

OUTPUT

ADC SAMPLE #5

I CHANNEL OUTPUT ENABLED

SAMPLE #2 Q CHANNEL OUTPUT

AD9201

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V DVDD DVSS –0.3 +6.5 V AVSS DVSS –0.3 +0.3 V AVDD DVDD –6.5 +6.5 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V AINA, AINB AVSS –1.0 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V REFSENSE AVSS –0.3 AVDD + 0.3 V REFT, REFB AVSS –0.3 AVDD + 0.3 V

Junction Temperature +150 °C Storage Temperature –65 +150 °C

Lead Temperature

10 sec +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options*

AD9201ARS –40°C to +85°C 28-Lead SSOP RS-28

AD9201-EVAL Evaluation Board

*RS = Shrink Small Outline.

PIN CONFIGURATION

DVSS

DVDD

(LSB) D0

(MSB) D9

SELECT

CLOCK

D1 D2 D3 D4 D5 D6 D7 D8

AD9201

TOP VIEW

(Not to Scale)

CHIP-SELECT INA-Q INB-Q REFT-Q REFB-Q AVDD VREF REFSENSE AVSS REFB-I REFT-I INB-I INA-I SLEEP

PIN FUNCTION DESCRIPTIONS

No. Name Description

1 DVSS Digital Ground 2 DVDD Digital Supply 3 D0 Bit 0 (LSB) 4 D1 Bit 1 5 D2 Bit 2 6 D3 Bit 3 7 D4 Bit 4 8 D5 Bit 5 9 D6 Bit 6 10 D7 Bit 7 11 D8 Bit 8 12 D9 Bit 9 (MSB)

13 SELECT Hi I Channel Out, Lo Q Channel Out 14 CLOCK Clock 15 SLEEP Hi Power Down, Lo Normal Operation

16 INA-I I Channel, A Input 17 INB-I I Channel, B Input 18 REFT-I Top Reference Decoupling, I Channel 19 REFB-I Bottom Reference Decoupling, I Channel 20 AVSS Analog Ground 21 REFSENSE Reference Select 22 VREF Internal Reference Output 23 AVDD Analog Supply 24 REFB-Q Bottom Reference Decoupling, Q Channel 25 REFT-Q Top Reference Decoupling, Q Channel 26 INB-Q Q Channel, B Input 27 INA-Q Q Channel, A Input 28 CHIP-SELECT Hi-High Impedance, Lo-Normal Operation

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

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AVDD

DRVDD

AVDD

AD9201

AVDD

AVSS

DRVSS

AVSS

a. D0–D9, OTR b. Three-State, Standby c. CLK

AVDD

AVSS

AVDD

REFBS

AVSS

REFBF

d. INA, INB e. Reference f. REFSENSE g. VREF

Figure 2. Equivalent Circuits

OFFSET ERROR

The first transition should occur at a level 1 LSB above “zero.” Offset is defined as the deviation of the actual first code transition from that point.

OFFSET MATCH

The change in offset error between I and Q channels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

It is possible to get a measure of performance expressed as N, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

AVSS

AVDD

AVSS

AVDD

AVSS

scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions.

GAIN MATCH

The change in gain error between I and Q channels.

PIPELINE DELAY (LATENCY)

The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising clock edge.

MUX SELECT DELAY

The delay between the change in SELECT pin data level and valid data on output pins.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the Sample-and-Hold Amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference in dB between the rms amplitude of the input signal and the peak spurious signal.

GAIN ERROR

The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full

REV. D

–5–

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

AD9201

INPUT FREQUENCY – Hz

1.00E+05

SNR – dB

1.00E+06 1.00E+07 1.00E+08

–6dB

–20dB

–0.5dB

–Typical Characteristic Curves

(AVDD = +3 V, DVDD = +3 V, FS = 20 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted)

1.5

1.0

0.5

INL

–0.5

–1.0

–1.5

0 768128

Figure 3. Typical INL (1 V Internal Reference)

256 384 512 640

CODE OFFSET

896 1024

Figure 6. SNR vs. Input Frequency

0.5

DNL

–0.5

–1.0

256 384 512 640

128

CODE OFFSET

768

896 1024

Figure 4. Typical DNL (1 V Internal Reference)

1.00

0.80

0.60

0.40

0.20

0.00

– nA

–0.20

–0.40

–0.60

–0.80 –1.00

–1.0 2.0–0.5

0 0.5 1.0 1.5

INPUT VOLTAGE – V

Figure 5. Input Bias Current vs. Input Voltage

SINAD – dB

1.00E+05

–0.5dB

–6dB

–20dB

1.00E+06 1.00E+07 1.00E+08 INPUT FREQUENCY – Hz

Figure 7. SINAD vs. Input Frequency

–30

–35

–40

–45

–50 –55

THD – dB

–60

–65

–70

–75 –80

1.00E+05

–20dB

–6dB

–0.5dB

1.00E+06 1.00E+07 1.00E+08

INPUT FREQUENCY – Hz

Figure 8. THD vs. Input Frequency

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