Analog Devices AD9200SSOP, AD9200LQFP, AD9200KSTRL, AD9200KST, AD9200JSTRL Datasheet
...
Complete 10-Bit, 20 MSPS, 80 mW
a
FEATURES
CMOS 10-Bit, 20 MSPS Sampling A/D Converter
Pin-Compatible with AD876
Power Dissipation: 80 mW (3 V Supply)
Operation Between 2.7 V and 5.5 V Supply
Differential Nonlinearity: 0.5 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
PRODUCT DESCRIPTION
The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9200 uses a multistage
differential pipeline architecture at 20 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9200 has been designed to ease the development of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold (SHA) amplifier is equally suited for both
multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit (AD9200ARS, AD9200KST). The dynamic performance is excellent.
The AD9200 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
FUNCTIONAL BLOCK DIAGRAM
CMOS A/D Converter
AD9200
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9200 can operate with supply range from 2.7 V to
5.5 V, ideally suiting it for low power operation in high speed
portable applications.
The AD9200 is specified over the industrial (–40°C to +85°C)
and commercial (0°C to +70°C) temperature ranges.
PRODUCT HIGHLIGHTS
Low Power
The AD9200 consumes 80 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9200 is available in both a 28-lead SSOP and 48-lead
LQFP packages.
Pin Compatible with AD876
The AD9200 is pin compatible with the AD876, allowing older
designs to migrate to lower supply voltages.
300 MHz On-Board Sample-and-Hold
The versatile SHA input can be configured for either singleended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9200’s input range.
Built-In Clamp Function
Allows dc restoration of video signals with AD9200ARS and
AD9200KST.
CLAMP
CLAMP
AIN
REFTS
REFBS
REFTF
REFBF
VREF
REFSENSE
IN
SHA SHAGAIN SHA GAINGAIN
SHA
AVSS
1V
A/D
D/A
A/D
AD9200
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DRVDDAVDDCLK
STBY
SHA GAIN
A/D
D/A A/D
CORRECTION LOGIC
OUTPUT BUFFERS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
D/A
DRVSS
A/D
D/A
MODE
THREE-
STATE
OTR
D9
(MSB)
D0
(LSB)
(AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
AD9200–SPECIFICATIONS
Span from 0.5 V to 2.5 V, External Reference, T
Parameter Symbol Min Typ Max Units Condition
RESOLUTION 10 Bits
CONVERSION RATE F
S
20 MHz
DC ACCURACY
Differential Nonlinearity DNL ±0.5 ±1 LSB REFTS = 2.5 V, REFBS = 0.5 V
Integral Nonlinearity INL ±0.75 ±2 LSB
Offset Error E
Gain Error E
ZS
FS
0.4 1.2 % FSR
1.4 3.5 % FSR
REFERENCE VOLTAGES
Top Reference Voltage REFTS 1 AVDD V
Bottom Reference Voltage REFBS GND AVDD – 1 V
Differential Reference Voltage 2 V p-p
Reference Input Resistance
1
10 kΩ REFTS, REFBS: MODE = AVDD
4.2 kΩ Between REFTF and REFBF: MODE = AVSS
ANALOG INPUT
Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD
Input Capacitance C
Aperture Delay t
Aperture Uncertainty (Jitter) t
IN
AP
AJ
1 pF Switched
4ns
2ps
Input Bandwidth (–3 dB) BW
Full Power (0 dB) 300 MHz
DC Leakage Current 23 µA Input = ±FS
INTERNAL REFERENCE
Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF
Output Voltage Tolerance (1 V Mode) ±10 ±25 mV
Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND
Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current
POWER SUPPLY
Operating Voltage AVDD 2.7 3 5.5 V
DRVDD 2.7 3 5.5 V
Supply Current IAVDD 26.6 33.3 mA AVDD = 3 V, MODE = AVSS
Power Consumption P
D
80 100 mW AVDD = DRVDD = 3 V, MODE = AVSS
Power-Down 4 mW STBY = AVDD, MODE and CLOCK =
AVSS
Gain Error Power Supply Rejection PSRR 1 % FS
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion SINAD
f = 3.58 MHz 54.5 57 dB
f = 10 MHz 54 dB
Effective Bits
f = 3.58 MHz 9.1 Bits
f = 10 MHz 8.6 Bits
Signal-to-Noise SNR
f = 3.58 MHz 55 57 dB
f = 10 MHz 56 dB
Total Harmonic Distortion THD
f = 3.58 MHz –59 –66 dB
f = 10 MHz –58 dB
Spurious Free Dynamic Range SFDR
f = 3.58 MHz –61 –69 dB
f = 10 MHz –61 dB
Two-Tone Intermodulation
Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz
Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp
Differential Gain DG 0.05 %
MIN
to T
unless otherwise noted)
MAX
–2–
REV. E
Parameter Symbol Min Typ Max Units Condition
DIGITAL INPUTS
High Input Voltage V
Low Input Voltage V
IH
IL
2.4 V
0.3 V
DIGITAL OUTPUTS
High-Z Leakage I
Data Valid Delay t
Data Enable Delay t
Data High-Z Delay t
OZ
OD
DEN
DHZ
–10 +10 µA Output = GND to VDD
25 ns CL = 20 pF
25 ns
13 ns
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I
= 50 µA) V
OH
= 0.5 mA) V
OH
= 1.6 mA) V
OL
= 50 µA) V
OL
OH
OH
OL
OL
+2.95 V
+2.80 V
+0.4 V
+0.05 V
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I
= 50 µA) V
OH
= 0.5 mA) V
OH
= 1.6 mA) V
OL
= 50 µA) V
OL
OH
OH
OL
OL
+4.5 V
+2.4 V
+0.4 V
+0.1 V
CLOCKING
Clock Pulsewidth High t
Clock Pulsewidth Low t
CH
CL
22.5 ns
22.5 ns
Pipeline Latency 3 Cycles
CLAMP
NOTES
1
2
Specifications subject to change without notice.
2
Clamp Error Voltage E
Clamp Pulsewidth t
See Figures 1a and 1b.
Available only in AD9200ARS and AD9200KST.
OC
CPW
±20 ±40 mV CLAMPIN = 0.5 V–2.7 V, RIN = 10 Ω
2 µsC
= 1 µF (Period = 63.5 µs)
IN
AD9200
REV. E
AV
DD
REFTS
REFBS
MODE
10kV
10kV
AD9200
0.4 3 V
DD
REFTS
REFTF
REFBF
REFBS
MODE
Figure 1a. Figure 1b.
–3–
AD9200
4.2kV
AD9200
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
AVSS DRVSS –0.3 +0.3 V
AVDD DRVDD –6.5 +6.5 V
MODE AVSS –0.3 AVDD + 0.3 V
CLK AVSS –0.3 AVDD + 0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
AIN AVSS –0.3 AVDD + 0.3 V
VREF AVSS –0.3 AVDD + 0.3 V
REFSENSE AVSS –0.3 AVDD + 0.3 V
REFTF, REFTB AVSS –0.3 AVDD + 0.3 V
REFTS, REFBS AVSS –0.3 AVDD + 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
10 sec +300 °C
AVDD
DRVDD
AVDD
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Options*
AD9200JRS 0°C to +70°C 28-Lead SSOP RS-28
AD9200ARS –40°C to +85°C 28-Lead SSOP RS-28
AD9200JST 0°C to +70°C 48-Lead LQFP ST-48
AD9200KST 0°C to +70°C 48-Lead LQFP ST-48
AD9200JRSRL 0°C to +70°C 28-Lead SSOP (Reel) RS-28
AD9200ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28
AD9200JSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48
AD9200KSTRL 0°C to +70°C 48-Lead LQFP (Reel) ST-48
AD9200 SSOP-EVAL Evaluation Board
AD9200 LQFP-EVAL Evaluation Board
*RS = Shrink Small Outline; ST = Thin Quad Flatpack.
AVDD
AVDD
AVDD
DRVSS
DRVSS
AVSS
a. D0–D9, OTR
AVDD
AVSS
b. Three-State, Standby, Clamp
d. AIN
AVDD
AVSS
f. CLAMPIN g. MODE
AVDD
AVSS
AVSS
REFBS
REFBF
AVDD
AVDD
AVSS
AVSS
AVSS
e. Reference
AVDD
AVSS
h. REFSENSE
Figure 2. Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9200 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REFTF
REFTS
AVSS
AVDD
AVDD
AVSS
c. CLK
AVSS
AVSS
AVDD
AVSS
i. VREF
REV. E
PIN CONFIGURATIONS
28-Lead Shrink Small Outline (SSOP)
AD9200
48-Lead Plastic Thin Quad Flatpack (LQFP)
AVSS
DRVDD
OTR
DRVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
1
2
3
4
5
AD9200
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
AVDD
28
AIN
27
VREF
26
REFBS
25
REFBF
24
23
MODE
REFTF
22
REFTS
21
20
CLAMPIN
19
CLAMP
18
REFSENSE
17
STBY
16
THREE-STATE
15
CLK
D0
D1
D2
D3
D4
NC
NC
D5
D6
D7
D8
D9
NC = NO CONNECT
NC
NC
DRVDD
NC
48 47 46 45 44 39 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
TOP VIEW
(Not to Scale)
NC
OTR
NC
AVSS
AD9200
NC
DRVSS
AVDD
NC
NC
NC
NC
NC
AIN
CLK
VREF
NC
36
35
34
33
32
31
30
29
28
27
26
25
STBY
THREE-STATE
PIN FUNCTION DESCRIPTIONS
SSOP LQFP
Pin No. Pin No. Name Description
1 44 AVSS Analog Ground
2 45 DRVDD Digital Driver Supply
3 1 D0 Bit 0, Least Significant Bit
4 2 D1 Bit 1
5 3 D2 Bit 2
6 4 D3 Bit 3
7 5 D4 Bit 4
8 8 D5 Bit 5
9 9 D6 Bit 6
10 10 D7 Bit 7
11 11 D8 Bit 8
12 12 D9 Bit 9, Most Significant Bit
13 16 OTR Out-of-Range Indicator
14 17 DRVSS Digital Ground
15 22 CLK Clock Input
16 23 THREE-STATE HI: High Impedance State. LO: Normal Operation
17 24 STBY HI: Power-Down Mode. LO: Normal Operation
18 26 REFSENSE Reference Select
19 27 CLAMP HI: Enable Clamp Mode. LO: No Clamp
20 28 CLAMPIN Clamp Reference Input
21 29 REFTS Top Reference
22 30 REFTF Top Reference Decoupling
23 32 MODE Mode Select
24 34 REFBF Bottom Reference Decoupling
25 35 REFBS Bottom Reference
26 38 VREF Internal Reference Output
27 39 AIN Analog Input
28 42 AVDD Analog Supply
NC
REFBS
REFBF
NC
MODE
NC
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
NC
REV. E
–5–
AD9200
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale”. The
point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
(AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Typical Characterization Curves
1.0
0.5
0
DNL
Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
Offset Error
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transition from that point.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference
between the first and last code transitions.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.
60
55
50
45
40
SNR– dB
35
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
–0.5
–1.0
1.0
0.5
INL
–0.5
–1.0
0 1024128
0
0 1024128
256 384 512 640 768 896
CODE OFFSET
Figure 3. Typical DNL
256 384 512 640 768 896
CODE OFFSET
Figure 4. Typical INL
30
25
20
1.00E+05 1.00E+081.00E+06 1.00E+07
INPUT FREQUENCY – Hz
Figure 5. SNR vs. Input Frequency
60
55
50
45
40
SINAD – dB
35
30
25
20
1.00E+05 1.00E+081.00E+06
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
INPUT FREQUENCY – Hz
1.00E+07
Figure 6. SINAD vs. Input Frequency
–6–
REV. E
AD9200
–30
–35
–40
–45
–50
–55
THD – dB
–60
–65
–70
–75
–80
1.00E+05 1.00E+081.00E+06 1.00E+07
–20.0 AMPLITUDE
–6.0 AMPLITUDE
–0.5 AMPLITUDE
INPUT FREQUENCY – Hz
Figure 7. THD vs. Input Frequency
–70
F
–60
–50
–40
–30
THD – dB
–20
–10
0
100E+03 100E+061E+06
CLOCK FREQUENCY – Hz
IN
= 1MHz
10E+06
CLOCK = 20MHz
80.5
80.5
80.0
80.0
79.5
79.5
79.0
79.0
78.5
78.5
78.0
78.0
POWER CONSUMPTION – mW
POWER CONSUMPTION – mW
77.5
77.5
77.0
77.0
0202
0202
4
6 8 10 12 14 16 18
4
6 8 10 12 14 16 18
CLOCK FREQUENCY – MHz
CLOCK FREQUENCY – MHz
Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)
1M
900k
800k
700k
600k
500k
HITS
400k
300k
200k
100k
54383
0
N–1 N
499856
CODE
54160
N+1
Figure 8. THD vs. Clock Frequency
1.005
1.004
1.003
1.002
– V
REF
V
1.001
1.000
0.999
0.998
–40 100–20
0
20 40 60 80
TEMPERATURE – °C
Figure 9. Voltage Reference Error vs. Temperature
Figure 11. Grounded Input Histogram
20
0
–20
–40
–60
–80
–100
–120
–140
0E+0 10E+61E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6
SINGLE TONE FREQUENCY DOMAIN
CLOCK = 20MHz
Figure 12. Single-Tone Frequency Domain
REV. E
–7–
AD9200
0
–3
–6
–9
–12
–15
–18
SIGNAL AMPLITUDE – dB
–21
–24
–27
1.0E+6 1.0E+910.0E+6
FREQUENCY – Hz
100.0E+6
Figure 13. Full Power Bandwidth
25
20
15
10
5
0
– mA
B
I
–5
–10
–15
–20
–25
0 3.01.0 2.0
INPUT VOLTAGE – V
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 20MHz
2.50.5 1.5
Figure 14. Input Bias Current vs. Input Voltage
APPLYING THE AD9200
THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9200 distributes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distributed conversion, the AD9200 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9200 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876 A/D.
To realize this flexibility, internal switches on the AD9200 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections, as well as the Table I should
assist in picking the desired mode.
Table I. Mode Selection
Input Input MODE REFSENSE
Modes Connect Span Pin Pin REF REFTS REFBS Figure
TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18
AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19
CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20
AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2
Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29
REFTS and
REFBS Are
Shorted Together
for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2
External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22
– REFBS (2 V max)
AGND Short to Short to 23
VREFTF VREFBF
AD876 AIN 2 V Float or AVDD No Connect Short to Short to 30
AVSS VREFTF VREFBF
–8–
REV. E
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