Analog Devices AD9054A d Datasheet
8-Bit, 200 MSPS
ENCODE
ENCODE
AD9054A
T/H
AIN
AIN
GND
2.5V REFERENCE
8
8
ENCODE
LOGIC
DEMULTIPLEXER
V
DD
DS
DS
DEMUX
QUANTIZER
VREF IN VREF OUT
DA7–DA
0
DB7–DB
0
TIMING
a
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal 2.5 V Reference and T/H
Low Power: 500 mW
5 V Single Supply Operation
TTL Output Interface
Single or Demultiplexed Output Ports
APPLICATIONS
RGB Graphics Processing
High Resolution Video
Digital Data Storage Read Channels
Digital Communications
Digital Instrumentation
Medical Imaging
GENERAL DESCRIPTION
The AD9054A is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, the AD9054A
includes an internal 2.5 V reference and track-and-hold circuit.
The user provides only a 5 V power supply and an encode clock.
No external reference or driver components are required for
many applications.
A/D Converter
AD9054A
FUNCTIONAL BLOCK DIAGRAM
The AD9054A’s encode input interfaces directly to TTL, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual-channel or singlechannel digital outputs. The dual (demultiplexed) mode interleaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the singlechannel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
Fabricated with an advanced BiCMOS process, the AD9054A is
provided in a space-saving 44-lead LQFP surface mount plastic
package (ST-44) and specified over the full industrial (–40°C to
+85°C) temperature range.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9054A–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(VDD = 5 V, external reference, fS = max unless otherwise noted.)
Test AD9054ABST-200 AD9054ABST-135
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25°CI ± 0.9 +1.5/–1.0 ± 0.9 +1.5/–1.0 LSB
Full VI ± 1.0 +2.0/–1.0 ± 1.0 +2.0/–1.0 LSB
Integral Nonlinearity 25°CI ± 0.6 ± 1.5 ± 0.6 ± 1.5 LSB
Full VI ± 0.9 ± 2.0 ± 0.9 ± 2.0 LSB
No Missing Codes Full VI Guaranteed Guaranteed
Gain Error
Gain Tempco
1
1
25°CI ± 2 ± 7 ± 2 ± 7% FS
Full V 160 160 ppm/°C
ANALOG INPUT
Input Voltage Range
(With Respect to AIN) Full V ±512 ± 512 mV p-p
Compliance Range AIN or AIN Full V 1.8 3.2 1.8 3.2 V
Input Offset Voltage 25°CI ± 4 ± 16 ± 4 ± 16 mV
Full VI ± 8 ± 19 ± 8 ± 19 mV
Input Resistance 25°C I 36 62 36 62 kΩ
Full VI 23 23 kΩ
Input Capacitance 25°CV 4 4 pF
Input Bias Current 25°C I 25 50 25 50 µA
Analog Bandwidth, Full Power
2
Full VI 75 75 µA
25°C V 350 350 MHz
REFERENCE OUTPUT
Output Voltage Full VI 2.4 2.5 2.6 2.4 2.5 2.6 V
Temperature Coefficient Full V 110 110 ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate (fS) Full VI 200 135 MSPS
Minimum Conversion Rate (f
Encode Pulsewidth High (t
Encode Pulsewidth Low (t
Aperture Delay (t
)25°C V 0.5 0.5 ns
A
) Full IV 25 25 MSPS
S
)25°C IV 2.0 22 3.0 22 ns
EH
)25°C IV 2.0 22 3.0 22 ns
EL
Aperture Uncertainty (Jitter) 25°C V 2.3 2.3 ps rms
Data Sync Setup Time (t
Data Sync Hold Time (t
Data Sync Pulsewidth (t
Output Valid Time (t
Output Propagation Delay (tPD)
DIGITAL INPUTS
HIGH Level Current (IIH)
LOW Level Current (I
)25°CIV 0 0 ns
SDS
)25°C IV 0.5 0.5 ns
HDS
)25°C IV 2.0 2.0 ns
PWDS
3
)
V
IL
3
4
4
)
Full VI 2.7 5.1 2.7 5.7 ns
Full VI 5.9 7.9 7.5 8.5 ns
Full VI 500 625 500 625 µA
Full VI 500 625 500 625 µA
Input Capacitance 25°CV 3 3 pF
DIFFERENTIAL INPUTS
Differential Signal Amplitude (VID) Full IV 400 400 mV
HIGH Input Voltage (V
LOW Input Voltage (V
IHD
ILD
Common-Mode Input (V
) Full IV 1.5 V
DD
) Full IV 0 VDD – 0.4 0 VDD – 0.4 V
) Full IV 1.5 1.5 V
ICM
1.5 V
DD
V
DEMUX INPUT
HIGH Input Voltage (VIH) Full IV 2.0 V
DD
2.0 V
DD
V
LOW Input Voltage (VIL) Full IV 0 0.8 0 0.8 V
DIGITAL OUTPUTS
HIGH Output Voltage (VOH) Full VI 2.4 2.4 V
LOW Output Voltage (V
) Full VI 0.4 0.4 V
OL
Output Coding Binary Binary
–2–
REV. D
AD9054A
Test AD9054ABST-200 AD9054ABST-135
Parameter Temp Level Min Typ Max Min Typ Max Unit
POWER SUPPLY
V
Supply Current (IDD) Full VI 128 156 120 140 mA
DD
Power Dissipation
Power Supply Sensitivity
DYNAMIC PERFORMANCE
Transient Response 25°C V 1.5 1.5 ns
Overvoltage Recovery Time 25°C V 1.5 1.5 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
= 19.7 MHz 25°CIV 4245 4245 dB
IN
= 49.7 MHz 25°C I 42 45 42 45 dB
f
IN
f
= 70.1 MHz 25°C I 42 45 dB
IN
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
= 19.7 MHz 25°CIV 4043 4043 dB
f
IN
fIN = 49.7 MHz 25°C I 40 43 40 43 dB
fIN = 70.1 MHz 25°C I 39 42 dB
Effective Number of Bits
= 19.7 MHz 25°C IV 6.35 6.85 6.35 6.85 Bits
f
IN
= 49.7 MHz 25°C I 6.35 6.85 6.35 6.85 Bits
f
IN
= 70.1 MHz 25°C I 6.18 6.85 Bits
f
IN
2nd Harmonic Distortion
fIN = 19.7 MHz 25°C IV 58 63 58 63 dBc
= 49.7 MHz 25°C I 54 59 54 59 dBc
f
IN
f
= 70.1 MHz 25°C I 49 55 dBc
IN
3rd Harmonic Distortion
= 19.7 MHz 25°C IV 48 56 48 56 dBc
f
IN
f
= 49.7 MHz 25°C I 48 54 48 54 dBc
IN
= 70.1 MHz 25°C I 43 50 dBc
f
IN
Two-Tone Intermod Distortion
(IMD)
= 19.7 MHz 25°C V 60 60 dBc
f
IN
= 49.7 MHz 25°C V 55 55 dBc
f
IN
fIN = 70.1 MHz 25°C V 50 dBc
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2
3 dB bandwidth with full-power input signal.
3
tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load during test is 5 pF (Refer to
equivalent circuits Figures 5 and 6).
4
IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.5 mA.
5
Power dissipation is measured under the following conditions: analog input is –1 dBFS at 19.7 MHz.
6
Typical thermal impedance for the ST-44 (LQFP) 44-lead package (in still air): θJC = 20°C/W, θCA = 35°C/W, θJA = 55°C/W.
7
A change in input offset voltage with respect to a change in VDD.
8
SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.
5, 6
7
8
Full VI 640 781 600 700 mW
25°C I 0.005 0.015 0.005 0.015 V/V
Full V 45 45 dB
Full V 45 45 dB
Full V 45 dB
Full V 43 43 dB
Full V 43 43 dB
Full V 42 dB
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at speci-
fied temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
–3–REV. D
AD9054A
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . V
to 0.0 V
DD
to 0.0 V
DD
to 0.0 V
DD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Option*
AD9054ABST-200 –40°C to +85°C ST-44
AD9054ABST-135 –40°C to +85°C ST-44
AD9054A/PCB 25°C Evaluation Board
*ST = Plastic Thin Quad Flatpack (LQFP).
Table I. Output Coding
Step AIN–AIN Code Binary
255 ≥0.512 V 255 1111 1111
254 0.508 V 254 1111 1110
253 0.504 V 253 1111 1101
•• • •
•• • •
•• • •
129 0.006 V 129 1000 0001
128 0.002 V 128 1000 0000
127 –0.002 V 127 0111 1111
126 –0.006 V 126 0111 1110
•• • •
•• • •
•• • •
2 –0.504 V 2 0000 0010
1 –0.508 V 1 0000 0001
0 ≤–0.512 V 0 0000 0000
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9054A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. D
AD9054A
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
DB
1
DB
2
DB
3
GND
DA
2
DA
1
DA0 (LSB)
VDD
GND
VDD
DB
0
(LSB)
VREF OUT
GND
VDD
VDD
GND
VDD
GND
ENCODE
ENCODE
VDD
GND
VDD
GND
DA
7
(MSB)
DA
6DA5DA4DA3
DB
7
(MSB)
DB
6DB5DB4
DS
DS
DEMUX
VDD
GND
AIN
AIN
GND
VDD
GND
VREF IN
AD9054A
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Function
1 ENCODE Encode Clock for ADC (ADC
Samples on Rising Edge
of ENCODE)
2 ENCODE Encode Clock Complement
(ADC Samples on Falling Edge
of ENCODE)
3, 5, 15, 18, 28, VDD Power Supply (5 V)
30, 31, 36, 41
4, 6, 16, 17, 27, GND Ground
29, 32, 35, 37, 40
14–7 DA
19–26 DB
–DA
0
–DB
0
Digital Outputs of ADC Channel
7
A. DA
is the MSB, DA0 the LSB
7
Digital Outputs of ADC Channel
7
B. DB
is the MSB, DB0 the LSB
7
33 VREF OUT Internal Reference Output
(2.5 V typical); Bypass with
0.1 µF to Ground
34 VREF IN Reference Input for ADC (2.5 V
typical, ± 4%)
38 AIN Analog Input—Complement.
Connect to input signal midscale
reference.
39 AIN Analog Input—True
42 DEMUX Format Select. LOW = Dual.
Channel Mode, HIGH = Single.
Channel Mode (Channel A Only)
43 DS Data Sync Complement
44 DS Data Sync—Aligns Output Chan-
nels in Dual-Channel Mode
PIN CONFIGURATION
D
7–D0
AIN
ENCODE
ENCODE
SAMPLE N–1
SAMPLE N SAMPLE N+3 SAMPLE N+4
t
A
t
EH
t
EL
1/f
S
Figure 1. Timing—Single Channel Mode
SAMPLE N+2SAMPLE N+1
DATA N–2DATA N–3DATA N–4DATA N–5
–5–REV. D
t
PD
t
V
DATA NDATA N–1
AD9054A
AIN
ENCODE
ENCODE
DS
DS
PORT A
D
7–D0
PORT B
D
7–D0
t
HDS
DATA N–7
OR N–8
DATA N–8
OR N–7
SAMPLE N–1
SAMPLE N–1
t
EHtEL
t
SDS
t
PWDS
DATA N–6
OR N–7
SAMPLE N
t
A
t
HDS
DATA N–7
OR N–6
1/f
S
t
SDS
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
SAMPLE N+3 SAMPLE N+4 SAMPLE N+5
t
PD
DATA N–2
DATA N–3 DATA N–1
Figure 2a. Timing—Dual Channel Mode (One-Shot Data Sync)
SAMPLE N
SAMPLE N+3 SAMPLE N+4
t
V
SAMPLE N+5
SAMPLE N+6SAMPLE N+2SAMPLE N+1SAMPLE N–2
DATA N
DATA N+1
AIN
ENCODE
ENCODE
DS
DS
PORT A
D
7–D0
PORT B
D
7–D0
t
HDS
DATA N–7
OR N–8
DATA N–8
OR N–7
t
t
t
HDS
EL
DATA N–7
A
1/f
S
t
SDS
OR N–6
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
t
PD
DATA N–2
DATA N–3 DATA N–1
t
EH
t
SDS
t
PWDS
DATA N–6
OR N–7
Figure 2b. Timing—Dual Channel Mode (Continuous Data Sync)
SAMPLE N+6SAMPLE N+2SAMPLE N+1SAMPLE N–2
t
V
DATA N
DATA N+1
–6–
REV. D
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