ANALOG DEVICES AD8310 Service Manual
www.BDTIC.com/ADI
Fast, Voltage-Out DC–440 MHz,
FEATURES
Multistage demodulating logarithmic amplifier
Voltage output, rise time <15 ns
High current capacity: 25 mA into grounded R
95 dB dynamic range: −91 dBV to +4 dBV
Single supply of 2.7 V min at 8 mA typ
DC–440 MHz operation, ±0.4 dB linearity
Slope of +24 mV/dB, intercept of −108 dBV
Highly stable scaling over temperature
Fully differential dc-coupled signal path
100 ns power-up time, 1 mA sleep current
APPLICATIONS
Conversion of signal level to decibel form
Transmitter antenna power measurement
Receiver signal strength indication (RSSI)
Low cost radar and sonar signal processing
Network and spectrum analyzers
Signal-level determination down to 20 Hz
True-decibel ac mode for multimeters
GENERAL DESCRIPTION
The AD8310 is a complete, dc−440 MHz demodulating
logarithmic amplifier (log amp) with a very fast voltage mode
output, capable of driving up to 25 mA into a grounded load in
under 15 ns. It uses the progressive compression (successive
detection) technique to provide a dynamic range of up to 95 dB
to ±3 dB law conformance or 90 dB to a ±1 dB error bound up
to 100 MHz. It is extremely stable and easy to use, requiring no
significant external components. A single-supply voltage of
2.7 V to 5.5 V at 8 mA is needed, corresponding to a power
consumption of only 24 mW at 3 V. A fast-acting CMOScompatible enable pin is provided.
Each of the six cascaded amplif
signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz.
A total of nine detector cells are used to provide a dynamic
range that extends from −91 dBV (where 0 dBV is defined as
the amplitude of a 1 V rms sine wave), an amplitude of about
±40 μV, up to +4 dBV (or ±2.2 V). The demodulated output
is accurately scaled, with a log slope of 24 mV/dB and an
intercept of −108 dBV. The scaling parameters are supplyand temperature-independent.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ier/limiter cells has a small-
L
95 dB Logarithmic Amplifier
AD8310
FUNCTIONAL BLOCK DIAGRAM
MIRROR
2μA
/
dB
2
3kΩ
AD8310
COMM
1kΩ
COMM
+
–
3kΩ
COMM
SUPPLY
+INPUT
–INPUT
COMMON
5
8
1
2
VPOS
INHI
1.0kΩ
INLO
COMM
BAND GAP REFERENCE
8mA
3
NINE DETECTOR CELLS
AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
SPACED 14.3dB
INPUT-OFFSET
COMPENSATION LOOP
Figure 1.
The fully differential input offers a moderately high impedance
(1 kΩ in p
arallel with about 1 pF). A simple network can match
the input to 50 Ω and provide a power sensitivity of −78 dBm to
+17 dBm. The logarithmic linearity is typically within ±0.4 dB
up to 100 MHz over the central portion of the range, but it is
somewhat greater at 440 MHz. There is no minimum frequency
limit; the AD8310 can be used down to low audio frequencies.
Special filtering features are provided to support this wide
range.
The output voltage runs from a noise-limited lower boundary of
400 mV t
o an upper limit within 200 mV of the supply voltage
for light loads. The slope and intercept can be readily altered
using external resistors. The output is tolerant of a wide variety
of load conditions and is stable with capacitive loads of 100 pF.
The AD8310 provides a unique combination of low cost, small
ow power consumption, high accuracy and stability, high
size, l
dynamic range, a frequency range encompassing audio to UHF,
fast response time, and good load-driving capabilities, making
this product useful in numerous applications that require the
reduction of a signal to its decibel equivalent.
The AD8310 is available in the industrial temperature range of
o +85°C in an 8-lead MSOP package.
−40°C t
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
ENBL
BFIN
VOUT
OFLT
33pF
ENABLE
7
BUFFER
6
INPUT
4
OUTPUT
OFFSET
3
FILTER
01084-001
AD8310
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TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics .............................................6
Theory of Operation ........................................................................ 9
Progressive Compression ............................................................ 9
Slope and Intercept Calibration................................................ 10
Offset Control............................................................................. 10
Product Overview........................................................................... 11
Enable Interface.......................................................................... 11
Input Interface ............................................................................ 11
Offset Interface ...........................................................................12
Output Interface......................................................................... 12
Using the AD8310 .......................................................................... 14
dBV vs. dBm ............................................................................... 15
Input Matching ........................................................................... 15
Narrow-Band Matching ............................................................ 16
General Matching Procedure.................................................... 16
Slope and Intercept Adjustments ............................................. 17
Increasing the Slope to a Fixed Value...................................... 17
Output Filtering.......................................................................... 18
Lowering the High-Pass Corner Frequency of the Offset
Compensation Loop .................................................................. 18
Applications..................................................................................... 19
Cable-Driving............................................................................. 19
DC-Coupled Input..................................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions .......................................................................22
Ordering Guide .......................................................................... 22
Basic Connections...................................................................... 14
Transfer Function in Terms of Slope and Intercept ...............15
REVISION HISTORY
6/05—Rev. D to Rev. E
Changes to Figure 6.......................................................................... 6
Change to Basic Connections Section .........................................14
Changes to Equation 10................................................................. 17
Changes to Ordering Guide.......................................................... 22
10/04—Rev. C to Rev. D
ormat Updated..................................................................Universal
F
Typical Performance Characteristics Reordered.......................... 6
Changes to Figures 41 and 42....................................................... 20
7/03—Rev. B to Rev. C
Repl
aced TPC 12............................................................................... 5
Change to DC-Coupled Input Section ........................................14
Replaced Figure 20 .........................................................................15
Updated Outline Dimensions....................................................... 16
2/03—Rev. A to Rev. B
C
hange to Evaluation Board Section ........................................... 15
Change to Table III......................................................................... 16
Updated Outline Dimensions....................................................... 16
1/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
Rev. E | Page 2 of 24
AD8310
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SPECIFICATIONS
TA = 25°C, VS = 5 V, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
INPUT STAGE Inputs INHI, INLO
Maximum Input1 Single-ended, p-p ±2.0 ±2.2 V
4 dBV
Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBm
Differential drive, p-p 20 dBm
Noise Floor Terminated 50 Ω source 1.28 nV/√Hz
Equivalent Power in 50 Ω 440 MHz bandwidth
Input Resistance From INHI to INLO 800 1000 1200 Ω
Input Capacitance From INHI to INLO 1.4 pF
DC Bias Voltage Either input 3.2 V
LOGARITHMIC AMPLIFIER Output VOUT
±3 dB Error Dynamic Range From noise floor to maximum input 95 dB
Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dB
Overtemperature, –40°C < TA < +85°C 20 26 mV/dB
Intercept (Log Offset)
Equivalent dBm (re 50 Ω) −102 −95 −86 dBm
Overtemperature, −40°C ≤ TA ≤ +85°C −120 −96 dBV
Equivalent dBm (re 50 Ω) −107 −83 dBm
Temperature sensitivity −0.04 dB/°C
Linearity Error (Ripple) Input from –88 dBV (–75 dBm) to +2 dBV (+15 dBm) ±0.4 dB
Output Voltage Input = –91 dBV (–78 dBm) 0.4 V
Input = 9 dBV (22 dBm) 2.6 V
Minimum Load Resistance, RL 100 Ω
Maximum Sink Current 0.5 mA
Output Resistance 0.05 Ω
Video Bandwidth 25 MHz
Rise Time (10% to 90%) Input Level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 15 ns
Input Level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 20 ns
Fall Time (90% to 10%) Input Level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 30 ns
Input Level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns
Output Settling Time to 1% Input Level = −13 dBV (0 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns
POWER INTERFACES
Supply Voltage, VPOS 2.7 5.5 V
Quiescent Current Zero-signal 6.5 8.0 9.5 mA
Overtemperature −40°C < TA < +85°C 5.5 8.5 10 mA
Disable Current 0.05 μA
Logic Level to Enable Power High condition, −40°C < TA < +85°C 2.3 V
Input Current when High 3 V at ENBL 35 μA
Logic Level to Disable Power Low condition, −40°C < TA < +85°C 0.8 V
1
The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed
offset of 13 dBm in the special case of a 50 Ω termination.
2
Guaranteed but not tested; limits are specified at six sigma levels.
2
10 MHz ≤ f ≤ 200 MHz
−115
−78
−108 −99 dBV
dBm
Rev. E | Page 3 of 24
AD8310
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Value
Supply Voltage, VS 7.5 V
Input Power (re 50 Ω), Single-Ended 18 dBm
Differential Drive 22 dBm
Internal Power Dissipation 200 mW
θ
JA
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
200°C/W
Stresses above those listed under Absolute Maximum Ratings
y cause permanent damage to the device. This is a stress
ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. E | Page 4 of 24
AD8310
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INLO
1
COMM
OFLT
VOUT
AD8310
2
TOP VIEW
3
(Not to Scale)
4
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2.
2 COMM Common Pin. Usually grounded.
3 OFLT Offset Filter Access. Nominally at about 1.75 V.
4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load.
5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current.
6 BFIN Buffer Input. Used to lower post-detection bandwidth.
7 ENBL CMOS Compatible Chip Enable. Active when high.
8 INHI Second of Two Balanced Inputs.
8
7
6
5
INHI
ENBL
BFIN
VPOS
01084-002
Rev. E | Page 5 of 24
AD8310
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TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
T
= –40°C
RSSI OUTPUT (V)
1.0
0.5
A
T
= +25°C
A
0
–120 20–100
(–87dBm)
= +85°C
T
A
–80 –60 –40 –20 0
INPUT LEVEL (dBV)
(+13dBm)
Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at T
+25°C, and +85°C, Single-Ended Input
3.0
2.5
2.0
1.5
RSSI OUTPUT (V)
1.0
0.5
0
–120 –100
(–87dBm)
–80 –60 –40 –20 0
INPUT LEVEL (dBV)
Figure 4. RSSI Output vs. Input Level at T
10MHz
= 25°C
A
100MHz
(+13dBm)
for Frequencies of 10 MHz, 50 MHz, and 100 MHz
= −40°C,
A
50MHz
20
01084-011
01084-012
3.0
2.5
PIN (dBm)
–40°C
85°C
25°C
2.0
1.5
–40°C
RSSI OUTPUT (V)
1.0
0.5
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20
25°C
85°C
Figure 6. Log Linearity of RSSI Output vs. Input Level,
10
0 MHz Sine Input at T
= −40°C, +25°C, and +85°C
A
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–120 20–100
(–87dBm)
–80 –60 –40 –20 0
INPUT LEVEL (dBV)
50MHz
100MHz
(+13dBm)
Figure 7. Log Linearity of RSSI Output vs. Input Level,
= 25°C, for Frequencies of 10 MHz, 50 MHz, and 100 MHz
at
T
A
10MHz
3
2
1
0
–1
–2
–3
01084-015
ERROR (dB)
01084-043
3.0
2.5
2.0
1.5
RSSI OUTPUT (V)
1.0
0.5
0
–120 20–100
(–87dBm)
–80 –60 –40 –20 0
INPUT LEVEL (dBV)
Figure 5. RSSI Output vs. Input Level at T
for Frequencies of 200 MHz, 300 MHz, and 440 MHz
300MHz
440MHz
(+13dBm)
= 25°C
A
200MHz
01084-013
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–120 20–100
(–87dBm)
–80 –60 –40 –20 0
INPUT LEVEL (dBV)
Figure 8. Log Linearity of RSSI Output vs. Input Level at T
for Frequencies of 200 MHz, 300 MHz, and 440 MHz
Rev. E | Page 6 of 24
300MHz
440MHz
200MHz
(+13dBm)
= 25°C
A
01084-016
AD8310
www.BDTIC.com/ADI
100pF
3300pF
50μs PER
HORIZONTAL
DIVISION
V
OUT
0.01μF
GROUND REFERENCE
Figure 9. Small-Signal AC Response of RSSI Output with External BFIN
C
apacitance of 100 pF, 3300 pF, and 0.01 μF
500mV PER
VERTICAL
DIVISION
01084-009
500mV PER
VERTICAL
DIVISION
10mV PER
VERTICAL
DIVISION
INPUT
GROUND REFERENCE
V
OUT
25ns PER
HORIZONTAL
DIVISION
01084-010
Figure 12. Small-Signal RSSI Pulse Response
= 402 Ω and CL = 68 pF
with R
L
V
OUT
100Ω
500mV PER
VERTICAL
DIVISION
GND REFERENCE
INPUT
500mV PER
VERTICAL
DIVISION
154Ω
Figure 10. Large-Signal RSSI Pulse Response with C
= 100 Ω, 154 Ω, and 200 Ω
and R
L
200Ω
100ns PER
HORIZONTAL
DIVISION
L
= 100 pF
01084-005
V
OUT
500mV PER
VERTICAL
DIVISION
GND REFERENCE
INPUT
–3dBV INPUT
LEVEL SHOWN
HERE
Figure 11. RSSI Pulse Response with R
100ns PER
HORIZONTAL
DIVISION
500mV PER
VERTICAL
DIVISION
= 402 Ω and CL = 68 pF,
L
01084-006
for Inputs Stepped from 0 dBV to −33 dBV, −23 dBV, −13 dBV, and −3 dBV
V
OUT
500mV PER
VERTICAL
DIVISION
GND REFERENCE
INPUT
500mV PER
VERTICAL
DIVISION
CURVES
OVERLAP
100ns PER
HORIZONTAL
DIVISION
Figure 13. Large-Signal RSSI Pulse Response with R
= 33 pF, 68 pF, and 100 pF
and C
L
V
OUT
200mV PER
VERTICAL
DIVISION
GND REFERENCE
INPUT
100ns PER
HORIZONTAL
DIVISION
20mV PER
VERTICAL
DIVISION
Figure 14. Small-Signal RSSI Pulse Response with R
and Back Termination of 50 Ω (Total Load = 100 Ω)
= 100 Ω
L
= 50 Ω
L
01084-007
01084-008
Rev. E | Page 7 of 24
AD8310
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100
10
1
0.1
0.01
0.001
SUPPLY CURRENT (mA)
T
= +85°C
A
T
= +25°C
A
V
OUT
500mV PER
VERTICAL
DIVISION
–3dBV
–23dBV
–43dBV
–63dBV
–83dBV
0.0001
0.00001
0.5 2.50.7
T
= –40°C
A
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3
ENABLE VOLTAGE (V)
Figure 15. Supply Current vs. Enable Voltage at T
30
29
28
27
26
25
24
RSSI SLOPE (mV/dB)
23
22
21
20
1 100010
FREQUENCY (MHz)
Figure 16. RSSI S lope vs. Frequency
= −40°C, +25°C, and +85°C
A
100
01084-003
01084-017
5V PER
VERTICAL
DIVISION
200ns PER HORIZONTAL DIVISION
ENABLE
Figure 18. Power-On/Off Response Time wi
–99
–101
–103
–105
–107
–109
–111
–113
RSSI INTERCEPT (dBV)
–115
–117
–119
1 100010
FREQUENCY (MHz)
Figure 19. RSSI Intercept vs. Frequency
01084-004
th RF Input of −83 dBV to −3 dBV
100
01084-018
40
35
30
25
20
COUNT
15
10
5
0
21.5 22.0
NORMAL
(23.6584,
0.308728)
22.5 23.0 23.5 24.0 24.5
SLOPE (mV/dB)
Figure 17. Transfer Slope Distribution, V
01084-019
= 5 V, Frequency = 100 MHz, 25°C
S
24
22
20
18
16
14
12
COUNT
10
8
6
4
2
0
–115 –113
–111 –109 –107 –105 –103 –101 –99 –97
INTERCEPT (dBV)
Figure 20. Intercept Distribution V
Rev. E | Page 8 of 24
NORMAL
(–107.6338,
2.36064)
= 5 V, Frequency = 100 MHz, 25°C
S
01084-020
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