Analog Devices AD8304 a Datasheet

160 dB Range (100 pA –10 mA)

a

FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Eight Full Decades of Range

Law Conformance 0.1 dB from 1 nA to 1 mA
Single-Supply Operation (3.0 V– 5.5 V)
Complete and Temperature Stable
Accurate Laser-Trimmed Scaling:

Logarithmic Slope of 10 mV/dB (at VLOG Pin)

Basic Logarithmic Intercept at 100 pA

Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/s Slew Rate
1-, 2-, or 3-Pole Low-Pass Filtering at Output
Miniature 14-Lead Package (TSSOP)
Low Power: ~4.5 mA Quiescent Current (Enabled)

APPLICATIONS
High Accuracy Optical Power Measurement
Wide Range Baseband Log Compression
Versatile Detector for APC Loops

VSUM

Logarithmic Converter

AD8304

FUNCTIONAL BLOCK DIAGRAM

VPS2 PWDN VPS1

10

VPDB

6

VSUM

3

I

PD

INPT

4

5

PDB BIAS VREF

1

VNEG

~10k

2 12

TEMPERATURE

COMPENSATION

14

ACOM

0.5V

5k

AD8304

11

VOUT

13

7

8

9

VREF

VLOG

BFIN

BFNG

PRODUCT DESCRIPTION

The AD8304 is a monolithic logarithmic detector optimized for
the measurement of low frequency signal power in fiber optic
systems. It uses an advanced translinear technique to provide an
exceptionally large dynamic range in a versatile and easily used
form. Its wide measurement range and accuracy are achieved
using proprietary design techniques and precise laser trimming.
In most applications only a single positive supply, V

, of 5 V

P

will be required, but 3.0 V to 5.5 V can be used, and certain
applications benefit from the added use of a negative supply,

. When using low supply voltages, the log slope is readily

V

N

altered to fit the available span. The low quiescent current and
chip disable features facilitate use in battery-operated applications.

The input current, I

, flows in the collector of an optimally

PD

scaled NPN transistor, connected in a feedback path around a
low offset JFET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5 V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply.
An adaptive biasing scheme is provided for reducing the dark
current at very low light input levels. The voltage at Pin VPDB
applies approximately 0.1 V across the diode for I
rising linearly with current to 2.0 V of net bias at I

= 100 pA,

PD

= 10 mA.

PD

The input pin INPT is flanked by the guard pins VSUM that
track the voltage at the summing node to minimize leakage.

The default value of the logarithmic slope at the output VLOG is
accurately scaled to 10 mV/dB (200 mV/decade). The resistance
at this output is laser-trimmed to 5 kΩ, allowing the slope to be
lowered by shunting it with an external resistance; the addition
of a capacitor at this pin provides a simple low-pass filter. The
intermediate voltage VLOG is buffered in an output stage that can
swing to within about 100 mV of ground (or V
tive supply, V

, and provides a peak current drive capacity of

P

) and the posi-

N

±20 mA. The slope can be increased using the buffer and a pair
of external feedback resistors. An accurate voltage reference of
2V is also provided to facilitate the repositioning of the intercept.

Many operational modes are possible. For example, low-pass filters
of up to three poles may be implemented, to reduce the output
noise at low input currents. The buffer may also serve as a com­parator, with or without hysteresis, using the 2 V reference, for
example, in alarm applications. The incremental bandwidth of
a translinear logarithmic amplifier inherently diminishes for small
input currents. At the 1 nA level, the AD8304’s bandwidth is
about 2 kHz, but this increases in proportion to I

up to a

PD

maximum value of 10 MHz.

The AD8304 is available in a 14-lead TSSOP package and specified
for operation from –40°C to +85°C.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD8304–SPECIFICATIONS

(VP = 5 V, VN = 0 V, TA = 25C, unless otherwise noted.)

Parameter Conditions Min1Typ Max1Unit

INPUT INTERFACE Pin 4, INPT; Pin 3 and Pin 5, VSUM

Specified Current Range Flows toward INPT Pin 100 pA

10 mA

Input Node Voltage Internally preset; may be altered 0.46 0.5 0.54 V
Temperature Drift –40°C < T
Input Guard Offset Voltage V

PHOTODIODE BIAS

2

Minimum Value I

– V

IN

Established between Pin 6, V

= 100 pA 70 100 mV

PD

< +85°C 0.02 mV/°C

SUM

A

, and Pin 4

PDB

–20 +20 mV

Transresistance 200 mV/mA

LOGARITHMIC OUTPUT Pin 8, VLOG

Slope Laser-trimmed at 25°C 196 200 204 mV/dec

0°C < T

< 70°C 194 207 mV/dec

A

Intercept Laser-trimmed at 25°C60100 140 pA

0°C < T

Law Conformance Error 10 nA < I

1 nA < I

< 70°C35175 pA

A

< 1 mA, Peak Error 0.05 0.25 dB

PD

< 1 mA, Peak Error 0.1 0.7 dB

PD

Maximum Output Voltage 1.6 V
Minimum Output Voltage Limited by V

= 0 V 0.1 V

N

Output Resistance Laser-trimmed at 25°C 4.95 5 5.05 kΩ

REFERENCE OUTPUT Pin 7, VREF

Voltage WRT Ground Laser-trimmed at 25°C 1.98 2 2.02 V

–40°C < T

< +85°C 1.92 2.08 V

A

Output Resistance 2 Ω

OUTPUT BUFFER Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT

Input Offset Voltage –20 +20 mV
Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 µA
Incremental Input Resistance 35 MΩ
Output Range R
Output Resistance 0.5 Ω
Wide-Band Noise
Small Signal Bandwidth

3

3

= 1 kΩ to ground VP – 0.1 V

L

IPD > 1 µA (see Typical Performance Characteristics) 1 µV/√Hz
IPD > 1 µA (see Typical Performance Characteristics) 10 MHz

Slew Rate 0.2 V to 4.8 V output swing 15 V/µs

POWER-DOWN INPUT Pin 2, PWDN

Logic Level, HI State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 2 V
Logic Level, LO State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 1 V

POWER SUPPLY Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG

Positive Supply Voltage 3.0 5 5.5 V
Quiescent Current 4.5 5.3 mA
In Disabled State 60 µA
Negative Supply Voltage

NOTES

1

Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.

2

This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.

3

Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics.

4

Optional

Specifications subject to change without notice.

4

|1VP–VN| < 8V 0 –5.5 V

REV. A–2–

AD8304

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 270 mW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

␪

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

ACOM

VNEG

PWDN

VSUM

INPT

VSUM

VPDB

VREF

1

2

3

AD8304

TOP VIEW

4

(Not to Scale)

5

6

7

14

13

12

11

10

9

8

BFNG

VPS1

VOUT

VPS2

BFIN

VLOG

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 VNEG Optional Negative Supply, V

. This

N

pin is usually grounded; for details of
usage, see Applications section.

2PWDN Power-Down Control Input. Device is

active when PWDN is taken LOW.

3, 5 VSUM Guard Pins. Used to shield the INPT

current line.

4INPT Photodiode Current Input. Usually

connected to photodiode anode (the
photo current flows toward INPT).

6 VPDB Photodiode Biaser Output. May be

connected to photodiode cathode to

provide adaptive bias control.
7 VREF Voltage Reference Output of 2 V
8 VLOG Output of the Logarithmic Front-End

Processor; R

= 5 kΩ to ground.

OUT

9 BFIN Buffer Amplifier Noninverting Input

(High Impedance)
10 VPS2 Positive Supply, V

(3.0 V to 5.5 V)

P

11 VOUT Buffer Output; Low Impedance
12 VPS1 Positive Supply, V

(3.0 V to 5.5 V)

P

13 BFNG Buffer Amplifier Inverting Input
14 ACOM Analog Ground

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8304ARU –40°C to +85°CTube, 14-Lead TSSOP RU-14
AD8304ARU-REEL 13" Tape and Reel
AD8304ARU-REEL7 7" Tape and Reel
AD8304-EVAL Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A

–3–

AD8304–Typical Performance Characteristics

INPUT – A

2.4

0.6
100p 10m1n

V

OUT

– V

10n 100n 1 10 100 1m

2.2

1.6

1.4

1.2

1.0

2.0

1.8

+85C

+25C

–40C

0.8

1.25

–1.00

ERROR – dB (10mV/dB)

1.00

0.25

0

–0.25

–0.50

0.75

0.50

–0.75

TA = –40C, +25C, +85C
V

P

= 3.0V

(VP = 5 V, VN = 0 V, TA = 25C, unless otherwise noted.)

1.6
= –40C, +25C, +85C

T

A

V

= –0.5V

N

1.4

1.2

+85C

–40C
+25C
+85C

INPUT – A

LOG

+25C

INPUT – A

vs. I

1.0

– V

0.8

LOG

V

0.6

0.4

0.2

0
100p 10m1n 10n 100n 1 10 100 1m

TPC 1. V

2.0

TA = –40C, +25C, +85C

= –0.5V

V

N

1.5

0C

0

+70C

100p 10m1n

–40C

10n 100n 1 10 100 1m

1.0

0.5

–0.5

ERROR – dB (10mV/dB)

–1.0

–1.5

–2.0

PD

0C

+70C

TPC 2. Logarithmic Conformance (Linearity) for V

LOG

0.510
TA = –40C, +25C, +85C

0.508

0.506

– V

SUM

V

0.504

0.502

0.500

100p 10m1n 10n 100n 1 10 100 1m

TPC 4. V

2.8
TA = –40C, +25C, +85C

2.6

2.4

2.2

2.0

1.8

– V

PDB

1.6

V

1.4

1.2

1.0

0.8

0.6

0101

23456 789

TPC 5. V

INPUT – A

vs. I

SUM

INPUT – mA

vs. I

PDB

–40C
+25C
+85C

PD

PD

–40C

+25C

+85C

2.0
VP = 4.5V, 5.0V, 5.5V

= –0.1V

V

N

1.5

1.0

0.5

4.5V

5.0V

0

5.5V

–0.5

–1.0

–1.5

ERROR FROM IDEAL OUTPUT – dB (10mV/dB)

–2.0

100p 10m1n 10n 100n 1 10 100 1m

INPUT – A

TPC 3. Absolute Deviation from Nominal Speci­fied Value of V

for Several Supply Voltages

LOG

TPC 6. Logarithmic Conformance (Linearity) for a
3 V

Single Supply (See Figure 6)

REV. A–4–

AD8304

10

0

–10

–20

–30

–40

–50

NORMALIZED RESPONSE – dB

–60

–70

100 100M1k

100nA

10nA

1nA

10k 100k 1M 10M

FREQUENCY – Hz

1A

10A

10mA

100A

TPC 7. Small Signal AC Response, IPD to V
(5% Sine Modulation of IPD at Frequency)

100

10kHz

10

Hz

1

V rms/



0.1

1MHz

100kHz

100Hz

1kHz

1mA

LOG

10

9

8

7

6

5

4

3

WIDEBAND NOISE – mV rms

2

1

0

INPUT CURRENT – A

TPC 10. Total Wideband Noise Voltage at V

3

GAIN = 1, 2, 2.5, 5 

0

AV = 5

–3

AV = 2.5

–6

NORMALIZED RESPONSE – dB

–9

A

= 2

V

LOG

AV = 1

10m100n 101n 10n 1 100 1m

vs. I

PD

0.01

IPD – A

TPC 8. Spot Noise Spectral Density at V

100

1nA

10

10nA

Hz

100nA

1

V rms/



0.1

0.01
100 10M1k

1A

10A

>100A

10k 100k 1M

FREQUENCY – Hz

TPC 9. Spot Noise Spectral Density at V

10m100n 101n 10n 1 100 1m

vs. I

LOG

vs. Frequency

LOG

PD

–12

100 100M1k

10k 100k 1M 10M

FREQUENCY – Hz

TPC 11. Small Signal Response of Buffer

10

f

= 1kHz

C

0

–10

–20

–30

–40

NORMALIZED GAIN – dB

–50

–60

–70

10 100k100

1k 10k

FREQUENCY – Hz

TPC 12. Small Signal Response of Buffer
Operating as Two-Pole Filter

REV. A

–5–

AD8304

2.0
TA = 25C

1.5

1.0

0.5

0

–0.5

ERROR – dB (10mV/dB)

–1.0

–1.5

–2.0

100p 10m1n

MEAN + 3

MEAN – 3

10n 100n 1 10 100 1m

INPUT – A

TPC 13. Logarithmic Conformance Error

σ

Distribution (3

5

TA = 0C, 70C

4

3

2

1

0

–1

–2

ERROR – dB (10mV/dB)

–3

–4

–5

100p 10m1n

to Either Side of Mean)

MEAN + 3 @ 70C

MEAN  3 @ 0C

MEAN – 3 @ 70C

10n 100n 1 10 100 1m

INPUT – A

TPC 14. Logarithmic Conformance Error
Distribution (3

σ

to Either Side of Mean)

20

15

10

5

0

–5

DRIFT – mV

–10

REF

V

–15

–20

–25

–30

–40 90–30

TPC 16. V

MEAN + 3

MEAN – 3

–20 –10 0 10 20 40 60 80

REF

TEMPERATURE – C

Drift vs. Temperature (3σ to Either

30 50 70

Side of Mean)

3

2

1

0

–1

–2

–3

SLOPE CHANGE FROM 25C – mV/dec

–4

–5

–40 90–30

MEAN + 3

MEAN – 3

–20

–10 0 10 20 40

TEMPERATURE – C

30 50

60 80

70

TPC 17. Slope Drift vs. Temperature (3σ to Either
Side of Mean)

5

4

3

2

1

0

–1

–2

ERROR – dB (10mV/dB)

–3

–4

–5

100p 10m1n

MEAN 3 @ 85C

10n 100n 1 10 100 1m

INPUT – A

TA = 40C, 85C

MEAN 3 @40C

MEAN 3 @40C

TPC 15. Logarithmic Conformance Error

σ

Distribution (3

to Either Side of Mean)

40

30

20

10

0

–10

–20

–30

INTERCEPT CHANGE FROM 25C – pA

–40

–50

–40 90–30

MEAN + 3

MEAN – 3

–20 –10 0 10 20 40 60 80

TEMPERATURE – C

30 50 70

TPC 18. Intercept Drift vs. Temperature (3σ to
Either Side of Mean)

REV. A–6–