Analog Devices AD7992 Datasheet
2-Channel, 12-Bit ADC with I2C-Compatible
A
T
FEATURES
12-bit ADC with fast conversion time: 2 µs typ
2 single-ended analog input channels
Specified for V
Low power consumption
Fast throughput rate: up to 188 kSPS
Sequencer operation
Temperature range: −40 °C to 125 °C
Automatic cycle mode
2
C®-compatible serial interface supports standard, fast,
I
and high speed modes
Out-of-range indicator/alert function
Pin-selectable addressing via AS
2 versions allow 5 I
Shutdown mode: 1 µA max
10-lead MSOP package
GENERAL DESCRIPTION
The AD7992 is a 12-bit, low power, successive approximation
ADC with an I
a single 2.7 V to 5.5 V power supply and features a 2 µs conversion time. The part contains a 2-channel multiplexer and trackand-hold amplifier that can handle input frequencies up to
11 MHz.
The AD7992 provides a 2-wire serial interface compatible with
2
C interfaces. The part comes in two versions, the AD7992-0
I
and the AD7992-1, and each version allows for at least two
different I
2
C interface modes, and the AD7992-1 supports standard,
fast I
fast, and high speed I
The AD7992 normally remains in a shutdown state while not
converting, and powers up only for conversions. The conversion
process can be controlled using the
command mode where conversions occur across I
operations, or an automatic conversion interval mode selected
through software control.
The AD7992 requires an external reference in the range of 1.2 V
. This allows the widest dynamic input range to the ADC.
to V
DD
On-chip limit registers can be programmed with high and low
limits for the conversion result, and an open-drain, out-ofrange indicator output (ALERT) becomes active when the
conversion result violates the programmed high or low limits.
This output can be used as an interrupt.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
of 2.7 V to 5.5 V
DD
2
C addresses
2
C-compatible interface. The part operates from
2
C addresses. The AD7992-0 supports standard and
2
C interface modes.
CONVST
pin, by a
2
C write
Interface in 10-Lead MSOP
AD7992
FUNCTIONAL BLOCK DIAGRAM
GND CONVST
AD7992
VIN1
2/REF
V
IN
IN
V
DD
AS
VIN2/REFIN
SOFTWARE
CONTROL
HYSTERESIS
REGISTER CH0
HYSTERESIS
REGISTER CH1
MUX
GND
I/P
T/H
PRODUCT HIGHLIGHTS
1. 2 µs conversion time and low power consumption.
2
2. I
C-compatible serial interface with pin-selectable
addresses. Two AD7992 versions allow five AD7992
devices to be connected to the same serial bus.
3. The part features automatic shutdown while not converting
to maximize power efficiency. Current consumption is
1 µA max when in shutdown mode at 3 V.
4. Reference can be driven up to the power supply.
5. Out-of-range indicator that can be software disabled or
enabled.
6. One-shot and automatic conversion rates.
7. Registers store minimum and maximum conversion
results.
Table 1. Related Products
Part Number No. of Bits No. of Channels Package
AD7998 12 8 20-TSSOP
AD7994 12 4 16-TSSOP
AD7997 10 8 20-TSSOP
AD7993 10 4 16-TSSOP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
12-BIT SUCCESSIVE
APPROXIMATION
DATA
LIMIT
HIGH
REGISTER CH1
DATA
LIMIT
LOW
REGISTER CH1
DATA
LIMIT
HIGH
REGISTER CH2
DATA
LIMIT
LOW
REGISTER CH2
Figure 1.
ADC
I2C INTERFACE
CONTROL
LOGIC
CONVERSION
RESULT
REGISTER
CONFIGURATION
REGISTER
ALERT STATUS
REGISTER
CYCLE TIMER
REGISTER
SCL
SDA
LER
03263-0-001
AD7992
TABLE OF CONTENTS
Specifications..................................................................................... 3
2
I
C Timing Specifications................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Pin Function Descriptions...................... 8
Te r mi n ol o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Circuit Information........................................................................ 13
Converter Operation.................................................................. 13
Typical C o n n e ction Di a g r am ................................................... 14
Analog Input ............................................................................... 14
Internal Register Structure ............................................................16
Address Pointer Register ........................................................... 16
Configuration Register .............................................................. 17
Conversion Result Register....................................................... 18
Serial Interface................................................................................ 20
Serial Bus Address...................................................................... 20
Writing to the AD7992 .................................................................. 21
Writing to the Address Pointer Register for a Subsequent
.............................................................................................. 21
Read
Writing a Single Byte of Data to the Alert Status Register,
Cycle Register, or Configuration Register
Writing Two Bytes of Data to a Limit Register or Hysteresis
Register
Reading Data from the AD7992................................................... 23
ALERT/BUSY Pin .......................................................................... 24
SMBus ALERT............................................................................ 24
Placing the AD7992-1 into High Speed Mode....................... 24
The Address Select (AS) Pin..................................................... 24
Modes of Operation ....................................................................... 25
Mode 1—Using the
........................................................................................ 22
CONVST
Pin ........................................... 25
............................... 21
Limit Registers ............................................................................ 18
Alert Status Register................................................................... 19
Cycle Timer Register.................................................................. 19
Sample Delay and Bit Trial Delay............................................. 19
REVISION HISTORY
1/05—Revision 0: Initial Version
Mode 2 – Command mode....................................................... 26
Mode 3—Automatic Cycle Mode............................................. 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28
AD7992
SPECIFICATIONS
Temperature range for B version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V to VDD. For the
AD7992-0, all specifications apply for f
up to 400 kHz; for the AD7992-1 all specifications apply for f
SCL
specifications are for both single-channel mode and dual-channel mode, Unless otherwise noted; T
Table 2.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
1
= 10 kHz sine wave for f
F
IN
3.4 MHz
= 1 kHz sine wave for f
F
IN
Signal-to-Noise + Distortion (SINAD)
2
70.5 dB min
Signal-to-Noise Ratio (SNR)2 71 dB min
Total Harmonic Distortion (THD)2 –78 dB max
Peak Harmonic or Spurious Noise (SFDR)2 –79 dB max
Intermodulation Distortion (IMD)2
fa = 10.1 kHz, fb = 9.9 kHz for f
to 3.4 MHz
fa = 1.1 kHz, fb = 0.9 kHz for f
Second-Order Terms –90 dB typ
Third-Order Terms –90 dB typ
Aperture Delay2 10 ns max
Aperture Jitter2 50 ps typ
Channel-to-Channel Isolation2
Full Power Bandwidth
2
−90
11 MHz typ @ 3 dB
dB typ FIN = 108 Hz; see the Terminology section
2 MHz typ @ 0.1 dB
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity
1, 2
±1 LSB max
±0.2 LSB typ
Differential Nonlinearity
1, 2
+1/–0.9 LSB max Guaranteed no missed codes to 12 bits
±0.2 LSB typ
Offset Error2 ±4 LSB max
Mode 1 (
±6 LSB max Mode 2 (command mode)
Offset Error Match2 ±1 LSB max Dual-channel mode
Gain Error2 ±2 LSB max
Gain Error Match2 ±1 LSB max Dual-channel mode
ANALOG INPUT
Input Voltage Range 0 to REF
V
IN
DC Leakage Current ±1 µA max
Input Capacitance 30 pF typ
REFERENCE INPUT
REFIN Input Voltage Range 1.2 to V
DD
V min/V max
DC Leakage Current ±1 µA max
Input Impedance 69 kΩ typ
LOGIC INPUTS (SDA, SCL)
Input High Voltage, V
Input Low Voltage, V
0.7 (VDD) V min
INH
0.3 (VDD) V max
INL
Input Leakage Current, IIN ±1 µA max VIN = 0 V or V
Input Capacitance, C
Input Hysteresis, V
3
IN
0.1 (VDD) V min
HYST
10 pF max
up to 3.4 MHz. All
SCL
= T
MIN
to T
MAX
A
CONVST mode)
DD
.
from 1.7 MHz to
SCL
up to 400 kHz
SCL
from 1.7 MHz
SCL
up to 400 kHz
SCL
Rev. 0 | Page 3 of 28
AD7992
Parameter B Version Unit Test Conditions/Comments
LOGIC INPUTS (CONVST)
Input High Voltage, V
2.4 V min VDD = 5 V
INH
2.0 V min VDD = 3 V
Input Low Voltage, V
0.8 V max VDD = 5 V
INL
0.4 V max VDD = 3 V
Input Leakage Current, IIN ±1 µA max VIN = 0 V or V
Input Capacitance, C
3
10 pF max
IN
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL 0.4 V max I
0.6 V max I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance3 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE See the Serial Interface section
Conversion Time 2 µs typ
Throughput Rate
Mode 1 (Reading after the Conversion) 5 kSPS typ f
21 kSPS typ f
121 kSPS typ f
Mode 2 5.5 kSPS typ f
22 kSPS typ f
147 kSPS typ f
POWER REQUIREMENTS
V
DD
I
DD
Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V
Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f
0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f
Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f
0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f
Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f
0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f
0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f
Mode 3 (I2C Inactive, T
× 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V
CONVERT
POWER DISSIPATION
Fully Operational
Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f
1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f
2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f
Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V
1
Maximum/minimum ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL
frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2
See the Terminology section.
3
Guaranteed by initial characterization.
DD
= 3 mA
SINK
= 6 mA
SINK
= 100 kHz
SCL
= 400 kHz
SCL
= 3.4 MHz
SCL
= 100 kHz
SCL
= 400 kHz
SCL
= 3.4 MHz , 188 kSPS typ @ 5 V
SCL
2.7/5.5 V min/max
Digital inputs = 0 V or V
DD
SCL
SCL
SCL
SCL
SCL
Mode1
SCL
Mode 2
SCL
SCL
Mode 1
SCL
Mode 2
SCL
Rev. 0 | Page 4 of 28
AD7992
I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values measured with the input filtering enabled. CB refers to the capacitive load on the bus
and tf measured between 0.3 VDD and 0.7 VDD.
line. t
r
High speed mode timing specifications apply to the AD7992-1 only. Standard and fast mode timing specifications apply to both the
AD7992-0 and the AD7992-1. See Figure 2. Unless otherwise noted, V
= 2.7 V to 5.5 V; REFIN = 2.5 V to VDD; TA =T
DD
Table 3.
Limit at T
MIN
, T
MAX
Parameter Conditions Min Max Unit Description
f
Standard mode 100 kHz Serial clock frequency
SCL
Fast mode 400 kHz
High speed mode
C
C
t1 Standard mode 4 µs t
= 100 pF max 3.4 MHz
B
= 400 pF max 1.7 MHz
B
, SCL high time
HIGH
Fast mode 0.6 µs
High speed mode
C
C
t2 Standard mode 4.7 µs t
= 100 pF max 60 ns
B
= 400 pF max 120 ns
B
, SCL low time
LOW
Fast mode 1.3 µs
High speed mode
C
C
t3 Standard mode 250 ns t
= 100 pF max 160 ns
B
= 400 pF max 320 ns
B
, data setup time
SU;DAT
Fast mode 100 ns
High speed mode 10 ns
1
t
4
Standard mode 0 3.45 µs t
, data hold time
HD;DAT
Fast mode 0 0.9 µs
High Speed mode
C
C
t5 Standard mode 4.7 µs t
= 100 pF max 0 702 ns
B
= 400 pF max 0 150 ns
B
, setup time for a repeated START condition
SU;STA
Fast mode 0.6 µs
High Speed mode 160 ns
t6 Standard mode 4 µs t
, hold time for a repeated START condition
HD;STA
Fast mode 0.6 µs
High speed mode 160 ns
t7 Standard mode 4.7 µs t
, bus free time between a STOP and a START condition
BUF
Fast mode 1.3 µs
t8 Standard mode 4 µs t
, setup time for STOP condition
SU;STO
Fast mode 0.6 µs
High speed mode 160 ns
t9 Standard mode 1000 ns t
, rise time of SDA signal
RDA
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
C
= 100 pF max 10 80 ns
B
= 400 pF max 20 160 ns
B
MIN
to T
MAX
.
Rev. 0 | Page 5 of 28
AD7992
Limit at T
Parameter Conditions Min Max Unit Description
t10 Standard mode 300 ns t
Fast mode 20 + 0.1 C
B
High speed mode
C
C
= 100 pF max 10 80 ns
B
= 400 pF max 20 160 ns
B
t11 Standard mode 1000 ns t
Fast mode 20 + 0.1 C
B
High speed mode
C
C
t
Standard mode 1000 ns
11A
Fast mode 20 + 0.1 C
= 100 pF max 10 40 ns
B
= 400 pF max 20 80 ns
B
B
High speed mode
C
C
= 100 pF max 10 80 ns
B
= 400 pF max 20 160 ns
B
t12 Standard mode 300 ns t
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
C
t
SP
= 100 pF max 10 40 ns
B
= 400 pF max 20 80 ns
B
Fast mode 0 50 ns Pulse width of suppressed spike
High speed mode 0 10 ns
t
POWER-UP
1 µs typ Power-up time
1
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
2
For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.
, T
MIN
MAX
300 ns
300 ns
300 ns
, fall time of SDA signal
FDA
, rise time of SCL signal
RCL
, rise time of SCL signal after a repeated START
t
RCL1
condition and after an acknowledge bit
, fall time of SCL signal
FCL
SCL
SDA
t
7
P
S = START CONDITION
P = STOP CONDITION
t
11
t
2
t
6
S
t
4
t
12
t
3
t
1
S
t
6
t
5
t
10
t
8
t
9
P
03623-0-019
Figure 2. Two-Wire Serial Interface Timing Diagram
Rev. 0 | Page 6 of 28
AD7992
ABSOLUTE MAXIMUM RATINGS
= 25°C, unless otherwise noted.
T
A
Table 4.
Parameter Rating
VDD to GND
Analog Input Voltage to GND
Reference Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1±10 mA
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature 150°C
10-Lead MSOP Package
θJA Thermal Impedance 200°C/W (MSOP)
θJC Thermal Impedance 44°C/W (MSOP)
Pb/SN Temperature,
Soldering Reflow (10 sec to 30 sec)
Pb-Free Temperature, Soldering Reflow 260 (+0)°C
ESD 1.5 kV
−0.3 V to 7 V
−0.3 V to V
−0.3 V to V
−0.3 V to +7 V
−0.3 V to V
−40°C to +125°C
−65°C to +150°
240 (+0/−5)°C
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7992
V
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
CONVST
AGND
2/REF
IN
V
V
IN
DD
IN
1
1
2
3
AD7992
4
TOP VIEW
(Not to Scale)
5
10
9
8
7
6
SCL
SDA
ALERT
AGND
AS
03263-0-002
Figure 3. AD7992 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Function
2, 7 AGND
Analog Ground. Ground reference point for all circuitry on the AD7992. All analog input signals should be
referred to this GND voltage.
3 VDD Power Supply Input. The VDD range for the AD7992 is from 2.7 V to 5.5 V.
4 VIN2/REF
Analog Input 2/Voltage Reference Input. In single-channel mode, this pin becomes the reference voltage input;
IN
an external reference should be applied at this pin. The external reference input range is 1.2 V to V
. A 0.1 µF
DD
and 1µF capacitor should be tied between this pin and AGND. If Bit D6 is set to 1 in the configuration register,
the AD7992 operates in single-channel mode. In dual-channel mode, D6 in the configuration register is 0; in
this case, this pin provides the second analog input channel. The reference voltage for the AD7992 is taken
from the power supply voltage in dual-channel mode. See the Configuration Register section and Table 10.
5 VIN1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN.
6 AS Logic Input. Address select input that selects one of three I2C addresses for the AD7992, as shown in Table 6.
1
CONVST Logic Input Signal. Convert start signal. This is an edge-triggered logic input. The rising edge of this signal
powers up the part. The power up time for the part is 1 µs. The falling edge of
CONVST places the track-andhold into hold mode and initiates a conversion. A power-up time of at least 1 µs must be allowed for the
CONVST high pulse; otherwise, the conversion result is invalid (see the Modes of Operation section).
8 ALERT/BUSY
Digital Output. Selectable as an ALERT or BUSY output function. When configured as an ALERT, this pin acts as
an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATA
DATA
register values. See the Limit Registers section. When configured as a BUSY output, this pin becomes
LOW
HIGH
active when a conversion is in progress. Open-drain output. An external pull-up resistor is required.
9 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. An external pull-up resistor is required.
10 SCL Digital Input. Serial bus clock. Open-drain output. An external pull-up resistor is required.
Table 6. I2C Address Selection
Part Number AS Pin I2C Address
AD7992-0 GND 010 0001
AD7992-0 VDD 010 0010
AD7992-1 GND 010 0011
AD7992-1 VDD 010 0100
AD7992-x
1
Float 010 0000
1
If the AS pin is left floating on any of the AD7992 parts, the device address is 010 0000. This gives each AD7992 device three different address options.
or
Rev. 0 | Page 8 of 28
AD7992
TERMINOLOGY
Signal-to-Noise and Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
/2), excluding dc. The ratio
S
is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise and distortion ratio for
an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, the SINAD is 74 dB for a 12-bit converter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7992, it is defined as
22222
VVVVV
++++
65432
THD
where V
V
is the rms amplitude of the fundamental, and V2, V3,
1
, V5, and V6 are the rms amplitudes of the second through
4
log20)dB(
=
1
V
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f
/2 and excluding dc) to the rms
S
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n equal zero. For example,
second-order terms include (fa + fb) and (fa − fb), while
third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb), and
(fa − 2fb).
The AD7992 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of intermodulation distortion is,
like the THD specification, the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals, expressed in dB.
Channel-to-Channel Isolation
A measure of the level of crosstalk between channels, taken
by applying a full-scale sine wave signal to the unselected input
channels, and determining how much the 108 Hz signal is
attenuated in the selected channel. The sine wave signal applied
to the unselected channels is then varied from 1 kHz up to
2 MHz, each time determining how much the 108 Hz signal in
the selected channel is attenuated. This figure represents the
worst-case level across all channels.
Aperture Delay
The measured interval between the sampling clock’s leading
edge and the point at which the ADC takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time
when the sample is taken.
Full-Power Bandwidth
The input frequency at which the amplitude of the reconstructed
fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at the full-scale
frequency, f, to the power of a 200 mV p-p sine wave applied
to the ADC V
PSRR (dB) = 10 log (Pf/Pf
where Pf is the power at frequency f in the ADC output; Pf
the power at frequency f
supply of frequency fS:
DD
)
S
coupled onto the ADC VDD supply.
S
is
S
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, AGND + 1 LSB.
Offset Error Match
The difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, REF
− 1 LSB) after the
IN
offset error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Rev. 0 | Page 9 of 28
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