ANALOG DEVICES AD7982 Service Manual

18-Bit, 1 MSPS PulSAR 7.0 mW

V

V

±

FEATURES

18-bit resolution with no missing codes
Throughput: 1 MSPS
Low power dissipation

7.0 mW at 1 MSPS

70 μW at 10 kSPS
INL: ±1 LSB typical, ±2 LSB maximum
Dynamic range: 99 dB
True differential analog input range: ±V

0 V to V

with V

REF

between 2.5 V to 5.0 V

REF

Allows use of any input range

Easy to drive with the

ADA4941
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic

interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN

(LFCSP), SOT-23 size

APPLICATIONS

Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems

REF

ADC in MSOP/QFN

AD7982

APPLICATION DIAGRAM EXAMPLE

2.5V TO 5

10V, ±5V, ..

ADA4941

GENERAL DESCRIPTION

The AD7982 is an 18-bit, successive approximation, analog-to­digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
and a versatile serial interface port. On the CNV rising edge,
the AD7982 samples the voltage difference between the IN+
and IN− pins. The voltages on these pins usually swing in
opposite phases between 0 V and V
REF, is applied externally and can be set independent of the
supply voltage, VDD. Its power scales linearly with throughput.

The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.

REF

IN+

AD7982

IN–

GND

Figure 1.

2.5

VIO

VDD

SDI

SCK

SDO

CNV

. The reference voltage,

REF

1.8V TO 5V

3- OR 4-WI RE
INTERFACE
(SPI, CS
DAISY CHAIN)

06513-001

The AD7982 is available in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADCs

Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver

18-Bit True Differential AD7691 AD7690 AD7982 ADA4941
AD7984 ADA4841
16-Bit True Differential AD7684 AD7687 AD7688 ADA4941
AD7693 ADA4841
16-Bit Pseudo Differential AD7680 AD7685 AD7686 AD7980 ADA4841
AD7683 AD7694
14-Bit Pseudo Differential AD7940 AD7942 AD7946 ADA4841

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD7982

TABLE OF CONTENTS

Features .............................................................................................. 1

Driver Amplifier Choice ........................................................... 14

Applications....................................................................................... 1

Application Diagram Example........................................................1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ...........................7

Te r mi n ol o g y ...................................................................................... 8

Typical Performance Characteristics............................................. 9

Theory of Operation ...................................................................... 12

Circuit Information.................................................................... 12

Converter Operation.................................................................. 12

Typical Con ne ction Diag ram ................................................... 13

Analog Inputs.............................................................................. 14

Single-to-Differential Driver .................................................... 15

Voltage Reference Input ............................................................ 15

Power Supply............................................................................... 15

Digital Interface.......................................................................... 16

CS

Mode, 3-Wire Without Busy Indicator .............................17

CS

Mode, 3-Wire with Busy Indicator.................................... 18

CS

Mode, 4-Wire Without Busy Indicator .............................19

CS

Mode, 4-Wire with Busy Indicator.................................... 20

Chain Mode Without Busy Indicator...................................... 21

Chain Mode with Busy Indicator............................................. 22

Application Hints ........................................................................... 23

Layout ..........................................................................................23

Evaluating AD7982 Performance............................................. 23

Outline Dimensions .......................................................................24

Ordering Guide .......................................................................... 24

REVISION HISTORY

10/07—Rev. 0 to Rev. A

Changes to Table 1 and Layout....................................................... 1

Changes to Table 2............................................................................ 3

Changes to Layout............................................................................ 5

Changes to Layout............................................................................ 6

Changes to Figure 5.......................................................................... 7

Changes to Figure 18 and Figure 20............................................. 11

Changes to Figure 23...................................................................... 13

Changers to Figure 26.................................................................... 15

Changes to Digital Interface Section............................................ 16

Changes to Figure 38...................................................................... 21

Changes to Figure 40...................................................................... 22

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

3/07—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7982

SPECIFICATIONS

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range IN+ − IN− −V

REF

Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V

× 0.475 V

REF

Analog Input CMRR fIN = 450 kHz 67 dB
Leakage Current at 25°C Acquisition phase 200 nA
Input Impedance See the Analog Inputs section

ACCURACY

No Missing Codes 18 Bits
Differential Linearity Error −0.85 ±0.5 +1.5 LSB
Integral Linearity Error −2 ±1 +2 LSB
Transition Noise REF = 5 V 1.05 LSB
Gain Error, T

MIN

to T

MAX

2

−0.023 +0.004 +0.023 % of FS
Gain Error Temperature Drift ±1 ppm/°C
Zero Error, T

MIN

to T

MAX

2

±100 +700 μV
Zero Temperature Drift 0.5 ppm/°C
Power Supply Rejection Ratio VDD = 2.5 V ± 5% 90 dB

THROUGHPUT

Conversion Rate 0 1 MSPS
Transient Response Full-scale step 290 ns

AC ACCURACY

Dynamic Range V
V
Oversampled Dynamic Range

4

Signal-to-Noise fIN = 1 kHz, V
f

= 5 V 97 99 dB

REF

= 2.5 V 93 dB

REF

FO = 1 kSPS 129 dB

= 5 V, TA = 25°C 95.5 98 dB

REF

= 1 kHz, V

IN

= 2.5 V, TA = 25°C 92.5 dB

REF

Spurious-Free Dynamic Range fIN = 10 kHz −115 dB
Total Harmonic Distortion
Signal-to-(Noise + Distortion) fIN = 1 kHz, V

1

LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 μV.

2

See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

3

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

4

Dynamic range is obtained by oversampling the ADC running at a throughput Fs of 1 MSPS followed by postdigital filtering with an output word rate of FO.

5

Tested fully in production at fIN = 1 kHz.

5

fIN = 10 kHz −120 dB

= 5 V, TA = 25°C 97 dB

REF

+V

× 0.5 V

REF

REF

+ 0.1 V

REF

× 0.525 V

REF

V

1

1

1

3

3

3

3

3

3

3

3

Rev. A | Page 3 of 24

AD7982

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 2.4 5.1 V
Load Current 1 MSPS, REF = 5 V 350 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 10 MHz
Aperture Delay VDD = 2.5 V 2 ns

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Serial 18 bits, twos complement
Pipeline Delay

VOL I
VOH I

POWER SUPPLIES

VDD 2.375 2.5 2.625 V
VIO Specified performance 2.3 5.5 V
VIO Range 1.8 5.5 V
Standby Current

1, 2

Power Dissipation 10 kSPS throughput 70 86 μW
1 MSPS throughput 7.0 8.6 mW
Energy per Conversion 7.0 nJ/sample

TEMPERATURE RANGE

3

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact an Analog Devices, Inc. sales representative for the extended temperature range.

VIO > 3 V –0.3 +0.3 × VIO V
VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIO ≤ 3 V –0.3 +0.1 × VIO V
VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V

−1 +1 μA

−1 +1 μA

Conversion results available immediately

after completed conversion

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

VDD and VIO = 2.5 V, 25°C 0.35 μA

MIN

to T

MAX

−40 +85 °C

Rev. A | Page 4 of 24

AD7982

TIMING SPECIFICATIONS

CONV

ACQ

CYC

t

CNVH

t

SCK

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

DIS

SSDICNV

t

HSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

1

500 710 ns
290 ns
1000 ns
10 ns

4.5 ns

4.5 ns
3 ns

20 ns
5 ns
2 ns
0 ns
5 ns
5 ns
2 ns
3 ns
15 ns

TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)

SCK Period (CS Mode)

VIO Above 4.5 V 10.5 ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns

SCK Period (Chain Mode) t

VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns

SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 3 V 10 ns
VIO Above 2.3 V 15 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge t
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

1

See Figure 2 and Figure 3 for load conditions.

1

Y% VIO

t

DELAY

V
V

2

IH

2

IL

06513-003

TO SDO

20pF

C

L

500µA I

500µA I

OL

1.4V

OH

06513-002

Figure 2. Load Circuit for Digital Interface Timing

1

X% VIO

t

DELAY

2

V

IH

2

V

IL

1

FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VI O > 3.0V, X = 70, AND Y = 30.

2

MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing

Rev. A | Page 5 of 24

AD7982

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+, IN− to GND

Supply Voltage

REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +3.0 V

VDD to VIO +3 V to −6 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

10-Lead MSOP 200°C/W

10-Lead QFN (LFCSP_WD) 48.7°C/W
θJC Thermal Impedance

10-Lead MSOP 44°C/W

10-Lead QFN (LFCSP_WD) 2.96°C/W
Lead Temperatures

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1

See the Analog Inputs section for an explanation of IN+ and IN−.

1

−0.3 V to V
or ±130 mA

+ 0.3 V

REF

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 24

AD7982

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7982

3

TOP VIEW

(Not to Scale)

4

5

10

VIO

SDI

9

SCK

8

SDO

7

CNV

6

06513-004

Figure 4. 10-Lead MSOP Pin Configuration

1REF

2VDD

AD7982

3IN+

TOP VIEW

4IN–

5GND

Figure 5. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6 CNV

06513-005

Table 6. Pin Function Descriptions

Pin

Mnemonic Type

No.

1 REF AI

1

Description

Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and should

be decoupled closely to the GND pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

selects the interface mode of the part: chain mode or

CS mode. In CS mode, the SDO pin is enabled

when CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is

output on SDO with a delay of 18 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator

feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 7 of 24

AD7982

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see

Figure 22).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.999943 V for the ±5 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first transition
from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows

ENOB = (SINAD

− 1.76)/6.02

dB

and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as

Noise-Free Code Resolution = log

(2N/Peak-to-Peak Noise)

2

and is expressed in bits.

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log

(2N/RMS Input Noise)

2

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dBF so that it includes all noise
sources and DNL artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.

Aperture Delay

Aperture delay is the measure of the acquisition performance
and is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.

Transi ent Res p ons e

Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.

Rev. A | Page 8 of 24