ANALOG DEVICES AD7951 Service Manual

14-Bit, 1 MSPS, Unipolar/Bipolar

VCCV

FEATURES

Multiple pins/software programmable input ranges:

5 V, 1 0 V, ± 5 V, ±1 0 V
Pins or serial SPI® compatible input ranges/mode selection
Throughput

1 MSPS (warp mode)

800 kSPS (normal mode)

670 kSPS (impulse mode)
14-bit resolution with no missing codes
INL: ±0.3 LSB typ, ±1 LSB max (±61 ppm of FSR)
SNR: 85 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation:

10 mW @ 100 kSPS

235 mW @ 1 MSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages

APPLICATIONS

Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
AT E

GENERAL DESCRIPTION

The AD7951 is a 14-bit, charge redistribution, successive
approximation register (SAR) architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write only serial configuration port for input
range and operating mode. The AD7951 contains a high speed
14-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial

CNVST

and parallel system interface ports. A falling edge on
samples the analog input on IN+ with respect to a ground
sense, IN−. The AD7951 features four different analog input
ranges and three different sampling modes: warp mode for the
fastest throughput, normal mode for the fastest asynchronous
throughput, and impulse mode where power is scaled with
throughput. Operation is specified from −40°C to +85°C.

Programmable Input PulSAR® ADC

AD7951

FUNCTIONAL BLOCK DIAGRAM

TEMP

REFBUFIN

AGND

AVDD
PDREF
PDBUF

CNVST

RESET

REF

IN+
IN–

PD

CONTROL LOGIC AND

CALIBRATI ON CIRCUITRY

WARP IMPULSE BIPOLAR TEN

REF REFGND

REF
AMP

SWITCHED

CAP DAC

CLOCK

Figure 1.

EE

AD7951

SERIAL DATA

CONFIGURATION

PARALLEL

INTERFACE

Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection

100 kSPS to

Type

Pseudo
Differential

True Bipolar AD7610

True
Differential

18-Bit, True
Differential

Multichannel/
Simultaneous

250 kSPS

AD7651
AD7660
AD7661

AD7663

AD7675 AD7676 AD7677 AD7621

AD7678 AD7679 AD7674 AD7641

AD7654

500 kSPS to
570 kSPS

AD7650
AD7652
AD7664
AD7666

AD7665 AD7951

AD7655

DGNDDVDD

OVDD
OGND

PORT

SERIAL

PORT

14

D[13:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
RD
CS

570 kSPS to
1000 kSPS

AD7653
AD7667

AD7612
AD7671

>1000
kSPS

AD7622
AD7623

AD7643

06396-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7951

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 12

Te r mi n ol o g y .................................................................................... 16

Theory of Operation ...................................................................... 17

Overview...................................................................................... 17

Converter Operation.................................................................. 17

Modes of Operation ................................................................... 18

Transfer Fu nctions ...................................................................... 18

Typical Con ne ction Diag ram ................................................... 19

Analog Inputs.............................................................................. 20

Driver Amplifier Choice ........................................................... 21

Voltage Reference Input/Output.............................................. 21

Power Supplies............................................................................ 22

Conversion Control ................................................................... 23

Interfaces.......................................................................................... 24

Digital Interface.......................................................................... 24

Parallel Interface......................................................................... 24

Serial Interface............................................................................ 25

Master Serial Interface............................................................... 25

Slave Serial Interface .................................................................. 27

Hardware Configuration ...........................................................29

Software Configuration............................................................. 29

Microprocessor Interfacing....................................................... 30

Application Information................................................................ 31

Layout Guidelines....................................................................... 31

Evaluating Performance ............................................................ 31

Outline Dimensions .......................................................................32

Ordering Guide .......................................................................... 32

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7951

SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 14 Bits
ANALOG INPUT

Voltage Range, V

IN

V
V
V
V

V

− V

IN+

IN+

IN+

IN+

IN−

= 0 V to 5 V −0.1 +5.1 V

IN−

− V

= 0 V to 10 V −0.1 +10.1 V

IN−

− V

= ±5 V −5.1 +5.1 V

IN−

− V

= ±10 V −10.1 +10.1 V

IN−

to AGND −0.1 +0.1 V
Analog Input CMRR fIN = 100 kHz 75 dB
Input Current V

= ±5 V, ±10 V @ 1 MSPS 300

IN

Input Impedance See the Analog Inputs section

THROUGHPUT SPEED

Complete Cycle In warp mode 1 s
Throughput Rate In warp mode 1 1 MSPS
Time Between Conversions In warp mode 1 ms
Complete Cycle In normal mode 1.25 s
Throughput Rate In normal mode 0 800 kSPS
Complete Cycle In impulse mode 1.49 s
Throughput Rate In impulse mode 0 670 kSPS

DC ACCURACY

Integral Linearity Error
No Missing Codes
Differential Linearity Error

2

2

2

−1 ±0.3 +1 LSB
14 Bits

−1 +1 LSB
Transition Noise 0.55 LSB
Zero Error (Unipolar or Bipolar) −15 +15 LSB
Zero Error Temperature Drift ±1 ppm/°C
Full-Scale Error (Unipolar or Bipolar) −20 +20 LSB
Full-Scale Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB

AC ACCURACY

Dynamic Range fIN = 2 kHz, −60 dB 84.5 85.5 dB
Signal-to-Noise Ratio fIN = 2 kHz 84.5 85.5 dB
f

= 20 kHz 85.5 dB

IN

Signal-to-(Noise + Distortion) (SINAD) fIN = 2 kHz 83 85.4 dB
Total Harmonic Distortion fIN = 2 kHz −105 dB
Spurious-Free Dynamic Range fIN = 2 kHz 102 dB
–3 dB Input Bandwidth V

= 0 V to 5 V 45 MHz

IN

Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 500 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 4.965 5.000 5.035 V
Temperature Drift –40°C to +85°C ±3 ppm/°C
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time C

= 22 µF 10 ms

REF

= 5 V; all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

1

µA

3

4

Rev. 0 | Page 3 of 32

AD7951

Parameter Conditions/Comments Min Typ Max Unit

REFERENCE BUFFER PDREF = high

REFBUFIN Input Voltage Range 2.4 2.5 2.6 V

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain 1 MSPS throughput 200 µA

TEMPERATURE PIN

Voltage Output @ 25°C 311 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.33 kΩ

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Parallel or serial 14-bit
Pipeline Delay

V

OL

V

OH

5

POWER SUPPLIES

Specified Performance

AVDD 4.75
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V

Operating Current

7, 8

AVDD

With Internal Reference 20 mA
With Internal Reference Disabled 18.5 mA

DVDD 7 mA
OVDD 0.5 mA
VCC VCC = 15 V, with internal reference buffer 4 mA
VCC = 15 V 3 mA
VEE VEE = −15 V 2 mA

Power Dissipation @ 1 MSPS throughput

With Internal Reference PDREF = PDBUF = low 235 260 mW
With Internal Reference Disabled PDREF = PDBUF = high 215 240 mW

In Power-Down Mode9 PD = high 10 µW

TEMPERATURE RANGE

10

Specified Performance T

1

With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 100 A. In all input ranges, the input current scales with throughput. See the An alog In puts section.

2

Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.

3

LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.

4

All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Conversion results are available immediately after completed conversion.

6

4.75 V or V

7

Tested in parallel reading mode.

8

With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.

9

With all digital inputs forced to OVDD.

10

Consult sales for extended temperature range.

– 0.1 V, whichever is larger.

REF

−0.3 +0.6 V

2.1 OVDD + 0.3 V

−1 +1 µA

−1 +1 µA

I

= 500 µA 0.4 V

SINK

I

= –500 µA OVDD − 0.6 V

SOURCE

6

5 5.25 V

@ 1 MSPS throughput

MIN

to T

MAX

−40 +85 °C

Rev. 0 | Page 4 of 32

AD7951

TIMING SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (See Figure 33 and Figure 34)

Convert Pulse Width t
Time Between Conversions t

Warp Mode/Normal Mode/Impulse Mode

1

CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert) t

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns
Aperture Delay t
End of Conversion to BUSY Low Delay t
Conversion Time t

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns
Acquisition Time t

Warp Mode/Normal Mode/Impulse Mode 200 ns
RESET Pulse Width t

PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)

CNVST Low to DATA Valid Delay

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns
DATA Valid to BUSY Low Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)

CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay

2

CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert

Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns
SYNC Asserted to SDCLK First Edge Delay t
Internal SDCLK Period
Internal SDCLK High
Internal SDCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SDCLK Last Edge to SYNC Delay

3

3

3

3

3

3

CS High to SYNC High-Z
CS High to Internal SDCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert

3

CNVST Low to SYNC Delay, Read After Convert

Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns
SYNC Deasserted to BUSY Low Delay t

= 5 V; all specifications T

REF

1

2

10 ns

MIN

to T

, unless otherwise noted.

MAX

1/1.25/1.49 s
t

3

4

5

6

7

8

9

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

30

35 ns

2 ns
10 ns

10 ns

20 ns
40 ns
2 15 ns

10 ns
10 ns
10 ns

3 ns
30 45 ns
15 ns
10 ns
4 ns
5 ns
5 ns
10 ns
10 ns

10 ns
See Table 4

25 ns

Rev. 0 | Page 5 of 32

AD7951

Parameter Symbol Min Typ Max Unit

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2

Figure 42, Figure 43, and Figure 45)

(See

External SDCLK, SCCLK Setup Time t
External SDCLK Active Edge to SDOUT Delay t
SDIN/SCIN Setup Time t
SDIN/SCIN Hold Time t
External SDCLK/SCCLK Period t
External SDCLK/SCCLK High t
External SDCLK/SCCLK Low t

1

In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.

2

In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3

In serial master read during convert mode. See Table 4 for serial master read after convert mode.

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SDCLK First Edge Delay Minimum t
Internal SDCLK Period Minimum t
Internal SDCLK Period Maximum t
Internal SDCLK High Minimum t
Internal SDCLK Low Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SDCLK Last Edge to SYNC Delay Minimum t
BUSY High Width Maximum t

Warp Mode 1.60 2.35 3.75 6.75 µs
Normal Mode 1.85 2.60 4.00 7.00 µs
Impulse Mode 2.10 2.85 4.25 7.25 µs

31

32

33

34

35

36

37

18

19

19

20

21

22

23

24

28

5 ns
2 18 ns
5 ns
5 ns
25 ns
10 ns
10 ns

3 20 20 20 ns
30 60 120 240 ns
45 90 180 360 ns
12 30 60 120 ns
10 25 55 115 ns
4 20 20 20 ns
5 8 35 90 ns
5 7 35 90 ns

1.6mA I

TO OUTPUT

PIN

C

L

60pF

500µA I

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEF INED WIT H A MAXIMUM LO AD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C

OL

1.4V

0.8V

t

OH

6396-002

DELAY

2V

2V

t

DELAY

2V

0.8V0.8V

06396-003

Figure 3. Voltage Reference Levels for Timing

= 10 pF

L

Rev. 0 | Page 6 of 32

AD7951

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,
REFGND to AGND

AVDD + 0.3 V to
AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V
VEE to GND +0.3 V to −16.5 V

Digital Inputs −0.3 V to OVDD + 0.3 V
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation

2

3

4

±20 mA
700 mW

2.5 W
Junction Temperature 125°C
Storage Temperature Range −65°C to +125°C

1

See the Analog Inputs section.

2

See the Voltage Reference Input section.

3

Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,

θJC = 30°C/W.

4

Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 32

AD7951

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VEE

DGND

IN–

VCC

REFGND

REF

36

BIPOLAR

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

TEN

29

BUSY

28

D13/SCCS

27

D12/SCCLK

26

D11/SCIN

25

D10/HW/SW

D8/SYNC

D7/SDCLK

D6/SDOUT

D9/RDERROR

06396-004

AGND
AVDD
AGND

BYTESWAP

OB/2C

WARP
IMPULSE
SER/PAR

NC

10

NC
D0/DIVSCLK[0]
D1/DIVSCLK[1]

NC = NO CONNECT

11
12

PDBUF

PDREF

REFBUFIN

48 47 46 45 44 43 42 41 40 39 38 37

1

PIN 1

2
3
4
5
6
7
8
9

13

14 15 16 17 18 19 20 21 22 23 24

D2/EXT/INT

D4/INVSCLK

D3/INVSYNC

IN+

TEMP

AVDD

AD7951

TOP VIEW

(Not to S cale)

OVDD

OGND

D5/RDC/SDIN

AGND

DVDD

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 3, 42 AGND P

Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,

the AGND, DGND, and OGND voltages should be at the same potential.
2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4 BYTESWAP DI

Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output

on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

2

5

OB/2C

DI

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.

When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI2 Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:

Conversion Mode WARP IMPULSE

Normal Low Low
Impulse Low High
Warp High Low
Normal High High

See the Modes of Operation section for a more detailed description.
7 IMPULSE DI2

Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the

Modes of Operation section for a more detailed description.
8

SER/PAR

DI Serial/Parallel Selection Input.

When SER/PAR = low, the parallel mode is selected.

When SER/PAR

= high, the serial modes are selected. Some bits of the data bus are used as a serial port

and the remaining data bits are high impedance outputs.
9, 10 NC DO No Connect. Do not connect.
11, 12 D[0:1] or DI/O In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus.
DIVSCLK[0:1]

Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR

= low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial

EXT/INT

= high,

data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

Rev. 0 | Page 8 of 32

AD7951

Pin No. Mnemonic Type1 Description

13 D2 or DI/O In parallel mode, this output is used as Bit 2 of the parallel port data output bus.

14 D3 or DI/O In parallel mode, this output is used as Bit 3 of the parallel port data output bus.
INVSYNC

15 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.

16 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
RDC or

SDIN

17 OGND P

18 OVDD P

19 DVDD P

20 DGND P

21 D6 or DO In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
SDOUT

22 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
SDCLK

23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SYNC

EXT/INT

Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated
(master) or external (slave) serial data clock for the AD7951 output data.

When EXT/INT
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated

by CS) connected to the SDCLK input.

Serial Data Invert Sync Select. In serial master mode (SER/PAR
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.

When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

Serial Data Read During Convert. In serial master mode (SER/PAR
select the read mode. Refer to the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not

attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
Serial Data In. In serial slave mode (SER/PAR
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data

level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be

connected to the system digital ground ideally at the same potential as AGND and DGND.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface

2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be

supplied from AVDD.
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system

digital ground ideally at the same potential as AGND and OGND.

Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7951 provides the conversion result, MSB
first, from its internal shift register. The data format is determined by the logic level of OB/2C

When EXT/INT
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent
on the logic state of the EXT/INT
the logic state of the INVSCLK pin.

Serial Data Frame Synchronization. In serial master mode (SER/PAR
is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.

= low, master mode; the internal serial data clock is selected on SDCLK output.

= high, EXT/INT = low). This input is used

= high, EXT/INT = low) RDC is used to

= high EXT/INT = high) SDIN can be used as a data input to

.

= low (master mode), SDOUT is valid on both edges of SDCLK.

pin. The active edge where the data SDOUT is updated depends on

= high, EXT/INT= low), this output

Rev. 0 | Page 9 of 32

AD7951

Pin No. Mnemonic Type1 Description

24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
RDERROR

25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus.

26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
SCIN

27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
SCCLK

28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus.

29 BUSY DO

30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following:

31
32

33 RESET DI

34 PD DI2

35

36 BIPOLAR DI2 Input Range Select. See description for Pin 30.
37 REF AI/O

38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI Analog Input. Referenced to IN−.

HW/SW

SCCS

RD
CS

CNVST

DI
DI

DI

Serial Data Read Error. In serial slave mode (SER/PAR

incomplete data read error flag. If a data read is started and not completed when the current

conversion is complete, the current data is lost and RDERROR is pulsed high.

Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure

the AD7951 by hardware or software. See the Hardware Configuration section and Software

Configuration section.

When HW/SW

When HW/SW

Serial Configuration Data Input. In serial software configuration mode (SER/PAR

this input is used to serially write in, MSB first, the configuration data into the serial configuration

register. The data on this input is latched with SCCLK. See the Software Configuration section.

Serial Configuration Clock. In serial software configuration mode (SER/PAR

input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on

the logic state of the INVSCLK pin. See the Software Configuration section.

Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low)

this input enables the serial configuration port. See the Software Configuration section.

Busy Output. Transitions high when a conversion is started, and remains high until the conversion

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be

used as a data ready clock signal. Note that in master read after convert mode (SER/PAR

EXT/INT

Input Range BIPOLAR TEN

0 V to 5 V Low Low
0 V to 10 V Low High
±5 V High Low

±10 V High High
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is

also used to gate the external clock in slave serial mode (not used for serial programmable port).
Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of

RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See
the Digital Interface section. If not used, this pin can be tied to OGND.

Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power-down.

Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.

Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled,
producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,
allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is
required with or without the internal reference and buffer. See the Reference Decoupling section.

= low, the AD7951 is configured through software using the serial configuration register.

= high, the AD7951 is configured through dedicated hardware input pins.

= low, RDC = low), the busy time changes according to Table 4.

= high, EXT/INT = high), this output is used as an

= high, HW/SW = low)

= high, HW/SW = low) this

= high,

Rev. 0 | Page 10 of 32