Analog Devices AD7869 Datasheet

LC2MOS

RO DAC

RI DAC

DGND

AD7869

R

R

RO ADC

AGND

CLOCK

R

R

14 - BIT

DAC

DAC

SERIAL

INTERFACE

ADC SERIAL
INTERFACE

14 - BIT

ADC

DAC 3V

REFERENCE

ADC 3V

REFERENCE

TRACK/HOLD

V

SS

V

DD

V

IN

V

OUT

LDAC

TFS

TCLK

DT

CONTROL

RFS

RCLK

DR

CLK

CONVST

a

Complete, 14-Bit Analog I/O System

FEATURES
Complete 14-Bit l/O System, Comprising

14-Bit ADC with Track/Hold Amplifier

83 kHz Throughput Rate

14-Bit DAC with Output Amplifier

3.5 ms Settling Time

On-Chip Voltage Reference
Operates from 65 V Supplies
Low Power—130 mW typ
Small 0.3" Wide DIP

APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control

GENERAL DESCRIPTION

The AD7869 is a complete 14-bit I/O system containing a DAC
and an ADC. The ADC is a successive approximation type with
a track-and-hold amplifier, having a combined throughput rate
of 83 kHz. The DAC has an output buffer amplifier with a set­tling time of 4 µs to 14 bits. Temperature compensated 3 V bur-
ied Zener references provide precision references for the DAC
and ADC.

Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines.

Asynchronous ADC conversion control and DAC updating is
made possible with the

CONVST and LDAC logic inputs.

The AD7869 operates from ±5 V power supplies; the analog in­put/output range of the ADC/DAC is ±3 V. The part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.

The part is available in a 24-pin, 0.3 inch wide, plastic or her­metic dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.

AD7869

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Complete 14-Bit I/O System.
The AD7869 contains a 14-bit ADC with a track-and-hold
amplifier and a 14-bit DAC with output amplifier. Also in
cluded are separate on-chip voltage references for the DAC
and the ADC.

2. Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7869 is
specified for ac parameters, including signal-to-noise ratio
and harmonic distortion. These parameters, along with im­portant timing parameters, are tested on every device.

3. Small Package.
The AD7869 is available in a 24-pin DIP and a 28-pin SOIC
package.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1996

AD7869–SPECIFICA TIONS

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, f

ADC SECTION

Parameter J Version1A Version1Units Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio

T

to T

MIN

Total Harmonic Distortion (THD) –86 –86 dB typ V
Peak Harmonic or Spurious Noise –86 –86 dB typ V
Intermodulation Distortion (IMD)

Second Order Terms –86 –86 dB typ fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms –88 –88 dB typ fa = 9 kHz, fb = 9.5 kHz, f

Track/Hold Acquisition Time 2 2 µs max

DC ACCURACY

Resolution 14 14 Bits
Minimum Resolution 14 14 Bits No Missing Codes Are Guaranteed
Integral Nonlinearity ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max
Bipolar Zero Error ±20 ±20 LSB max
Positive Gain Error
Negative Gain Error

ANALOG INPUT

Input Voltage Range ±3 ±3 Volts
Input Current ±1 ±1 mA max

REFERENCE OUTPUT

RO ADC @ +25°C 2.99/3.01 2.99/3.01 V min/ V max
RO ADC TC ±25 ±25 ppm/°C typ

Reference Load Sensitivity

(∆RO ADC vs. ∆I) –1.5 –1.5 mV max Reference Load Current Change (0–500 µA),

LOGIC INPUTS

(

CONVST, CLK, CONTROL)

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current7 (CONTROL & CLK) ±10 ±10 µA max VIN = VSS to DGND
Input Capacitance, C

LOGIC OUTPUTS

DR,

Output Low Voltage, V

RCLK Output

Output Low Voltage, V

DR,

Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance

CONVERSION TIME

External Clock 10 10 µs max
Internal Clock 10 10 µs max The Internal Clock Has a Nominal Value of 2.0 MHz

POWER REQUIREMENTS For Both DAC and ADC

V

DD

V

SS

I

DD

I

SS

Total Power Dissipation 170 170 mW max Typically 130 mW

NOTES

1

Temperature ranges are as follows: J Version, 0°C to +70° C; A Version, –40°C to +85 °C.

2

VIN = ±3 V.

3

SNR calculation includes distortion and noise components.

4

SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.

5

Measured with respect to internal reference.

6

For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).

7

Tying the CONTROL input to VDD places the device in a factory test mode where normal operation is not exhibited.

8

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

MAX

RFS Outputs

RFS, RCLK Outputs

All specifications T

2

3, 4

(SNR) @ +25°C 78 78 dB min VIN = 10 kHz Sine Wave, f

MIN

to T

unless otherwise noted.)

MAX

78 77 dB min

5

5

6

±20 ±20 LSB max
±20 ±20 LSB max

±40 ±ppm/°C max

INH

INL

IN

8

IN

OL

OL

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 µA max VIN = 0 V to V

10 10 pF max

0.4 0.4 V max I

0.4 0.4 V max I

8

15 15 pF max

+5 +5 V nom ±5% for Specified Performance
–5 –5 V nom ±5% for Specified Performance
22 22 mA max Cumulative Current from the Two VDD Pins
12 12 mA max Cumulative Current from the Two VSS Pins

= 2.0 MHz external.

CLK

= 10 kHz Sine Wave, f

IN

= 10 kHz Sine Wave, f

IN

Reference Load Should Not Be Changed
During Conversion

DD

= 1.6 mA, Pull-Up Resistor = 4.7 kΩ

SINK

= 2.6 mA, Pull-Up Resistor = 2 kΩ

SINK

SAMPLE

SAMPLE
SAMPLE

SAMPLE
SAMPLE

= 83 kHz
= 83 kHz

= 83 kHz
= 50 kHz

= 50 kHz

–2–

REV. A

AD7869

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, Rl DAC = +3 V and decoupled as shown in Figure 2,
V

DAC SECTION

Load to AGND; = 2 kV, CL = 100 pF. All specifications T

OUT

Parameter J Versions1A Version1Units Test Conditions/Comments

DYNAMIC PERFORMANCE

2

Signal-to-Noise Ratio3 (SNR) @ +25°C 78 78 dB min V

to T

T

MIN

MAX

78 77 dB min Typically 82 dB at +25°C for 0 < V

Total Harmonic Distortion (THD) –86 –86 dB typ V
Peak Harmonic or Spurious Noise –86 –86 dB typ V

DC ACCURACY

Resolution 14 14 Bits
Integral Nonlinearity ±2 ± 2 LSB max
Differential Nonlinearity ±1 ± 1 LSB max Guaranteed Monotonic
Bipolar Zero Error ±10 ±10 LSB max
Positive Full-Scale Error
Negative Full-Scale Error

REFERENCE OUTPUT

5

5

6

±10 ±10 LSB max
±10 ±10 LSB max

RO DAC @ +25°C 2.99/3.01 2.99/3.01 V min/V max
RO DAC TC ±25 ±25 ppm/°C typ

±40 ppm/°C max

Reference Load Change

(∆RO DAC vs. ∆I) –1.5 –1.5 mV max Reference Load Current Change (0 µA–500 µA)

REFERENCE INPUT

RI DAC Input Range 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current 1 1 µA max

LOGIC INPUTS

LDAC, TFS, TCLK, DT)

(

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

7

2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 µA max VIN = 0 V to V
10 10 pF max

ANALOG OUTPUT

Output Voltage Range ±3 ±3 V nom
DC Output Impedance 0.3 0.3 Ω typ
Short-Circuit Current 20 20 mA typ

AC CHARACTERISTICS

7

Voltage Output Settling-Time Settling Time to Within ±1/2 LSB of Final Value

Positive Full-Scale Change 4 4 µs max Typically 3 µs

Negative Full-Scale Change 4 4 µs max Typically 3.5 µs
Digital-to-Analog Glitch Impulse 10 10 nV secs typ DAC Code Change All 1s to All 0s
Digital Feedthrough 2 2 nV secs typ
VIN to V

Isolation 100 100 dB typ VIN = ±3 V, 41.5 kHz Sine Wave

OUT

POWER REQUIREMENTS As per ADC Section

NOTES

1

Temperature ranges are as follows: J Version, 0°C to +70° C; A Version, –40°C to +85 °C.

2

V

(p-p) = ±3 V.

OUT

3

SNR calculation includes distortion and noise components.

4

Using external sample and hold, see Figures 13 to 15.

5

Measured with respect to REF IN and includes bipolar offset error.

6

For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).

7

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice

to T

MIN

unless otherwise noted.)

MAX

= 1 kHz Sine Wave, f

OUT

= 1 kHz Sine Wave, f

OUT

Typically –84 dB at +25°C for 0 < V

= 1 kHz, f

OUT

SAMPLE

Typically –84 dB at +25°C for 0 < V

DD

SAMPLE

SAMPLE

= 83 kHz

= 83 kHz

< 20 kHz

OUT

= 83 kHz

< 20 kHz

OUT

< 20 kHz

OUT

4

4

4

REV. A

–3–

AD7869

MIN

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)

, T

MAX

TIMING SPECIFICATIONS

Limit at T

Parameter (All Versions) Units Conditions/Comments

ADC TIMING

t

1

3

t

2

t

3

t

4

4

t

5

t

6

5

t

13

DAC TIMING

t

7

t

8

t

9

t

10

t

11

t

l2

NOTES

1

Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.

2

Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 k Ω pull-up resistor on RCLK. The capacitance on all three outputs is 35 pF.

3

When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.

4

DR will drive higher capacitance loads but this will add to t5 since it increases the external RC time constant (4.7 k Ω//CL) and hence the time to reach 2.4 V.

5

Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.

6

TCLK mark/space ratio is 40/60 to 60/40.

50 ns min CONVST Pulse Width
440 ns min RCLK Cycle Time, Internal Clock
100 ns min RFS to RCLK Falling Edge Setup Time
20 ns min RCLK Rising Edge to RFS
100 ns max
155 ns max RCLK to Valid Data Delay, CL = 35 pF
4 ns min Bus Relinquish Time after RCLK
100 ns max
2 RCLK + 200 to ns typ CONVST to RFS Delay
3 RCLK + 200

50 ns min TFS to TCLK Falling Edge
75 ns min TCLK Falling Edge to TFS
150 ns min TCLK Cycle Time
30 ns min Data Valid to TCLK Setup Time
75 ns min Data Valid to TCLK Hold Time
40 ns min LDAC Pulse Width

ABSOLUTE MAXIMUM RATINGS*

(TA = + 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

SS

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to V

OUT

VIN to AGND . . . . . . . . . . . . . . . . V

–0.3 V to VDD + 0.3 V

SS

RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V

RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V

RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

Digital Outputs to DGND . . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

DD

Operating Temperature Range

J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Signal-

Temperature to-Noise Relative Package

Model Range Ratio (SNR) Accuracy Option*

AD7869JN 0°C to +70°C 78 dB ±2 LSB max N-24
AD7869JR 0°C to +70°C 78 dB ±2 LSB max R-28
AD7869AQ –40°C to +85°C 77 dB ±2 LSB max Q-24

*N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. A

AD7869

0.01 (0.254)

0.006 (0.15)

0.019 (0.49)

0.014 (0.35)

0.096 (2.44)

0.089 (2.26)

0.05
(1.27)
BSC

0.013 (0.32)

0.009 (0.23)

0.042 (1.067)

0.018 (0.457)

6°
0°

0.03 (0.76)

0.02 (0.51)

x 45°

0.708 (18.02)

0.696 (17.67)

0.414 (10.52)

0.398 (10.10)

0.299 (7.6)

0.291 (7.39)

28 15

141

1. LEAD NO. 1 INDENTIFIED BY A DOT.

2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.

AD7869 PIN FUNCTION DESCRIPTION

DIP Pin
Number Mnemonic Function

POWER SUPPLY
7 & 23 V

10 & 22 V

DD
SS

8 & 19 AGND Analog Ground. Both AGND pins must be tied together.
6 & 17 DGND Digital Ground. Both DGND pins must be tied together.

ANALOG SIGNAL AND REFERENCE
21 V

9V

IN
OUT

20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a

11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this

12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally

ADC INTERFACE AND CONTROL
2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to V

3

RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output that provides a framing

4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external

5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with

1

CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold

24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-

DAC INTERFACE AND CONTROL
14

TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial
15 DT Transmit Data, Logic Input. This is the data input that is used in conjunction with
16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when

13

LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
18 NC No Connect.

Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.

ADC Analog Input. The ADC input range is ±3 V.
Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ±3 V

with RI DAC = +3 V.

reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 µA.

internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 µA.

buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7869 is 3 V.

enables the internal laser-trimmed oscillator.

SS

pulse for serial data. An external 4.7 kΩ pull-up resistor is required on

ADC clock. If the CONTROL input is at V

, the clock runs continuously. With the CONTROL input at DGND,

SS

RFS.

the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 kΩ pull-up resistor.

RFS and RCLK to transmit

data from the ADC. Serial data is valid on the falling edge of RCLK when

RFS is low. An external 4.7 kΩ resistor is

required on the DR output.

mode and starts an ADC conversion. This input is asynchronous to the CLK input.

uous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited.

data expected after the falling edge of this signal.

TFS and TCLK to transfer

serial data to the input latch.

TFS is low.

of this signal.

CONVST

REV. A

RCLK

DGND

AGND

RO DAC

RI DAC

V

CLK
RFS

V

V

DR

OUT

1
2
3
4
5
6
7

DD

8
9

10

SS

11
12

DIP

AD7869

TOP VIEW

(Not to Scale)

NC = NO CONNECT

24
23
22
21
20
19
18
17
16
15
14
13

CONTROL
V

DD

V

SS

V

IN

RO ADC
AGND
NC
DGND
TCLK
DT
TFS

LDAC

PIN CONFIGURATIONS

SOIC

–5–