Analog Devices AD7868BR, AD7868BQ, AD7868AR, AD7868AQ, AD7868AN Datasheet

LC2MOS

RO DAC

RI DAC

DGND

AD7868

R

R

RO ADC

AGND

CLOCK

R

R

12-BIT

DAC

DAC SERIAL

INTERFACE

ADC SERIAL
INTERFACE

12-BIT

ADC

DAC 3V

REFERENCE

ADC 3V

REFERENCE

TRACK/HOLD

V

IN

V

OUT

LDAC

TFS

TCLK

DT

CONTROL

RFS

RCLK

DR

CLK

CONVST

V

DD

V

SS

a

Complete, 12-Bit Analog I/O System

FEATURES
Complete 12-Bit I/O System, Comprising:

12-Bit ADC with Track/Hold Amplifier

83 kHz Throughout Rate
72 dB SNR

12-Bit DAC with Output Amplifier

3 ms Settling Time
72 dB SNR

On-Chip Voltage Reference
Operates from 65 V Supplies
Low Power – 130 mW typ
Small 0.3" Wide DIP

APPLICATIONS
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modems
DSP Servo Control

GENERAL DESCRIPTION

The AD7868 is a complete 12-bit I/O system containing a DAC
and an ADC . The ADC is a successive approximation type
with a track-and-hold amplifier having a combined throughput
rate of 83 kHz. The DAC has an output buffer amplifier with a
settling time of 3 µs to 12 bits. Temperature compensated 3 V
buried Zener references provide precision references for the
DAC and ADC.

Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines. Asyn­chronous ADC conversion control and DAC updating is made
possible with the

CONVST and LDAC logic inputs.

The AD7868 operates from ±5 V power supplies, the analog in­put/output range of the ADC/DAC is ±3 V. The part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.

The part is available in a 24-pin, 0.3" wide, plastic or hermetic
dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.

AD7868

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Complete 12-Bit I/O System.
The AD7868 contains a 12-bit ADC with a track-and-hold
amplifier and a 12-bit DAC with output amplifier. Also
included are separate on-chip voltage references for the DAC
and the ADC.

2. Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7868 is
specified for ac parameters including signal-to-noise ratio
and harmonic distortion. These parameters along with im­portant timing parameters are tested on every device.

3. Small Package.
The AD7868 is available in a 24-pin DIP and a 28-pin SOIC
package.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7868–SPECIFICA TIONS

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, f

ADC SECTION

unless otherwise noted.)

= 2.0 MHz external. All specifications T

CLK

MIN

to T

MAX-

Parameter Version1Version1Version1Units Test Conditions/Comments

ABT

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio

T

to T

MIN

Total Harmonic Distortion (THD) –78 –78 –76 dB max VIN = 10 kHz Sine Wave, f

MAX

Peak Harmonic or Spurious Noise –78 –78 –76 dB max VIN = 10 kHz Sine Wave, f

2

3, 4

(SNR) @ +25°C 70 72 70 dB min VIN = 10 kHz Sine Wave, f

70 71 70 dB min Typically 71.5 dB for 0 < VIN < 41.5 kHz

Typically 71.5 dB for 0 < VIN < 41.5 kHz
Typically 71.5 dB for 0 < VIN < 41.5 kHz

SAMPLE

SAMPLE

SAMPLE

= 83 kHz
= 83 kHz
= 83 kHz

Intermodulation Distortion (IMD)

Second Order Terms –78 –78 –76 dB max fa = 9 kHz, fb = 9.5 kHz, f
Third Order Terms –80 –80 –78 dB max fa = 9 kHz, fb = 9.5 kHz, f

Track/Hold Acquisition Time 2 2 2 µs max

SAMPLE
SAMPLE

= 50 kHz
= 50 kHz

DC ACCURACY

Resolution 12 12 12 Bits
Minimum Resolution 12 12 12 Bits No Missing Codes Are Guaranteed
Integral Nonlinearity ± 12 ± 12 ±12 LSB typ
Integral Nonlinearity ± 1 ±1 LSB max
Differential Nonlinearity ± 0.9 ± 0.9 ± 0.9 LSB max
Bipolar Zero Error ±5 ±5 ±5 LSB max
Positive Gain Error
Negative Gain Error

5

5

±5 ±5 ±5 LSB max
±5 ±5 ±5 LSB max

ANALOG INPUT

Input Voltage Range ±3 ±3 ±3 Volts
Input Current ± 1 ±1 ±1 mA max

REFERENCE OUTPUT

6

RO ADC @ +25°C 2.99/3.01 2.99/3.01 2.99/3.01 V min/V max
RO ADC TC ±25 ±25 ±25 ppm/°C typ
RO ADC TC ±40 ±50 ppm/°C max
Reference Load Sensitivity (∆RO ADC vs. ∆I) –1.5 –1.5 –1.5 mV max Reference Load Current Change (0 µA–500 µA),

Reference Load Should Not Be Changed
During Conversion

LOGIC INPUTS (CONVST, CLK, CONTROL)

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current7 (CONTROL Input Only) ±10 ±10 ±10 µA max VIN = VSS to DGND
Input Capacitance, C

INH

INL

IN

8

IN

2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 ±10 µA max VIN = 0 V to V

10 10 10 pF max

DD

LOGIC OUTPUTS

DR, RFS Outputs

Output Low Voltage, V

RCLK Output

Output Low Voltage, V

DR, RFS, RCLK Outputs

Floating-State Leakage Current ± 10 ±10 ±10 µA max
Floating-State Output Capacitance

OL

OL

8

0.4 0.4 0.4 V max I

0.4 0.4 0.4 V max I

15 15 15 pF max

= 1.6 mA, Pull-Up Resistor = 4.7 kΩ

SINK

= 2.6 mA, Pull-Up Resistor = 2 kΩ

SINK

CONVERSION TIME

External Clock 10 10 10 µs max
Internal Clock 10 10 10 µs max The Internal Clock Has a Nominal Value of 2.0 MHz

POWER REQUIREMENTS For Both DAC and ADC

V

DD

V

SS

I

DD

I

SS

+5 +5 +5 V nom ± 5% for Specified Performance
–5 –5 –5 V nom ±5% for Specified Performance
22 22 25 mA max Cumulative Current from the Two VDD Pins
12 12 13 mA max Cumulative Current from the Two VSS Pins

Total Power Dissipation 170 170 190 mW max Typically 130 mW

NOTES

1

Temperature ranges are as follows: A/B Versions, –40°C to +85 °C; T Version, –55 °C to +125°C.

2

VIN = ±3 V

3

SNR calculation includes distortion and noise components.

4

SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.

5

Measured with respect to internal reference.

6

For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section).

7

Tying the CONTROL input to VDD places the device in a factory test mode where normal operation is not exhibited.

8

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. B

DAC SECTION

AD7868

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, V
Load to AGND; RL = 2 kΩ, CL = 100 pF. All specifications T

MIN

to T

unless otherwise noted.)

MAX

OUT

Parameter Version1Version1Version1Units Test Conditions/Comments

ABT

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio3 (SNR) @ +25°C 70 72 70 dB min V

T

to T

MIN

Total Harmonic Distortion (THD) –78 –78 –76 dB max V

MAX

Peak Harmonic or Spurious Noise –78 –78 –76 dB max V

2

= 1 kHz Sine Wave, f

70 71 70 dB min Typically 71.5 dB at +25°C for 0 < V

OUT

= 1 kHz Sine Wave, f

OUT

Typically –84 dB at +25°C for 0 < V

= 1 kHz Sine Wave, f

OUT

Typically –84 dB at +25°C for 0 < V

SAMPLE

SAMPLE

SAMPLE

= 83 kHz

< 20 kHz

OUT

= 83 kHz

< 20 kHz

OUT

= 83 kHz

< 20 kHz

OUT

DC ACCURACY

Resolution 12 12 12 Bits
Integral Nonlinearity ±1/2 ±1/2 ±1/2 LSB typ
Integral Nonlinearity ± 1 ±1 LSB max
Differential Nonlinearity ± 0.9 ± 0.9 ± 0.9 LSB max Guaranteed Monotonic
Bipolar Zero Error ±5 ±5 ±5 LSB max
Positive Full-Scale Error
Negative Full-Scale Error

REFERENCE OUTPUT

5

5

6

± 5 ±5 ±5 LSB max
±5 ±5 ±5 LSB max

RO ADC @ +25°C 2.99/3.01 2.99/3.01 2.99/3.01 V min/V max
RO ADC TC ±25 ±25 ±25 ppm/°C typ
RO ADC TC ±40 ±50 ppm/°C max
Reference Load Change (∆RO DAC vs. ∆I) –1.5 –1.5 –1.5 mV max Reference Load Current Change (0–500 µA)

REFERENCE INPUT

RI DAC Input Range 2.85/3.15 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current 1 1 1 µA max

LOGIC INPUTS (LDAC, TFS, TCLK, DT)

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

IN

INL

IN

INH

7

2.4 2.4 2.4 V min VDD = 5 V ± 5%

0.8 0.8 0.8 V max VDD = 5 V ± 5%
±10 ±10 ±10 µA max VIN = 0 V to V
10 10 10 pF max

DD

ANALOG INPUT

Output Voltage Range ±3 ±3 ±3 V nom
dc Output Impedance 0.3 0.3 0.3 Ω typ
Short-Circuit Current 20 20 20 mA typ

AC CHARACTERISTICS

7

Voltage Output Settling-Time Settling Time to Within ± 1/2 LSB of Final Value

Positive Full-Scale Change 3 3 3 µs max Typically 2 µs

Negative Full-Scale Change 3 3 3 µs max Typically 2.5 µs
Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ DAC Code Change All 1s to All 0s
Digital Feedthrough 2 2 2 nV secs typ
VIN to V

Isolation 100 100 100 dB typ VIN = ±3 V, 41.5 kHz Sine Wave

OUT

POWER REQUIREMENTS As per ADC Section

NOTES

1

Temperature ranges are as follows: A/B Versions, –40°C to +85 °C; T Version, –55 °C to +125°C.

2

V

(pk–pk) = ±3 V.

OUT

3

SNR calculation includes distortion and noise components.

4

Using external sample and hold.

5

Measured with respect to RI DAC and includes bipolar offset error.

6

For capacitive loads greater than 50 pF a series resistor is required
(see INTERNAL REFERENCE section).

7

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

Model Range SNR (LSB) Option*

AD7868AN –40°C to +85°C 70 dB ±1/2 typ N-24

ORDERING GUIDE

Relative

Temperature Accuracy Package

AD7868AQ –40°C to +85°C 70 dB ± 1/2 typ Q-24
AD7868BN –40°C to +85°C 72 dB ± 1 max N-24
AD7868BQ –40°C to +85°C 72 dB ±1 max Q-24
AD7868AR –40°C to +85°C 70 dB ±1/2 typ R-28
AD7868BR –40°C to +85°C 72 dB ± 1 max R-28

*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).

4

4

4

REV. B

–3–

AD7868

WARNING!

ESD SENSITIVE DEVICE

RO ADC

DGND

TCLK

DT

RI DAC

AGND

CONTROL

CLK

RCLK

DR

DGND

AGND

RO DAC

NC

V

DD

NC = NO CONNECT

1

7

8
9

24
23

22
21

20

19
18
17

16

15

14

12

13

AD7868

TOP VIEW

(Not to Scale)

CONVST

RFS

V

SS

V

OUT

V

IN

TFS

LDAC

10

11

3

4
5

6

2

28
27

26
25

NC

NC

NC

NC

V

DD

V

SS

TIMING CHARACTERISTICS

1, 2

(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)

Limit at T

MIN

, T

MAX

Limit at T

MIN

, T

MAX

Parameter (A, B Versions) (T Version) Units Conditions/Comments

ADC TIMING

t

1

3

t

2

t

3

t

4

4

t

5

t

6

5

t

13

50 50 ns min CONVST Pulse Width
440 440 ns min RCLK Cycle Time, Internal Clock
100 100 ns min RFS to RCLK Falling Edge Setup Time
20 20 ns min RCLK Rising Edge to RFS
100 100 ns max
155 155 ns max RCLK to Valid Data Delay, CL = 35 pF
4 4 ns min Bus Relinquish Time after RCLK
100 100 ns max
2 RCLK +200 to 2 RCLK +200 to ns typ CONVST to RFS Delay
3 RCLK + 200 3 RCLK + 200

DAC TIMING

t

7

t

8

6

t

9

t

10

t

11

t

12

NOTES

1

Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.

2

Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 k Ω pull-up resistor on RCLK . The capacitance on all three output is 35 pF.

3

When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
external clock mark/space ratio.

4

DR will drive higher capacitance loads but this will add to t5 since it increases the external RC time constant (4.7 kΩ/CL) and hence the time to reach 2.4 V.

5

Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.

6

TCLK mark/space ratio is 40/60 to 60/40.

50 50 ns min TFS to TCLK Falling Edge
75 100 ns min TCLK Falling Edge to TFS
150 200 ns min TCLK Cycle Time
30 40 ns min Data Valid to TCLK Setup Time
75 100 ns min Data Valid to TCLK Hold Time
40 40 ns min LDAC Pulse Width

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

SS

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

V

OUT

VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V

RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V

RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V

RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V

Digital Inputs to AGND . . . . . . . . . . . –0.3 V to V

Digital Outputs to AGND . . . . . . . . . . –0.3 V to V

Operating Temperature Range

A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

+0.3 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

DD

–4–

CONVST

CLK

RFS

RCLK

DGND

V

AGND

V

OUT

V

RO DAC

RI DAC

1

2

3

4

5

DR

6

7

DD

8

9

SS

10

11

12

PIN CONFIGURATIONS

DIP

AD7868

TOP VIEW

(Not to Scale)

NC = NO CONNECT

24

23

22

21

20

19

18

17

16

15

14

13

CONTROL

V

DD

V

SS

V

IN

RO ADC

AGND

NC

DGND

TCLK

DT

TFS

LDAC

SOIC

REV. B

AD7868

PIN FUNCTION DESCRIPTION

DIP Pin
Number Mnemonic Function

POWER SUPPLY
7 & 23 V

10 & 22 V

DD
SS

8 & 19 AGND Analog Ground. Both AGND pins must be tied together.
6 &17 DGND Digital Ground. Both DGND pins must be tied together.

ANALOG SIGNAL AND REFERENCE
21 V

9V

IN
OUT

20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be

11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC

12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is

Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.

ADC Analog Input. The ADC input range is ± 3 V.
Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is

bipolar, ±3 V with RI DAC = +3 V.

used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of
this reference is 500 µA.

with this internal reference, RO DAC should be connected to RI DAC. The external load capability of
the reference is 500 µA.

internally buffered before being applied to the DAC. The nominal reference voltage for correct
operation of the AD7868 is 3 V.

ADC INTERFACE AND CONTROL
2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to

V

enables the internal laser-trimmed oscillator.

SS

3

RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides

a framing pulse for serial data. An external 4.7 kΩ pull-up resistor is required on

RFS.

4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal

or external ADC clock. If the CONTROL input is at V

the clock runs continuously. With the

SS

CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is
complete. RCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.

5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with

RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when

RFS and

RFS is

low. An external 4.7 kΩ resistor is required on the DR output.

1

CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into

the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input.

24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the

RCLK is continuous. Note, tying this pin to V

places the part in a factory test mode where normal

DD

operation is not exhibited.

DAC INTERFACE AND CONTROL
14

TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC

with serial data expected after the falling edge of this signal.

15 DT Transmit Data, Logic Input. This is the data input which is used in conjunction with

TFS and TCLK

to transfer serial data to the input latch.

16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when
13

LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the

TFS is low.

falling edge of this signal.

18 NC No Connect.

REV. B

–5–