Analog Devices AD7821 b Datasheet

LC2MOS High Speed, ␮P Compatible

a

FEATURES
Fast Conversion Time: 660 ns Max
100 kHz Track-and-Hold Function
1 MHz Sample Rate
Unipolar and Bipolar Input Ranges
Ratiometric Reference Inputs
No External Clock
Extended Temperature Range Operation
Skinny 20-Lead DlPs, SOIC, and 20-Terminal

Surface-Mount Packages

GENERAL DESCRIPTION

The AD7821 is a high speed, 8-bit, sampling, analog-to-digital
converter that offers improved performance over the popular
AD7820. It offers a conversion time of 660 ns (versus 1.36 µs
for the AD7820) and 100 kHz signal bandwidth (versus 6.4
kHz). The sampling instant is better defined and occurs on the
falling edge of WR or RD. The provision of a V
allows the part to operate from ±5 V supplies and to digitize
bipolar input signals. Alternatively, for unipolar inputs, the V
can be grounded and the AD7821 will operate from a single +5 V
supply, like the AD7820.

The AD7821 has a built-in track-and-hold function capable of
digitizing full-scale signals up to 100 kHz max. It also uses a
half-flash conversion technique that eliminates the need to gen­erate a CLK signal for the ADC.

The AD7821 is designed with standard microprocessor control
signals (CS, RD, WR, RDY, INT) and latched, three-state data
outputs capable of interfacing to high speed data buses. An
overflow output (OFL) is also provided for cascading devices to
achieve higher resolution.

The AD7821 is fabricated in Linear Compatible CMOS

2

(LC

MOS), an advanced, mixed technology process combining
precision bipolar circuits with low power CMOS logic. The part
features a low power dissipation of 50 mW.

pin (Pin 19)

SS

8-Bit ADC with Track/Hold Function

pin

SS

AD7821

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Fast Conversion Time
The half-flash conversion technique, coupled with fabrication
on Analog Devices’ LC
version time. The conversion time for the WR-RD mode is
660 ns, with 700 ns for the RD mode.

2. Built-In Track-and-Hold
This allows input signals with slew rates up to 1.6 V/µs to be
converted to 8 bits without an external track-and-hold. This
corresponds to a 5 V peak-to-peak, 100 kHz sine wave signal.

3. Total Unadjusted Error
The AD7821 features an excellent total unadjusted error figure
of less than ±1 LSB over the full operating temperature range.

4. Unipolar/Bipolar Input Ranges
The AD7821 is specified for single-supply (+5 V) operation
with a unipolar full-scale range of 0 to +5 V, and for dual-supply
(±5 V) operation with a bipolar input range of ±2.5 V. Typical
performance characteristics are given for other input ranges.

5. Dynamic Specifications for DSP Users
In addition to the traditional ADC specifications, the
AD7821 is specified for ac parameters, including signal-to­noise ratio, distortion, and slew rate.

2

MOS process, enables a very fast con-

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

VDD = +5 V ⴞ 5%, GND = 0 V. Unipolar Input Range: VSS = GND, V
V

AD7821–SPECIFICATIONS

V

(–) = –2.5 V. These test conditions apply unless otherwise stated. All specifications T

REF

(–) = GND. Bipolar Input Range: VSS = –5 V ⴞ 5%, V

REF

MIN

to T

unless otherwise noted. Specifications

MAX

(+) = 2.5 V,

REF

apply for RD Mode (Pin 7 = 0 V).

REF

REF

(–)/V

REF

(–)/V

1

B, T Versions Unit Comments

V

DD

(+) VSS/V

REF

(+) V

REF

REF

(–)/V

(+) V min/V max

REF

(–)/V

V min/V max

DD

(+) V min/ max

REF

fa (84.72 kHz) and fb (94.97 kHz) Full-Scale Sine Waves
with f

SOURCE

SINK

SINK

(V

REF

= 500 kHz

SAMPLING

= 360 µA

= 1.6 mA

= 2.6 mA

(+) = 4.75 V max for Unipolar Mode)

Parameter K Version

UNIPOLAR INPUT RANGE

Resolution
Total Unadjusted Error

2

3

88Bits
±1 ±1 LSB max

Minimum Resolution for which

No Missing Codes are Guaranteed 8 8 Bits

BIPOLAR INPUT RANGE

Resolution

2

88Bits

Zero Code Error ±1 ±1 LSB max
Full Scale Error ±1 ±1 LSB max
Signal-to-Noise Ratio (SNR)

3

45 45 dB min VIN = 99.85 kHz Full-Scale Sine Wave with f
Total Harmonic Distortion (THD)3–50 –50 dB max VIN = 99.85 kHz Full-Scale Sine Wave with f
Peak Harmonic or Spurious Noise3–50 –50 dB max VIN = 99.85 kHz Full-Scale Sine Wave with f
Intermodulation Distortion (IMD)

3

–50 –50 dB max Second Order Terms

Slew Rate, Tracking

3

–50 –50 dB max Third Order Terms

1.6 1.6 V/µs max

2.36 2.36 V/µs typ

REFERENCE INPUT

Input Resistance 1.0/4.0 1.0/4.0 kΩ min/kΩ max
V

(+) Input Voltage Range V

REF

V

(–) Input Voltage Range VSS/V

REF

ANALOG INPUT

Input Voltage Range V
Input Leakage Current ±3 ±3 µA max –5 V ≤ VIN ≤ +5 V
Input Capacitance 55 55 pF typ

LOGIC INPUTS

CS, WR, RD

V

INH

V

INL

I

(CS, RD)11µA max

INH

I

(WR)33µA max

INH

I

INL

Input Capacitance

4

2.4 2.4 V min

0.8 0.8 V max

–1 –1 µA max

88pF max Typically 5 pF
MODE

V

INH

V

INL

I

INH

I

INL

Input Capacitance

4

3.5 3.5 V min

1.5 1.5 V max

200 200 µA max 50 µA typ

–1 –1 µA max

88pF max Typically 5 pF

LOGIC OUTPUTS

DB0–DB7, OFL, INT

V

OH

V

OL

I

(DB0–DB7) ±3 ±3 µA max Floating State Leakage

OUT

Output Capacitance4 (DB0–DB7) 8 8 pF max Typically 5 pF

4.0 4.0 V min I

0.4 0.4 V max I

RDY

V

OL

I

OUT

Output Capacitance

POWER SUPPLY

5

I

DD

I

SS

Power Dissipation 50 50 mW typ

4

0.4 0.4 V max I

±3 ±3 µA max Floating State Leakage

88pF max Typically 5 pF

20 20 mA max CS = RD = 0 V

100 100 µA max CS = RD = 0 V

Power Supply Sensitivity ±1/4 ±1/4 LSB max ±1/16 LSB typ, VDD = 4.75 V to 5.25 V,

NOTES

1

Temperature Ranges are as follows: K Version = –40°C to +85°C; B Version = –40°C to +85°C; T Version = –55°C to +125°C.

2

1 LSB = 19.53 mV for both the unipolar (0 V to +5 V) and bipolar (–2.5 V to +2.5 V) input ranges.

3

See Terminology.

4

Sample tested at +25°C to ensure compliance.

5

See Typical Performance Characteristics.

Specifications subject to change without notice.

(+) = 5 V,

REF

SAMPLING

SAMPLING

SAMPLING

= 500 kHz
= 500 kHz
= 500 kHz

–2–

REV. B

AD7821

TIMING CHARACTERISTICS

1

(VDD = +5 V ⴞ 5%, VSS = 0 V or –5 V ⴞ 5%; Unipolar or Bipolar Input Range)

Limit at Limit at

Parameter (All Versions) (K, B Versions) (T Version) Unit Conditions/Comments

Limit at +25ⴗCT

t

CSS

t

CSH

t

RDY

t

CRD

t

ACC0

t

INTH

t

DH

t

P

t

WR

t

RD

t

READ1

t

ACC1

2

3

2

4

3

000ns min CS to RD/WR Setup Time
000ns min CS to RD/WR Hold Time
70 85 100 ns max CS to RDY Delay. Pull-Up

700 875 975 ns max Conversion Time (RD Mode)

t

+ 25 t

CRD

t

+ 50 t

CRD

50 – – ns typ RD to INT Delay (RD Mode)
80 85 90 ns max
15 15 15 ns min Data Hold Time
60 70 80 ns max
350 425 500 ns min Delay Time Between Conversions
250 325 400 ns min Write Pulsewidth
10 10 10 µs max
250 350 450 ns min Delay Time between WR and RD Pulses
160 205 240 ns min RD Pulsewidth (WR-RD Mode, see Figure 12b)

160 205 240 ns max CL = 20 pF

, T

MIN

MAX

+ 30 t

CRD

+ 65 t

CRD

T

, T

MIN

MAX

Resistor 5 kΩ

Data Access Time (RD Mode)

+ 35 ns max CL = 20 pF

CRD

+ 75 ns max CL = 100 pF

CRD

Determined by t
Data Access Time (WR-RD Mode, see Figure 12b)

ACC1

185 235 275 ns max CL = 100 pF

t

RI

t

INTL

t

READ2

t

ACC2

t

IHWR

t

ID

2

3

2

3

150 185 220 ns max RD to INT Delay
380 – – ns typ WR to INT Delay
500 610 700 ns max
65 75 85 ns min RD Pulsewidth (WR-RD Mode, see Figure 12a)

Determined by t
Data Access Time (WR-RD Mode, see Figure 12a)

ACC2

65 75 85 ns max CL = 20 pF
90 110 130 ns max CL = 100 pF
80 100 120 ns max WR to INT Delay (Stand-Alone Operation)

Data Access Time after INT
(Stand-Alone Operation)

30 35 40 ns max CL = 20 pF
45 60 70 ns max CL = 100 pF

NOTES

1

Sample tested at +25°C to ensure compliance. All input control signals are specified with t

2

CL = 50 pF.

3

Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

Specifications subject to change without notice.

RISE

= t

= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

FALL

Test Circuits

a. High Z to V

OH

Figure 1. Load Circuits for Data Access Time Test

a. VOH to High Z b. VOL to High Z

Figure 2. Load Circuits for Data Hold Time Test

REV. B

b. High Z to V

OL

ORDERING GUIDE

Total
Temperature Unadjusted Package
Range Error (LSB) Option

Model

1

AD7821KN –40°C to +85°C ±1 max N-20
AD7821KP –40°C to +85°C ± 1 max P-20A
AD7821KR –40°C to +85°C ± 1 max RW-20
AD7821BQ –40°C to +85°C ± 1 max Q-20
AD7821TQ –55°C to +125°C ±1 max Q-20
AD7821TE –55°C to +125°C ± 1 max E-20A

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.

2

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.

–3–

2

AD7821

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, + 7 V

V

SS

Digital Input Voltage to GND

(Pins 6–8, 13) . . . . . . . . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

DD

Digital Output Voltage to GND

(Pins 2–5, 9, 14–18) . . . . . . . . . . . . . . . –0.3 V, V

V

(+) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

REF

(–) to GND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

V

REF

to GND . . . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

V

IN

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Commercial (K Version) . . . . . . . . . . . . . . –40°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7821 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP AND SOIC LCCC PLCC

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1VINAnalog Input: Range V

(–) ≤ VIN ≤ V

REF

REF

(+)
2 DB0 Three-State Data Output (LSB)
3–5 DB1–DB3 Three-State Data Outputs
6 WR/RDY WRITE control input/READY status output. See Digital Interface section.
7 MODE Mode Selection Input. It determines whether the device operates in the WR-RD or RD mode. This input is internally

pulled low through a 50 µA current source. See Digital Interface section.

8 RD READ Input. RD must be low to access data from the part. See Digital Interface section.
9 INT INTERRUPT Output. INT going low indicates that the conversion is complete. INT returns high on the rising

edge of CS or RD. See Digital Interface section.

10 GND Ground
11 V

12 V

(–) Lower limit of reference span.

REF

(+) Upper limit of reference span.

REF

Range: V

Range: V

SS

REF

≤ V

REF

(–) < V

(–) ≤ V

(+) ≤ VDD.

REF

REF

(+).

13 CS Chip Select Input. The device is selected when this input is low.
14–16 DB4–DB6 Three-State Data Outputs
17 DB7 Three-State Data Output (MSB)
18 OFL Overflow Output. If the analog input is higher than (V

is a non-three-state output which can be used to cascade two or more devices to increase resolution.

19 V

20 V

SS

DD

Negative Supply Voltage
V

= 0 V; Unipolar Operation

SS

V

= –5 V; Bipolar Operation

SS

Positive Supply Voltage, +5 V

–4–

(+) – 1/2 LSB), OFL will be low at the end of conversion. It

REF

REV. B

AD7821

TERMINOLOGY
LEAST SIGNIFICANT BIT (LSB)

An ADC with 8-bit resolution can resolve one part in 28 (1/256
of full scale). For the AD7821 operating in either the unipolar
or bipolar input range with 5 V full scale, one LSB is 19.53 mV.

TOTAL UNADJUSTED ERROR

This is a comprehensive specification which includes relative
accuracy, offset error, and full-scale error.

SLEW RATE

Slew rate is the maximum allowable rate of change of input
signal such that the digital sample values are not in error.

TOTAL HARMONIC DISTORTION (THD)

Total harmonic distortion is the ratio of the square root of the
sum of the squares of the rms value of the harmonics to the rms
value of the fundamental. For the AD7821, total harmonic dis­tortion is defined as



VVVVV

++++

()

223242526



20

log






where V1 is the rms amplitude of the fundamental and V2, V3, V4,

, and V6 are the rms amplitudes of the individual harmonics.

V

5

V

1



2



dB






INTERMODULATION DISTORTION

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m+n), at sum and difference frequencies of
mfa+nfb, where m, n = 0, 1, 2, 3…. Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), and the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb). For the AD7821 intermodulation distortion is calcu­lated separately for both the second and third order terms.

SIGNAL-TO-NOISE RATIO (SNR)

Signal-to-noise ratio is measured signal-to-noise at the output of
the ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all nonfundamental signals (excluding
dc) up to half the sampling frequency. SNR is dependent on the
number of quantization levels used in the digitization process.
The theoretical SNR for a sine wave input is given by:

SNR N dB=+

where N is the number of bits in the ADC. Thus, for an ideal
8-bit ADC, SNR = 50 dB.

PEAK HARMONIC OR SPURIOUS NOISE

Peak harmonic or spurious noise is the rms value of the largest
nonfundamental frequency (excluding dc) up to half the sam­pling frequency to the rms value of the fundamental.

602 176..

()

REV. B

–5–