Analog Devices AD7738 Datasheet

8-Channel, High Throughput,

SCLK

DIN

DOUT

CS

RDY

RESET

SERIAL

INTERFACE

CONTROL

LOGIC

AIN4

AIN5

AIN6

AIN7

MUX

AINCOM/P0

AIN0

AIN1

AIN2

AIN3

DGND DV

DD

REFERENCE

DETECT

REFIN– REFIN+

I/O PORT

SYNC/P1

CLOCK

GENERATOR

MCLKINMCLKOUT

MUXOUT ADCIN

AGND AV

DD

24-BIT

- ADC

BUFFER

AD7738

CALIBRATION

CIRCUITRY

a

FEATURES
High Resolution ADC

24 Bits No Missing Codes
0.0015% Nonlinearity

Optimized for Fast Channel Switching

18-Bits p-p Resolution (21 Bits Effective) at 500 Hz
16-Bits p-p Resolution (19 Bits Effective) at 8.5 kHz
15-Bits p-p Resolution (18 Bits Effective) at 15 kHz
On-Chip Per Channel System Calibration

Configurable Inputs

8 Single-Ended or 4 Fully Differential

Input Ranges

+625 mV, +1.25 V, +2.5 V, 625 mV, 1.25 V, 2.5 V

3-Wire Serial Interface

SPI™, QSPI™, MICROWIRE™ and DSP Compatible
Schmitt Trigger on Logic Inputs

Single-Supply Operation

5 V Analog Supply
3 V or 5 V Digital Supply

Package: 28-Lead TSSOP

24-Bit - ADC

AD7738

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS
PLCs/DCS
Multiplexing Applications
Process Control
Industrial Instrumentation

GENERAL DESCRIPTION

The AD7738 is a high precision, high throughput analog front
end. True 16-bit p-p resolution is achievable with a total con­version time of 117 µs (8.5 kHz channel switching), making it
ideally suitable for high resolution multiplexing applications.

The part can be configured via a simple digital interface, which
allows users to balance the noise performance against data
throughput up to a 15.4 kHz.

The analog front end features eight single-ended or four fully
differential input channels with unipolar or bipolar 625 mV,

1.25 V, and 2.5 V input ranges and accepts a common-mode
input voltage from 200 mV above AGND to AVDD – 300 mV.
The multiplexer output is pinned out externally, allowing the
user to implement programmable gain or signal conditioning
before applying the input to the ADC.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

The differential reference input features “No-Reference” detect
capability. The ADC also supports per channel system calibra­tion options.

The digital serial interface can be configured for 3-wire opera­tion and is compatible with microcontrollers and digital signal
processors. All interface inputs are Schmitt triggered.

The part is specified for operation over the extended industrial
temperature range of –40C to +105C.

Other parts in the AD7738 family are the AD7734 and the
AD7732.

The AD7734 analog front end features four single-ended input
channels with unipolar or true bipolar input ranges to ±10 V
while operating from a single 5 V analog supply. The AD7734
accepts an analog input overvoltage to ±16.5 V while not
degrading the performance of the adjacent channels.

The AD7732 is similar to AD7734, but its analog front end
features two fully differential input channels.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD7738–SPECIFICATIONS

(–40ⴗC to +105ⴗC, AVDD = 5 V ⴞ 5%, DVDD = 2.7 V to 3.6 V or 5 V ⴞ 5%,

REFIN(+) = 2.5 V, REFIN(–) = 0 V, AINCOM = 2.5 V, MUXOUT(+) = ADCIN(+), MUXOUT(–) = ADCIN(–), Internal Buffer ON, AIN Range = ⴞ1.25 V,
f

= 6.144 MHz; unless otherwise noted.)

MCLK

Parameter Min Typ Max Unit Test Conditions/Comment

ADC PERFORMANCE—
CHOPPING ENABLED

Conversion Time Rate 372 12190 Hz Configure via Conversion Time Register
No Missing Codes

1

24 Bits FW ≥ 6 (Conversion Time ≥ 165 µs)

See Typical Performance Characteristics
Output Noise See Table I
Resolution See Tables II and III
Integral Nonlinearity (INL) ± 0.0015 % of FSR AIN Range = ± 2.5 V

Offset Error (Unipolar, Bipolar)
Offset Drift vs. Temperature
Gain Error

2

Gain Drift vs. Temperature
Positive Full-Scale Error
Positive Full-Scale Drift vs. Temperature
Bipolar Negative Full-Scale Error

2

1

1

2

1

3

± 0.0015 % of FSR AIN Range = ± 1.25 V
± 10 µV Before Calibration

± 280 nV/°C
± 0.2 % Before Calibration
± 2.5 ppm of FS/ⴗC
± 0.2 % of FSR Before Calibration
± 2.5 ppm of FS/ⴗC

± 0.0030 % of FSR After Calibration

3

Common-Mode Rejection 80 100 dB At DC, AIN = 1 V
Power Supply Rejection 70 80 dB At DC, AIN = 1 V

ADC PERFORMANCE—
CHOPPING DISABLED

Conversion Time Rate 737 15437 Hz Configure via Conversion Time Register
No Missing Codes

1

24 Bits FW ≥ 8 (Conversion Time ≥ 117 µs)

See Typical Perfomance Charateristics
Output Noise See Table IV
Resolution See Tables V and VI
Integral Nonlinearity (INL) ± 0.0015 % of FSR
Offset Error (Unipolar, Bipolar)
Offset Drift vs. Temperature ± 1.5 µV/ⴗC
Gain Error

2

Gain Drift vs. Temperature ± 2.5 ppm of FS/ⴗC
Positive Full-Scale Error
Positive Full-Scale Drift vs. Temperature ± 2.5 ppm of FS/ⴗC
Bipolar Negative Full-Scale Error

4

± 1mVBefore Calibration

± 0.2 % Before Calibration

2

3

± 0.2 % of FSR Before Calibration

± 0.0030 % of FSR After Calibration

3

Common-Mode Rejection 75 dB At DC, AIN = 1 V
Power Supply Rejection 65 dB At DC, AIN = 1 V

ANALOG INPUTS

Analog Input Voltage Ranges

1, 5

± 2.5 V Range –2.9 ± 2.5 +2.9 V
+2.5 V Range 0 0 to 2.5 2.9 V
± 1.25 V Range –1.45 ± 1.25 +1.45 V
+1.25 V Range 0 0 to 1.25 1.45 V
± 0.625 V Range –725 ±625 +725 mV

+0.625 V Range 0 0 to 625 725 mV
AIN, AINCOM Common-Mode Voltage
AIN, AINCOM Input Current

6

AIN to MUXOUT On Resistance

REFERENCE INPUT

REFIN(+) to REFIN(–) Voltage

1, 7

1

0.2 AV

1

200 Ω

– 0.3 V

DD

200 nA Only One Channel, Chop Disabled

2.475 2.5 2.525 V
NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register
REFIN(+), REFIN(–)

Common-Mode Voltage

Reference Input Current

SYSTEM CALIBRATION

1, 9

1

8

0AV

DD

V

400 µA

Full Scale Calibration Limit +1.05 ⫻ FS V
Zero Scale Calibration Limit –1.05 ⫻ FS V
Input Span 0.8 ⫻ FS 2.1 ⫻ FS V

REV. 0–2–

AD7738

Parameter Min Typ Max Unit Test Conditions/Comment

LOGIC INPUTS

SCLK, DIN, CS, and RESET Inputs

Input Current ± 1 µA
Input Current CS ± 10 µA CS = AV

–40 µA Internal Pull-Up Resistor

Input Capacitance 4 pF

1

V

T+

1

V

T–

V

T+

V

T+

V

T–

V

T+

– V

1

1

– V

1

T–

1

T–

1.4 2 V DVDD = 5 V

0.8 1.4 V DVDD = 5 V

0.3 0.85 V DVDD = 5 V

0.95 2 V DVDD = 3 V

0.4 1.1 V DVDD = 3 V

0.3 0.85 V DVDD = 3 V

MCLK IN Only

Input Current ± 10 µA
Input Capacitance 4 pF

Input Low Voltage 0.8 V DVDD = 5 V

V

INL

Input High Voltage 3.5 V DVDD = 5 V

V

INH

Input Low Voltage 0.4 V DVDD = 3 V

V

INL

V

Input High Voltage 2.5 V DVDD = 3 V

INH

LOGIC OUTPUTS

MCLKOUT

V

OL

V

OH

V

OL

V

OH

10

, DOUT, RDY

Output Low Voltage 0.4 V I

Output High Voltage 4.0 V I

Output Low Voltage 0.4 V I

Output High Voltage DVDD – 0.6 V I

SINK

SOURCE

SINK

SOURCE

Floating State Leakage Current ± 1 µA
Floating State Leakage Capacitance 3 pF

P1 INPUT Levels Referenced to Analog Supplies

Input Current ± 10 µA
V

Input Low Voltage 0.8 V AVDD = 5 V

INL

V

Input High Voltage 3.5 V AVDD = 5 V

INH

P0, P1 OUTPUT

Output Low Voltage 0.4 V

V

OL

0.4 V

0.4 V I

VOH Output High Voltage 4.0 V I

I

SINK

I

SINK

SINK

SOURCE

POWER REQUIREMENTS

– AGND Voltage 4.75 5.25 V

AV

DD

DV

– DGND Voltage 4.75 5.25 V

DD

2.70 3.60 V

Current (Normal Mode) 13.6 16 mA AVDD = 5 V

AV

DD

Current (Internal Buffer Off ) 8.5 mA AVDD = 5 V

AV

DD

Current (Normal Mode)

DV

DD

Current (Normal Mode)

DV

DD

AV

+ DVDD Current (Standby Mode)

DD

Power Dissipation (Normal Mode)
Power Dissipation (Standby Mode)

NOTES

1

Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.

2

Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.

3

Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.

4

Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.

5

The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit descr iption for more details.

6

If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplex er, capacitance of the pins,

and any additional capacitance connected to the MUXOUT. See the circuit description for more details.

7

For specified performance. Part is functional with Lower V

8

Dynamic current charging the sigma-delta modulator input switching capacitor.

9

Outside the specified calibration range, calibration is possible but the performance may degrade.

10

These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.

11

With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register).

12

External MCLKIN = 0 V or DVDD, Digital Inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.

Specifications are subject to change without notice.

REV. 0

11

11

12

11

12

REF

2.7 3 mA DVDD = 5 V

1.0 1.5 mA DVDD = 3 V
80 µAAV
85 100 mW
500 µWAV

–3–

DD

= 800 µA, DVDD = 5 V

= 200 µA, DVDD = 5 V

= 100 µA, DVDD = 3 V

= 100 µA, DVDD = 3 V

= 8 mA, T
= 5 mA, T

= 2.5 mA, T

= 70°C, AVDD = 5 V

MAX

= 85°C, AVDD = 5 V

MAX

= 105°C, AVDD = 5 V

MAX

= 200 µA, AVDD = 5 V

= DVDD = 5 V

DD

= DVDD = 5 V

DD

AD7738

TIMING SPECIFICATIONS

1, 2, 3

(AVDD = 5 V  5%; DVDD = 2.7 V to 3.6 V or 5 V  5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comment

MASTER CLOCK RANGE 1 6.144 MHz

t

1

t

2

50 ns SYNC Pulsewidth
500 ns RESET Pulsewidth

READ OPERATION

t

4

4

t

5

4, 5

t

5A

t

6

t

7

t

8

6

t

9

0nsCS Falling Edge to SCLK Falling Edge Setup Time

SCLK Falling Edge to Data Valid Delay
060nsDV
080nsDV

of 4.75 V to 5.25 V

DD

of 2.7 V to 3.3 V

DD

CS Falling Edge to Data Valid Delay
060nsDV
080nsDV

of 4.75 V to 5.25 V

DD

of 2.7 V to 3.3 V

DD

50 ns SCLK High Pulsewidth
50 ns SCLK Low Pulsewidth
0nsCS Rising Edge after SCLK Rising Edge Hold Time

10 80 ns Bus Relinquish Time after SCLK Rising Edge

WRITE OPERATION

t

11

t

12

t

13

t

14

t

15

t

16

NOTES

1

Sample tested during initial release to ensure compliance.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

3

See Figures 1 and 2.

4

These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits.

5

This specification is relevant only if CS goes low while SCLK is low.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

0nsCS Falling Edge to SCLK Falling Edge Setup
30 ns Data Valid to SCLK Rising Edge Setup Time
25 ns Data Valid after SCLK Rising Edge Hold Time
50 ns SCLK High Pulsewidth
50 ns SCLK Low Pulsewidth
0nsCS Rising Edge after SCLK Rising Edge Hold Time

Specifications are subject to change without notice.

REV. 0–4–

CS

t

4

SCLK

t

5

t

5A

DOUT MSB

Figure 1. Read Cycle Timing Diagram

CS

t

11

SCLK

t

12

DIN

MSB

AD7738

LSB

LSB

t

8

t

9

t

16

t

6

t

7

t

14

t

15

t

13

Figure 2. Write Cycle Timing Diagram

I

OUTPUT

PIN

(800A AT DV

SINK

100A AT DV

TO

50pF

I

( 200A AT DVDD = 5V

SOURCE

100A AT DV

1.6V

DD

DD

= 5V
= 3V)

DD

= 3V)

Figure 3. Load Circuit for Access Time and Bus Relinquish Time

REV. 0

–5–

AD7738

SCLK

DIN

DOUT

CS

RDY

RESET

SERIAL

INTERFACE

CONTROL

LOGIC

AIN4

AIN5

AIN6

AIN7

MUX

AINCOM/P0

AIN0

AIN1

AIN2

AIN3

DGND DV

DD

REFERENCE

DETECT

REFIN– REFIN+

I/O PORT

SYNC/P1

CLOCK

GENERATOR

MCLKINMCLKOUT

MUXOUT ADCIN

AGND AV

DD

24-BIT

- ADC

BUFFER

AD7738

CALIBRATION

CIRCUITRY

DV

DD

AV

DD

ABSOLUTE MAXIMUM RATINGS*

(TA = 25C unless otherwise noted.)

AVDD to AGND, DVDD to DGND . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V

AV

DD

AIN, AINCOM to AGND . . . . . . . . . –0.3 V to AV

REFIN(+), REFIN(–) to AGND . . . . . –0.3 V to AV

MUXOUT(+) to AGND . . . . . . . . . . . –0.3 V to AV

MUXOUT(–) to AGND . . . . . . . . . . . –0.3 V to AV

ADCIN(+), ADCIN(–) to AGND . . . . –0.3 V to AV

P1 Voltage to AGND . . . . . . . . . . . . . . –0.3 V to AV

Digital Input Voltage to DGND . . . . . –0.3 V to AV

Digital Output Voltage to DGND . . . . –0.3 V to AV

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range . . . . . . . . . . –40C to +105C

Storage Temperature Range . . . . . . . . . . . . –65C to +150C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 660 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9C/W

␪

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

AD7738BRU –40C to +105CTSSOP 28 RU-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7738 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

Figure 4. Block Diagram

REV. 0–6–

PIN CONFIGURATION

AD7738

SCLK

MCLKIN

MCLKOUT

CS

RESET

AV

AINCOM/P0

SYNC/P1

AIN7

AIN6

AIN5

AIN4

MUXOUT(+)

MUXOUT(–)

DD

1

2

3

4

5

6

AD7738

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

DGND

27

DV

26

DIN

25

DOUT

24

RDY

23

AGND

22

REFIN(–)

21

REFIN(+)

20

AIN0

19

AIN1

18

AIN2

17

AIN3

16

ADCIN(+)

15

ADCIN(–)

DD

PIN FUNCTION DESCRIPTION

Pin No. Mnemonic Description

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer

serial data to or from the AD7738.

2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external

clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN
pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected.

3MCLKOUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between

MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an
inverted clock signal or can be switched off to lower the device power consumption. MCLKOUT is
capable of driving one CMOS load.

4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input

hardwired low, the AD7738 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS
can be used to select the device in systems with more than one device on the serial bus. It can also be used as
an 8-bit frame synchronization signal.

5 RESET Schmitt-Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter,

analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the
part except the clock oscillator is reset when the RESET pin is exercised.

6AV

DD

Analog Positive Supply Voltage. 5 V to AGND nominal.

7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The pin is determined by the P0 Dir bit; the digital

value can be written as the P0 bit in the I/O Port register. The digital voltage is referenced to analog
supplies. When configured as an input (P0 Dir bit set to 1), the single-ended Analog Inputs 0 to 7 can be
referenced to this pin’s voltage level.

8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 Dir bit; the digital value

can be read/written as the P1 bit in the I/O Port register. When the SYNC Enable bit in the I/O Port
register is set to 1, the SYNC/P1 pin can be used to synchronize the AD7738 modulator and digital filter
with other devices in the system. The digital voltage is referenced to the analog supplies. When configured
as an input, the pin should be tied high or low.

9–12, AIN0–AIN7 Analog Inputs
17–20

13 MUXOUT(+) Analog Multiplexer Positive Output

14 MUXOUT(–) Analog Multiplexer Negative Output

REV. 0

–7–

AD7738

PIN FUNCTION DESCRIPTION (continued)

Pin No. Mnemonic Pin Description

15 ADCIN(–) ADC Negative Input. In normal circuit configuration, this pin should be connected to the MUXOUT– pin.

16 ADCIN(+) ADC Positive Input. In normal circuit configuration, this pin should be connected to the MUXOUT+ pin.

21 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN+ voltage potential can lie any where between

AV

and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage.

DD

22 REFIN(–) Negative Terminal of the Differential Reference Input. REFIN– voltage potential can lie any where between

AV

and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage.

DD

23 AGND Ground Reference Point for Analog Circuitry
24 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion

mode, a falling edge on this output indicates that either any channel or all channels have unread data
available—according to the RDY function bit in the I/O Port register. In calibration mode, a falling edge
on this output indicates that calibration is complete. See more details in Digital Interface Description
section later in this data sheet.

25 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output

shift register can contain information from any AD7738 register depending on the address bits of the
Communications register.

26 DIN Serial Data Input (Schmitt triggered) with serial data being written to the input shift register on the part.

Data from this input shift register is transferred to any AD7738 register depending on the address bits of
the Communications register.

27 DV

DD

28 DGND Ground Reference Point for Digital Circuitry

Digital Supply Voltage, 3 V or 5 V Nominal

REV. 0–8–

AD7738

OUTPUT NOISE AND RESOLUTION SPECIFICATION

The AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the
throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of
operation are outlined below for a selection of output rates and settling times.

CHOPPING ENABLED

The first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower
output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output
data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms
noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a
six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise.

These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage
set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register.

Table I. Typical Output RMS Noise in V vs. Conversion Time and Input Range with
Chopping Enabled

Conversion Conversion Output –3 dB
Time Time Data Rate Frequency

FW Register (s) (Hz) (Hz) 2.5 V, +2.5 V 1.25 V, +1.25 V, 625 mV, +625 mV

127 FFh 2686 372 194 1.8 1.1
46 AEh 999 1001 521 3.0 1.8
17 91h 395 2534 1317 5.1 3.0
8 88h 207 4826 2510 8.1 4.5
4 84h 124 8074 4198 9.3 5.3
2 82h 82 12166 6326 17.0 10.6

Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with
Chopping Enabled

Conversion Conversion Output –3 dB
Time Time Data Rate Frequency

FW Register (s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV

127 FFh 2686 372 194 21.4 20.4 21.1 20.1 20.1 19.1
46 AEh 999 1001 521 20.6 19.6 20.4 19.4 19.4 18.4
17 91h 395 2534 1317 19.9 18.9 19.6 18.6 18.6 17.6
8 88h 207 4826 2510 19.2 18.2 19.0 18.0 18.0 17.0
4 84h 124 8074 4198 19.0 18.0 18.8 17.8 17.8 16.8
2 82h 82 12166 6326 18.1 17.1 17.8 16.8 16.8 15.8

Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with
Chopping Enabled

Input Range

Input Range

Conversion Conversion Output –3 dB
Time Time Data Rate Frequency

FW Register (s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV

127 FFh 2686 372 194 18.4 17.4 18.2 17.2 17.2 16.2
46 AEh 999 1001 521 17.8 16.8 17.5 16.5 16.5 15.5
17 91h 395 2534 1317 16.8 15.8 16.7 15.7 15.7 14.7
8 88h 207 4826 2510 16.5 15.5 16.2 15.2 15.2 14.2
4 84h 124 8074 4198 16.0 15.0 16.0 15.0 15.0 14.0
2 82h 82 12166 6326 15.0 14.0 15.0 14.0 14.0 13.0

REV. 0

–9–

Input Range