Analog Devices AD7731EB, AD7731BRU, AD7731BR, AD7731BN Datasheet

Low Noise, High Throughput

FEATURES 24-Bit Sigma-Delta ADC 16 Bits p-p Resolution at 800 Hz Output Rate Programmable Output Rates up to 6.4 kHz Programmable Gain Front End

60.0015% Nonlinearity Buffered Differential Inputs Programmable Filter Cutoffs

FAST

Step™* Mode for Channel Sequencing

Single Supply Operation APPLICATIONS

Process Control PLCs/DCS Industrial Instrumentation

24-Bit Sigma-Delta ADC

AD7731

GENERAL DESCRIPTION

The AD7731 is a complete analog front-end for process control applications. The device has a proprietary programmable gain front end that allows it to accept a range of input signal ranges, including low level signals, directly from a transducer. The sigmadelta architecture of the part consists of an analog modulator and a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time.

The part features three buffered differential programmable gain analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part operates from a single +5 V supply and accepts seven unipolar analog input ranges: 0 to +20 mV, +40 mV, +80 mV, +160mV, +320 mV, +640 mV and +1.28 V, and seven bipolar ranges:

±20 mV, ±40 mV, ± 80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V. The peak-to-peak resolution achievable directly from

the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a performance level of 13 bits of peak-to-peak resolution.

The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2ppm/°C.

The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

NC AIN1 AIN2 AIN3 AIN4 AIN5 AIN6

*FASTStep is a trademark of Analog Devices, Inc.

100nA

MUX

100nA

AGND

BUFFER

REF IN(–)

DGNDAGND

REF IN(+)

PGA

SERIAL INTERFACE

AND CONTROL LOGIC

MICROCONTROLLER

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

AD7731

SIGMA-DELTA A/D CONVERTER

SIGMA-

DELTA

MODULATOR

CALIBRATION

POL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997

PROGRAMMABLE

RDY

DIGITAL

FILTER

CLOCK

GENERATION

RESET

STANDBY

SYNC

MCLK IN MCLK OUT

SCLK

DIN DOUT

(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = +2.5 V; REFIN(–) = AGND; AGND =

AD7731–SPECIFICA TIONS

Parameter B Version

STATIC PERFORMANCE (CHP = 0)

No Missing Codes Output Noise and Update Rates Integral Nonlinearity 15 ppm of FSR max Offset Error Offset Drift vs. Temperature

Offset Drift vs. Time Positive Full-Scale Error Positive Full-Scale Drift vs. Temp

Positive Full-Scale Drift vs. Time Gain Error Gain Drift vs. Temperature Gain Drift vs. Time Bipolar Negative Full-Scale Error Negative Full-Scale Drift vs. Temp Power Supply Rejection Power Supply Rejection Common-Mode Rejection (CMR)

2, 9

2, 6

2, 7, 8

2, 7, 10

2, 7 11 11

24 Bits min SKIP = 0 See Tables I and II

See Note 4 Offset Error and Offset Drift Refer to Both

0.5 µV/°C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV 1/2/5 µV/°C typ Input Range = 320 mV/640 mV/1.28 V

2.5 µV/1000 Hr See Note 4

0.6 µV/°C typ Input Range = 20 mV, 40 mV, 80 mV, 160 mV

1.5/3/6 µV/°C typ Input Range = 320 mV/640 mV/1.28 V 3 µV/1000 Hr See Note 4 2 ppm/°C typ 10 ppm/1000 Hr See Note 4 1 µV/°C typ 90 dB typ Input Range = 20 mV 60 dB typ Input Range = 1.28 V

DGND = 0 V; f

On AIN 95 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V

On REF IN 120 dB typ Analog Input DC Bias Current Analog Input DC Bias Current Drift Analog Input DC Offset Current

60 nA max 150 pA/°C typ 30 nA max

Analog Input DC Offset Current Drift2100 pA/°C typ

STATIC PERFORMANCE (CHP = 1)

No Missing Codes 24 Bits min Output Noise and Update Rates See Tables III and IV Integral Nonlinearity 15 ppm of FSR max Offset Error See Note 4 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature 5 nV/°C typ Unipolar Offset and Bipolar Zero Errors Offset Drift vs. Time Positive Full-Scale Error Positive Full-Scale Drift vs. Temp Positive Full-Scale Drift vs. Time Gain Error

Gain Drift vs. Temperature Gain Drift vs. Time

7, 8

7, 10

25 nV/1000 Hr typ See Note 4 2 ppm of FS/°C max 10 ppm of FS/1000 Hr See Note 4 2 ppm/°C max

10 ppm/1000 Hr Bipolar Negative Full-Scale Error See Note 4 Negative Full-Scale Drift vs. Temp 2 ppm of FS/°C max Power Supply Rejection Power Supply Rejection Common-Mode Rejection (CMR)

11 11

110 dB typ Input Range = 20 mV

85 dB typ Input Range = 1.28 V

On AIN 110 dB typ At DC. Input Range = 20 mV On AIN 85 dB typ At DC. Input Range = 1.28 V

On REF IN 120 dB typ Analog Input DC Bias Current 50 nA max Analog Input DC Bias Current Drift 100 pA/°C typ Analog Input DC Offset Current 10 nA max Analog Input DC Offset Current Drift 50 pA/°C typ

= 4.9152 MHz. All specifications T

CLK IN

MIN

to T

Units Conditions/Comments

unless otherwise noted.)

MAX

ANALOG INPUTS/REFERENCE INPUTS

Normal Mode 50 Hz/60 Hz Rejection Common-Mode 50 Hz/60 Hz Rejection Analog Inputs

Differential Input Voltage Ranges

88 dB min 50 Hz/60 Hz ±1 Hz. SKIP = 0 120 dB min 50 Hz/60 Hz ±1 Hz. SKIP = 0

Assuming 2.5 V or 5 V Reference with HIREF

Bit Set Appropriately 0 to +20 or ±20 mV nom RN2, RN1, RN0 of Mode Register = 0, 0, 1 0 to +40 or ±40 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 0 0 to +80 or ±80 mV nom RN2, RN1, RN0 of Mode Register = 0, 1, 1 0 to +160 or ±160 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 0 0 to +320 or ±320 mV nom RN2, RN1, RN0 of Mode Register = 1, 0, 1 0 to +640 or ±640 mV nom RN2, RN1, RN0 of Mode Register = 1, 1, 0 0 to +1.28 or ±1.28 V nom RN2, RN1, RN0 of Mode Register = 1, 1, 1

–2–

REV. 0

AD7731

Parameter B Version

Absolute/Common-Mode Voltage

AGND + 1.2 V V min AV

– 0.95 V V max

Units Conditions/Comments

Reference Input

REF IN(+) – REF IN (–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0 REF IN(+) – REF IN (–) Voltage +5 V nom HIREF Bit of Mode Register = 1 Reference DC Input Current 5.5 µA max HIREF Bit of Mode Register = 0 Reference DC Input Current 10 µA max HIREF Bit of Mode Register = 1 Absolute/Common-Mode Voltage

AGND – 30 mV V min

+ 30 mV V max

NO REF Trigger Voltage 0.3 V min NO REF Bit Active If VREF Below This Voltage

0.65 V max NO REF Bit Inactive If VREF Above This Voltage

LOGIC INPUTS

Input Current ±10 µA max All Inputs Except SCLK and MCLK IN

, Input Low Voltage 0.8 V max DVDD = +5 V

INL

, Input Low Voltage 0.4 V max DVDD = +3 V

INL

, Input High Voltage 2.0 V min

INH

SCLK Only (Schmitt Triggered Input)

T+

T–

– V

T+

T–

– V

T+

T–

1.4/3 V min/V max DVDD = +5 V

0.95/2.5 V min/V max DVDD = +3 V

0.8/1.4 V min/V max DVDD = +5 V

0.4/1.1 V min/V max DVDD = +3 V

0.4/0.85 V min/V max DVDD = +5 V

0.4/0.8 V min/V max DVDD = +3 V

MCLK IN Only

, Input Low Voltage 0.8 V max DVDD = +5 V

INL

, Input Low Voltage 0.4 V max DVDD = +3 V

INL

, Input High Voltage 3.5 V min DVDD = +5 V

INH

, Input High Voltage 2.5 V min DVDD = +3 V

INH

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage 0.4 V max I

, Output High Voltage 4.0 V min I

, Output High Voltage DVDD – 0.6 V V min I

Floating State Leakage Current ±10 µA max Floating State Output Capacitance

TRANSDUCER BURNOUT

6 pF typ

= 800 µA Except for MCLK OUT15.

SINK

= +5 V

= 100 µA Except for MCLK OUT15.

SINK

= +3 V

= 200 µA Except for MCLK OUT15.

SOURCE

= +5 V

= 100 µA Except for MCLK OUT15.

SOURCE

= +3 V

AIN1(+) Current –100 nA nom AIN1(–) Current 100 nA nom Initial Tolerance @ 25°C ±10 % typ Drift 0.1 %/°C typ

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit Negative Full-Scale Calibration Limit

Offset Calibration Limit Input Span

1.05 × FS V max FS Is the Nominal Full-Scale Voltage (20 mV,

–1.05 × FS V max

40 mV, 80 mV, 160 mV, 320 mV, 640 mV, 1.28 V)

–1.05 × FS V min

0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS

Power Supply Voltages

– AGND Voltage +5 V nom

Voltage +2.7 to +5.25 V min to V max With AGND = 0 V

Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV

AVDD Current (Normal Mode) 10.3 mA max

Current (Normal Mode) 1.7 mA max DVDD of 2.7 V to 3.3 V

Current (Normal Mode) 3.2 mA max DVDD of 4.75 V to 5.25 V

+ DVDD Current (Standby Mode) 25 µA max Typically 10 µA. External MCLK IN = 0 V or DV

Power Dissipation AV

= DV

= +5 V. Digital I/Ps = 0 V or DV

Normal Mode 67.5 mW max Standby Mode 125 µW max Typically 50µW. External MCLK IN = 0 V or DV

–3–REV. 0

AD7731

NOTES

Temperature Range: –40°C to +85°C.

Sample tested during initial release.

No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits.

The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. Offset numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40mV range, an internal full-scale calibration should be performed on the 80 mV input range with a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can be calculated from the offset and gain errors.

These numbers are generated during life testing of the part.

Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.

Recalibration at any temperature will remove these errors.

Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are positive full-scale and negative full-scale. See Terminology.

Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.

Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs) between these values for the other input ranges.

The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input.

The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.

These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

VDD refers to DVDD for all logic outputs expect D0 and D1 where it refers to AVDD. In other words, the output logic high for these two outputs is determined by AVDD.

See Burnout Current section.

After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

Specifications subject to change without notice.

(AVDD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V;

1, 2

TIMING CHARACTERISTICS

Limit at T

Parameter (B Version) Units Conditions/Comments

Master Clock Range 1 MHz min For Specified Performance

5 MHz max

50 ns min SYNC Pulse Width 50 ns min RESET Pulse Width

Read Operation

0 ns min RDY to CS Setup Time 0 ns min CS Falling Edge to SCLK Active Edge Setup Time 0 ns min SCLK Active Edge to Data Valid Delay 60 ns max DVDD = +4.75 V to +5.25 V

4, 5

80 ns max DV 0 ns min CS Falling Edge to Data Valid Delay 60 ns max DVDD = +4.75 V to +5.25 V 80 ns max DV

100 ns min SCLK High Pulse Width 100 ns min SCLK Low Pulse Width 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time 10 ns min Bus Relinquish Time after SCLK Inactive Edge 80 ns max

100 ns max SCLK Active Edge to RDY High

Write Operation

NOTES

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

See Figures 15 and 16.

SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V

This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to DSP machines.

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update.

0 ns min CS Falling Edge to SCLK Active Edge Setup Time 30 ns min Data Valid to SCLK Edge Setup Time 25 ns min Data Valid to SCLK Edge Hold Time 100 ns min SCLK High Pulse Width 100 ns min SCLK Low Pulse Width 0 ns min CS Rising Edge to SCLK Edge Hold Time

MIN

= 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted)

CLK IN

, T

MAX

= +2.7 V to +3.3 V

or VOH limits.

–4–

3, 7

REV. 0

AD7731

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5 V to +0.3 V

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V

Analog Input Voltage to AGND . . . . –0.3 V to AV

Reference Input Voltage to AGND . . –0.3 V to AV

DD DD

+ 0.3 V

AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV Output Voltage (D0, D1) to DGND . . –0.3 V to AV

+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

ORDERING GUIDE

Model Temperature Range Package Description Package Options

AD7731BN –40°C to +85°C Plastic DIP N-24 AD7731BR –40°C to +85°C Small Outline R-24 AD7731BRU –40°C to +85°C Thin Shrink Small Outline (TSSOP) RU-24 EVAL-AD7731EB Evaluation Board

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TO OUTPUT

50pF

(800µA AT DV

SINK

100µA AT DV

(200µA AT DVDD = +5V

SOURCE

100µA AT DV

+1.6V

DD DD

= +5V = +3V)

= +3V)

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7731 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. 0

AD7731

BURNOUT CURRENTS

TWO 100nA BURNOUT

CURRENTS ALLOW THE

USER TO EASILY DETECT

IF A TRANSDUCER HAS

BURNT OUT OR GONE

OPEN-CIRCUIT

SEE PAGE 23

AIN3/D1 AIN4/D0

ANALOG MULTIPLEXER

A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE

FULLY DIFFERENTIAL PAIRS OR

FIVE PSEUDO-DIFFERENTIAL INPUT

PAIRS TO BE SWITCHED TO THE

BUFFER AMPLIFIER. THE

MULTIPLEXER IS CONTROLLED

VIA THE SERIAL INTERFACE

SEE PAGE 23

BUFFER AMPLIFIER

THE BUFFER AMPLIFIER

PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS

ALLOWING SIGNIFICANT

EXTERNAL SOURCE

IMPEDANCES

SEE PAGE 23

AIN1 AIN2

MUX

AIN5 AIN6

AD7731

PROGRAMMABLE GAIN

THE PROGRAMMABLE

GAIN AMPLIFIER ALLOWS

SEVEN UNIPOLAR AND

SEVEN BIPOLAR INPUT

RANGES FROM +20mV TO

AMPLIFIER

+1.28V

SEE PAGE 23

REF IN(–)

PGA

REF IN(+)

DIFFERENTIAL

REFERENCE

THE REFERENCE INPUT TO THE

PART IS DIFFERENTIAL AND FACILITATES RATIOMETRIC

OPERATION. THE REFERENCE

VOLTAGE CAN BE SELECTED TO

BE NOMINALLY +2.5V OR +5V.

REFERENCE DETECT CIRCUITRY

TESTS FOR OPEN OR SHORTED

REFERENCES

SEE PAGE 24

SIGMA-DELTA A/D CONVERTER

SIGMADELTA

MODULATOR

PROGRAMMABLE

BUFFER

AGND

SERIAL INTERFACE

AND CONTROL LOGIC

CALIBRATION

MICROCONTROLLER

DGNDAGND

OUTPUT DRIVERS

THE AIN3 AND AIN4 INPUT

CHANNELS CAN BE

RECONFIGURED TO BECOME

TWO OUTPUT DIGITAL PORT

LINES THAT CAN BE

PROGRAMMED OVER THE

SERIAL INTERFACE

SEE PAGE 32

POL

CALIBRATION

MICROCONTROLLER

THE AD7731 OFFERS A

NUMBER OF DIFFERENT

CALIBRATION OPTIONS

INCLUDING SELF AND SYSTEM CALIBRATION

SEE PAGE 28

RDY

Figure 2. Detailed Functional Block Diagram

SIGMA-DELTA ADC

THE SIGMA-DELTA

ARCHITECTURE ENSURES

24 BITS NO MISSING CODES. THE ENTIRE

SIGMA-DELTA ADC CAN BE

CHOPPED TO REMOVE

DRIFT ERRORS

SEE PAGE 24

DIGITAL

FILTER

CLOCK

GENERATION

RESET

TWELVE REGISTERS CONTROL

ALL FUNCTIONS ON THE PART

AND PROVIDE STATUS

INFORMATION AND

CONVERSION RESULTS

SEE PAGE 20

*SPI IS A TRADEMARK OF MOTOROLA, INC.

TWO STAGE FILTER THAT ALLOWS PROGRAMMING OF OUTPUT UPDATE RATE AND

SETTLING TIME AND THAT

HAS A FASTSTEP

STANDBY

SYNC

THE CLOCK SOURCE FOR THE

MCLK IN MCLK OUT

PART CAN BE PROVIDED BY

CLOCK OR BY CONNECTING A

SCLK

DIN DOUT

SERIAL INTERFACE

SPI*-COMPATIBLE OR DSP-

INTERFACE THAT CAN BE

OPERATED FROM JUST THREE

WIRES. ALL FUNCTIONS ON THE

PART (APART FROM MASTER

RESET) CAN BE ACCESSED VIA

THE SERIAL INTERFACE

PROGRAMMABLE

DIGITAL FILTER

(SEE FIGURE 3)

MODE

SEE PAGE 24

STANDBY MODE

THE STANDBY MODE

REDUCES POWER

CONSUMPTION TO 50mW

SEE PAGE 32

CLOCK OSCILLATOR

CIRCUIT

AN EXTERNALLY-APPLIED

CRYSTAL OR CERAMIC

RESONATOR ACROSS THE

CLOCK PINS

SEE PAGE 31

COMPATIBLE SERIAL

SEE PAGE 33

–6–

REV. 0

AD7731

FASTSTEP™

FILTER

CHOP

ANALOG

INPUT

DIGITAL OUTPUT

BUFFER

SKIP

OUTPUT

SCALING

22-TAP

FIR FILTER

THE ANALOG INPUT TO THE PART

CAN BE CHOPPED. IN CHOPPING MODE,

THE INPUT IS CHOPPEDAND THE OUTPUT OF

THE FIRST STAGE FILTER IS CHOPPED

REMOVING ERRORS IN THAT PATH.

THE DEFAULT CONDITION IS

CHOPPING DISABLED

THE FIRST STAGE OF THE DIGITAL

FILTERING ON THE PART IS THE

SINC

FILTER. THE OUTPUT UPDATE

RATE AND BANDWIDTH OF THIS

FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC

FILTER IS

THE ONLY FILTERING PERFORMED

ON THE P3T.

IN SKIP MODE, THERE IS NO

SECOND STAGE OF FILTERING ON

THE PART. THE SINC

FILTER IS

THE ONLY FILTERING PERFORMED

ON THE PART. THIS IS THE

SECOND STAGE FILTER

WITH SKIP DISABLED, THE NORMAL

OPERATING MODE OF THE SECOND STAGE

OF THE DIGITAL FILTERING ON THE PART IS

A FIXED 22-TAP FIR FILTER. IN SKIP MODE,

THIS FIR FILTER IS BYPASSED. WHEN

FASTSTEP™

MODE IS ENABLED AND A

STEP INPUT IS DETECTED, THE SECOND STAGE FILTERING IS PERFORMED BY THE FAST STEP FILTER UNTIL THE OUTPUT OF

THIS FILTER HAS FULLY SETTLED

THE OUTPUT WORD FROM THE

DIGITAL FILTER IS SCALED BY THE

CALIBRATION COEFFICIENTS

BEFORE BEING PROVIDED AS THE

CONVERSION RESULT

WHEN FASTSTEP™ MODE IS

ENABLED AND A STEP CHANGE ON

THE INPUT HAS BEEN DETECTED,

THE SECOND STAGE FILTERING IS

PERFORMED BY THE FASTSTEP™

FILTER UNTIL THE FIR FILTER HAS

FULLY SETTLED.

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. THE DEFAULT

CONDITION IS CHOPPING

DISABLED

THE PROGRAMMABLE GAIN

CAPABILITY OF THE PART IS

INCORPORATED AROUND THE SIGMA DELTA MODULATOR.THE MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED

TO THE SAMPLING CAPACITOR OF

THE SIGMA DELTA MODULATOR.

THIS ISOLATES THE SAMPLING

CAPACITOR CHARGING CURRENTS

FROM THE ANALOG INPUT PINS

PGA &

SIGMA-DELTA

MODULATOR

SINC

FILTER

CHOP

INPUT CHOPPING

SINC

FILTER SKIP MODE 22-TAP FIR FILTER

OUTPUT SCALING

FASTSTEP™

FILTER

OUTPUT CHOPPING

PGA & SIGMA-DELTA

MODULATOR

BUFFER

SEE PAGE 25

SEE PAGE 26

SEE PAGE 29

SEE PAGE 28

SEE PAGE 25

SEE PAGE 24

SEE PAGE 23

Pin Pin No. Mnemonic Function

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock.

serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7731 in smaller batches of data.

A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with a clock input frequency of 4.9152 MHz.

Figure 3. Signal Processing Chain

PIN CONFIGURATION

SCLK

MCLK IN

MCLK OUT

SYNC

RESET

AGND

AIN3/D1

PIN FUNCTION DESCRIPTIONS

POL

1 2 3 4 5

AD7731

TOP VIEW

(Not to Scale)

24 23 22 21

20 19 18

817 916

10 15

AIN1 AIN2

12 13

NC = NO CONNECT

–7–REV. 0

DGND DV

DIN DOUT RDY CS STANDBY AIN6 AIN5 REF IN(–) REF IN(+) AIN4/D0

AD7731

PIN FUNCTION DESCRIPTIONS (Continued)

Pin Pin No. Mnemonic Function

3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between

MCLK IN and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving one CMOS load.

4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces-

sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle low between data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a high-to-low transition of SCLK and clocks in data from the DATA IN line in a write operation on a low-tohigh transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle high between data transfers.

5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number

of AD7731s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up for a subsequent operation that will commence when the SYNC pin is deasserted.

6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and

all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock

oscillator is reset when the RESET pin is exercised. 7 NC No Connect. The user is advised not to connect anything to this pin. 8 AGND Ground reference point for analog circuitry. 9AV

10 AIN1 Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input

11 AIN2 Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input

12 AIN3/D1 Analog Input Channel 3 or Digital Output 1. This pin can be used as either an analog input or a digital

13 AIN4/D0 Analog Input Channel 4 or Digital Output 0. This pin can be used as either an analog input or a digital

14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7731. REF IN(+) can lie

15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7731. The REF IN(–) can lie

16 AIN5 Analog Input Channel 5. Programmable-gain analog input which can be used is the positive input of a differ-

17 AIN6 Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the

18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption

19 CS Chip Select. Active low Logic Input used to select the AD7731. With this input hardwired low, the

Analog Positive Supply Voltage. The AVDD to AGND differential is 5 V nominal.

when used with AIN6 or as the positive input of a differential pair when used with AIN2.

when used with AIN6 or as the negative input of a differential pair when used with AIN1.

output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain

analog input, it can be used as a pseudo-differential input when used with AIN6 or as the positive input of a

differential pair when used with AIN4. When selected as a digital output, this output can be programmed

over the serial interface using bit D1 of the Mode Register.

output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain

analog input, it can be used as a pseudo-differential input when used with AIN6 or as the negative input of a

differential pair when used with AIN3. When selected as a digital output, this output can be programmed

over the serial interface using bit D0 of the Mode Register.

anywhere between AV

and AGND. The nominal reference voltage (i.e., the differential voltage between

REF IN(+) and REF IN(–)) should be +2.5 V when the HIREF bit of the Mode Register is 0 and is +5 V

when the HIREF bit of the Mode Register is 1.

anywhere between AV

and AGND.

ential pair when used with AIN6.

negative input of a differential input pair when used with AIN5.

to the 10 µA range. The on-chip registers retain all their values when the part is in standby mode.

AD7731 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the

device. CS can be used to select the device in systems with more than one device on the serial bus or as a

frame synchronization signal in communicating with the AD7731.

–8–

REV. 0

AD7731

PIN FUNCTION DESCRIPTIONS (Continued)

Pin Pin No. Mnemonic Function

20 RDY Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a

logic low on this output indicates that a new output word is available from the AD7731 data register. The RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again. This gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY goes high when calibration is initiated and returns low to indicate that calibration is complete. A number of different events on the AD7731 set the RDY high and these are outlined in Table XVII.

21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift

register can contain information from the calibration registers, mode register, status register, filter register or data register depending on the register selection bits of the Communications Register.

22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input

shift register is transferred to the calibration registers, mode register, communications register or filter register depending on the register selection bits of the Communications Register.

23 DV

24 DGND Ground reference point for digital circuitry.

Digital Supply Voltage, +3 V or +5 V nominal.

TERMINOLOGY

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line passing through the endpoints of thetransferfunction. The endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB belowthefirstcode transition (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5LSB above the last code transition (111 .. .110to 111...111). The error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive Full-Scale Error is the deviation of the last code transition (111 . . . 110 to 111 . .. 111) from the ideal AIN(+) voltage (AIN(–) + V

/GAIN – 3/2 LSBs). It applies to both unipolar

REF

and bipolar analog input ranges.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when operating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111...111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –

0.5 LSB) when operating in the bipolar mode.

GAIN ERROR

This is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain error are positive full scale and negative full scale.

POSITIVE FULL-SCALE OVERRANGE

Positive Full-Scale Overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than AIN(–) + V

/GAIN (for example, noise peaks or excess volt-

REF

ages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modulator or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) – V

/GAIN without overloading the

REF

analog modulator or overflowing the digital filter.

OFFSET CALIBRATION RANGE

In the system calibration modes, the AD7731 calibrates its offset with respect to the analog input. The Offset Calibration Range specification defines the range of voltages the AD7731 can accept and still accurately calibrate offset.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7731 can accept in the system calibration mode and still accurately calibrate full scale.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence to the AD7731’s analog input define the analog input range. The input span specification defines the minimum and maximum input voltages from zero to full scale that the AD7731 can accept and still accurately calibrate gain.

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – V

/GAIN + 0.5 LSB) when operat-

REF

ing in the bipolar mode. Negative full-scale error is a summation of zero error and gain error.

–9–REV. 0

AD7731

OUTPUT NOISE AND RESOLUTION SPECIFICATION

The AD7731 has a number of different modes of operation of the on-chip filter and chopping features. These options are discussed in more detail in later sections. The part can be programmed either to optimize the throughput rate and settling time or to optimize noise and drift performance. Noise tables for two of the primary modes of operation of the part are outlined below for a selection of output rates and settling times. The first mode, where the AD7731 is configured with CHP = 0 and SKIP mode enabled, provides fast settling time while still maintaining high resolution. The second mode, where CHP = 1 and the full second filter is included, provides very low noise numbers with lower output rates. Settling time refers to the time taken to get an output that is 100% settled to the new value after a channel change or exercising SYNC.

Output Noise (CHP = 0, SKIP = 1)

Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in nonchop mode (CHP of Filter Register = 0) and with the second filter bypassed (SKIP of Filter Register = 1). The table is generated with a master clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-topeak resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges. To calculate the numbers for Table II for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.

Table I. Output Noise vs. Input Range and Update Rate (CHP = 0, SKIP = 1)

Typical Output RMS Noise in mV

Output –3 dB SF Settling Input Range Data Rate Frequency Word Time 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV

150 Hz 39.3 Hz 2048 20 ms 2.6 1.45 0.87 0.6 0.43 0.28 0.2 200 Hz 52.4 Hz 1536 15 ms 3.0 1.66 1.02 0.69 0.48 0.32 0.22 300 Hz 78.6 Hz 1024 10 ms 3.7 2 1.26 0.84 0.58 0.41 0.28 400 Hz 104.8 Hz 768 7.5 ms 4.2 2.3 1.46 1.0 0.69 0.46 0.32 600 Hz 157 Hz 512 5 ms 5.2 2.9 1.78 1.2 0.85 0.58 0.41 800 Hz 209.6 Hz 384 3.75 ms 6 3.3 2.1 1.4 0.98 0.66 0.47 1200 Hz 314 Hz 256 2.5 ms 7.8 4.3 2.6 1.8 1.27 0.82 0.57 1600 Hz 419.2 Hz 192 1.87 ms 10.9 5.4 3.5 2.18 1.51 0.94 0.64 2400 Hz 629 Hz 128 1.25 ms 27.1 13.9 7.3 3.5 2.22 1.24 0.83 3200 Hz 838.4 Hz 96 0.94 ms 47 24.4 11.4 5.3 3.1 1.9 1.0 4800 Hz 1260 Hz 64 0.625 ms 99 50.3 24.5 12.5 6.5 3.3 1.7 6400 Hz 1676 Hz 48 0.47 ms 193 97 48 24 11.8 6.6 3.0

Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0, SKIP = 1)

Peak-to-Peak Resolution in Bits

Output –3 dB SF Settling Input Range Data Rate Frequency Word Time 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV

150 Hz 39.3 Hz 2048 20 ms 17.5 17 17 16.5 16 15.5 15 200 Hz 52.4 Hz 1536 15 ms 17 17 16.5 16.5 16 15.5 15 300 Hz 78.6 Hz 1024 10 ms 17 16.5 16.5 16 15.5 15 14.5 400 Hz 104.8 Hz 768 7.5 ms 16.5 16.5 16 15.5 15.5 15 14.5 600 Hz 157 Hz 512 5 ms 16.5 16 16 15.5 15 14.5 14 800 Hz 209.6 Hz 384 3.75 ms 16 16 15.5 15 14.5 14.5 14 1200 Hz 314 Hz 256 2.5 ms 15.5 15.5 15.5 15 14.5 14 13.5 1600 Hz 419.2 Hz 192 1.87 ms 15 15.5 15 14.5 14 14 13.5 2400 Hz 629 Hz 128 1.25 ms 14 14 14 14 13.5 13.5 13 3200 Hz 838.4 Hz 96 0.94 ms 13 13 13 13 13 13 12.5 4800 Hz 1260 Hz 64 0.625 ms 12 12 12 12 12 11.5 12 6400 Hz 1676 Hz 48 0.47 ms 11 11 11 11 11 11 11

–10–

REV. 0

AD7731

RS2 RS1 RS0

SELECT

DECODER

STATUS REGISTER

DATA REGISTER

MODE REGISTER

FILTER REGISTER

OFFSET REGISTER (x3)

GAIN REGISTER (x3)

TEST REGISTER

COMMUNICATIONS REGISTER

DINDIN

DIN

DOUT

Output Noise (CHP = 1, SKIP = 0)

Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a master clock frequency of 4.9152 MHz. These numbers are typical and generated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges. To calculate the number for Table IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.

Table III. Output Noise vs. Input Range and Update Rate (CHP = 1, SKIP = 0)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Input Range Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV

50 Hz 1.97 Hz 2048 440 ms 40 ms 700 425 265 170 120 85 55 100 Hz 3.95 Hz 1024 220 ms 20 ms 980 550 330 230 190 115 90 150 Hz 5.92 Hz 683 147 ms 13.3 ms 1230 700 445 270 210 140 100 200 Hz 7.9 Hz 512 110 ms 10 ms 1260 840 500 340 245 170 105 400 Hz 15.8 Hz 256 55 ms 5 ms 2000 1230 690 430 335 215 160 800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 3800 2100 1400 760 590 345 220

Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1, SKIP = 0)

Peak-to-Peak Resolution in Bits

Output –3 dB SF Settling Time Input Range Data Rate Frequency Word Normal Fast Step 61.28 V 6640 mV 6320 mV 6160 mV 680 mV 640 mV 620 mV

50 Hz 1.97 Hz 2048 440 ms 40 ms 19 19 18.5 18.5 18 17.5 17 100 Hz 3.95 Hz 1024 230 ms 30 ms 19 18.5 18.5 18 17 17 16 150 Hz 5.92 Hz 683 147 ms 13.3 ms 18.5 18 18 17.5 17 16.5 16 200 Hz 7.9 Hz 512 110 ms 10 ms 18.5 18 17.5 17.5 17 16.5 16 400 Hz 15.8 Hz 256 55 ms 5 ms 17.5 17.5 17 17 16.5 16 15.5 800 Hz 31.6 Hz 128 27.5 ms 2.5 ms 17 16.5 16 16 15.5 15 15

ON-CHIP REGISTERS

The AD7731 contains 12 on-chip registers that can be accessed via the serial port of the part. These registers are summarized in Figure 4 and in Table V, and described in detail in the following sections.

Figure 4. Register Overview

–11–REV. 0

AD7731

Table V. Summary of On-Chip Registers

Power-On/Reset

Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through Register the Communications Register. This controls whether

NEW

OREZ1WR0WROREZ2SR1SR0SR

Status Register Read Only 8 Bits CX Hex Provides status information on conversions, calibra-

YDRYDTS

YBTSFERON3SM2SM1SM0SM

Data Register Read Only 16 Bits or 24 Bits 000000 Hex Provides the most up-to-date conversion result from

Mode Register Read/Write 16 Bits 0174 Hex Controls functions such as mode of operation, uni-

2DM1DM0DM

FERIH2NR1NR0NROB2HC1HC0HC

BU/

NED1D0DLW

Filter Register Read/Write 16 Bits 2002 Hex Controls the amount of averaging in the first stage

11FS01FS9FS8FS7FS6FS5FS4FS

3FS2FS1FS0FSOREZPHCPIKSTSAF

subsequent operations are read or write operations and also selects the register for that subsequent operation. Most subsequent operations return control to the Communications Register except for the continuous read mode of operation.

tions, settling to step inputs, standby operation and the validity of the reference voltage.

the part. Register length can be programmed to be 16 bit or 24 bit.

polar/bipolar operation, controlling the function of AIN3/D1 and AIN4/D0, burnout current and Data Register word length. It also contains the reference selection bit, the range selection bits and the channel selection bits.

filter, selects the fast step and skip modes and controls the chopping modes on the part.

Offset Register Read/Write 24 Bits Contains a 24-bit word which is the offset calibration

coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are three Offset Registers on the part and these are associated with input channel pairs as outlined in Table XIII.

Gain Register Read/Write 24 Bits Contains a 24-bit word which is the gain calibration

coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are three Gain Registers on the part and these are associated with input channel pairs as outlined in Table XIII.

Test Register Read/Write 24 Bits 000000 Hex Controls the test modes of the part which are used

when testing the part. The user is advised not to

change the contents of this register.

–12–

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AD7731

Communications Register (RS2-RS0 = 0, 0, 0)

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation and to which register this operation takes place. For single-shot read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7731 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream.

Table VI. Communications Register

7RC

NEW

Bit Bit Location Mnemonic Description

CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communica-

CR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. CR5, CR4 RW1, RW0 Read Write Mode Bits. These two bits determine the nature of the subsequent read/write

6RC5RC4RC3RC2RC1RC0RC

OREZ1WR0WROREZ2SR1SR0SR

tions Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register.

operation. Table VII outlines the four options.

Table VII. Read/Write Mode

RW1 RW0 Read/Write Mode

0 0 Single Write to Specified Register 0 1 Single Read of Specified Register 1 0 Start Continuous Read of Specified Register 1 1 Stop Continuous Read Mode

With 0, 0 written to these two bits, the next operation is a write operation to the register specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified register has been completed, the part returns to where it is expecting a write operation to the Communications Register.

With 0, 1 written to these two bits, the next operation is a read operation of the register specified by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been completed, the part returns to where it is expecting a write operation to the Communications Register.

Writing 1, 0 to these bits, sets the part into a mode of continuous reads from the register specified by bits RS2, RS1, RS0. The most likely registers which the user will want to use this function with are the Data Register and the Status Register. Subsequent operations to the part will consist of read operations to the specified register without any intermediate writes to the Communications Register. This means that once the next read operation to the specified register has taken place, the part will be in a mode where it is expecting another read from that specified register. The part will remain in this continuous read mode until 30 Hex has been written to bits RW1 and RW0.

When 1, 1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous read mode is stopped and the part returns to where it is expecting a write operation to the Communications Register. Note, the part continues to look at the DIN line on each SCLK edge during the continuous read mode so that it can determine when to stop the continuous read mode. Therefore, the user must be careful not to inadvertently exit the continuous read mode or reset the part by writing a series of 1s to the part. The easiest way to avoid this is to place a logic 0 on the DIN line while the part is in continuous read mode.

–13–REV. 0

AD7731

Bit Bit Location Mnemonic Description

CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7731. CR2-CR0 RS2-RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which

one of eight on-chip registers the next read or write operation takes place as shown in Table VIII.

Table VIII. Register Selection

RS2 RS1 RS0 Register

0 0 0 Communications Register (Write Operation) 0 0 0 Status Register (Read Operation) 0 0 1 Data Register 0 1 0 Mode Register 0 1 1 Filter Register 1 0 0 No Register Access 1 0 1 Offset Register 1 1 0 Gain Register 1 1 1 Test Register

Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex

The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets indicates the power-on/reset default status of that bit.

Table IX. Status Register

7RS6RS5RS4RS3RS2RS1RS0RS

YDR)1(YDTS)1(

Bit Bit Location Mnemonic Description

SR7 RDY Ready Bit. This bit provides the status of the RDY flag from the part. The status and func-

tion of this bit is the same as the RDY output pin. A number of events set the RDY bit high as indicated in Table XVII.

SR6 STDY Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter

is in FASTStep™ mode (see Filter Register section), and responding to a step input, the STDY bit remains high as the initial conversion results become available. The RDY output and bit are set low on these initial conversions to indicate that a result is available. However, if the STDY is high, it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coincident with RDY. If the part is never placed into its FASTStep™ mode, the STDY bit will go low at the first Data Register read and it is not cleared by subsequent Data Register reads.

A number of events set the STDY bit high as indicated in Table XVII. STDY is set high along with RDY by all events in the table except a Data Register read.

SR5 STBY Standby Bit. This bit indicates whether the AD7731 is in its Standby Mode or normal mode

of operation. The part can be placed in its standby mode using the STANDBY input pin or by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit is 0 assuming the STANDBY pin is high.

SR4 NOREF No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V

or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion of a calibration, updating of the calibration registers is inhibited.

SR3-SR0 MS3-MS0 These bits are for factory use. The power-on/reset status of these bits varies depending on the

factory-assigned number.

)0(YBTS)0(FERON)X(3SM)X(2SM)X(1SM)X(0SM

–14–

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+ 30 hidden pages

Analog Devices AD7731EB, AD7731BRU, AD7731BR, AD7731BN Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FUNCTIONAL BLOCK DIAGRAM

TIMING CHARACTERISTICS

ORDERING GUIDE

TERMINOLOGY

OUTPUT NOISE AND RESOLUTION SPECIFICATION