Analog Devices AD7730LEB, AD7730EB, AD7730LBRU, AD7730LBR, AD7730BRU Datasheet

a

Bridge Transducer ADC

AD7730/AD7730L

KEY FEATURES
Resolution of 230,000 Counts (Peak-to-Peak)
Offset Drift: 5 nV/8C
Gain Drift: 2 ppm/8C
Line Frequency Rejection: >150 dB
Buffered Differential Inputs
Programmable Filter Cutoffs
Specified for Drift Over Time
Operates with Reference Voltages of 1 V to 5 V

ADDITIONAL FEATURES
Two-Channel Programmable Gain Front End
On-Chip DAC for Offset/TARE Removal

FAST

Step™ Mode
AC or DC Excitation
Single Supply Operation

APPLICATIONS
Weigh Scales
Pressure Measurement

GENERAL DESCRIPTION

The AD7730 is a complete analog front end for weigh-scale and
pressure measurement applications. The device accepts low­level signals directly from a transducer and outputs a serial
digital word. The input signal is applied to a proprietary pro­grammable gain front end based around an analog modulator.

The modulator output is processed by a low pass programmable
digital filter, allowing adjustment of filter cutoff, output rate and
settling time.

The part features two buffered differential programmable gain
analog inputs as well as a differential reference input. The part
operates from a single +5 V supply. It accepts four unipolar
analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and
+80 mV and four bipolar ranges: ±10 mV, ±20 mV, ±40 mV
and ±80 mV. The peak-to-peak resolution achievable directly
from the part is 1 in 230,000 counts. An on-chip 6-bit DAC
allows the removal of TARE voltages. Clock signals for synchro­nizing ac excitation of the bridge are also provided.

The serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. The AD7730 contains self-calibration and
system calibration options, and features an offset drift of less
than 5 nV/°C and a gain drift of less than 2 ppm/°C.

The AD7730 is available in a 24-pin plastic DIP, a 24-lead
SOIC and 24-lead TSSOP package. The AD7730L is available
in a 24-lead SOIC and 24-lead TSSOP package.

NOTE

The description of the functions and operation given in this data
sheet apply to both the AD7730 and AD7730L. Specifications
and performance parameters differ for the parts. Specifications
for the AD7730L are outlined in Appendix A.

FUNCTIONAL BLOCK DIAGRAM

AV

VBIAS

AIN1(+)
AIN1(–)

MUX

AIN2(+)/D1
AIN2(–)/D0

ACX

ACX

FASTStep is a trademark of Analog Devices, Inc.

EXCITATION

CLOCK

DD

DV

AV

100nA

100nA

AGND

AC

DD

DD

BUFFER

6-BIT

DAC

REF IN(–)

REFERENCE DETECT

+

PGA

+/–

DGNDAGND

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REF IN(+)

AD7730

SIGMA-DELTA A/D CONVERTER

SIGMA-

DELTA

MODULATOR

SERIAL INTERFACE

AND CONTROL LOGIC

CALIBRATION

MICROCONTROLLER

POL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

PROGRAMMABLE

REGISTER BANK

RDY

DIGITAL

FILTER

CLOCK

GENERATION

RESET

STANDBY

SYNC

MCLK IN
MCLK OUT

SCLK

CS

DIN
DOUT

(AVDD = +5 V, DVDD = +3 V or +5 V; REF IN(+) = AVDD; REF IN(–) = AGND = DGND =

AD7730–SPECIFICATIONS

Parameter B Version

STATIC PERFORMANCE (CHP = 1)

No Missing Codes
Output Noise and Update Rates
Integral Nonlinearity 18 ppm of FSR max
Offset Error
Offset Drift vs. Temperature
Offset Drift vs. Time
Positive Full-Scale Error
Positive Full-Scale Drift vs Temp
Positive Full-Scale Drift vs Time
Gain Error
Gain Drift vs. Temperature
Gain Drift vs. Time
Bipolar Negative Full-Scale Error
Negative Full-Scale Drift vs. Temp

2, 8

2

2

2

2

4

2, 5

2, 6, 7

4

2, 6, 9

4

2

24 Bits min
See Tables I & II

See Note 3 Offset Error and Offset Drift Refer to Both
5 nV/°C typ Unipolar Offset and Bipolar Zero Errors
25 nV/1000 Hours typ
See Note 3
2 ppm of FS/°C max
10 ppm of FS/1000 Hours typ
See Note 3
2 ppm/°C max
10 ppm/1000 Hours typ
See Note 3

2, 6

2 ppm of FS/°C max

0 V; f

1

Power Supply Rejection 120 dB typ Measured with Zero Differential Voltage
Common-Mode Rejection (CMR) 120 dB min At DC. Measured with Zero Differential Voltage
Analog Input DC Bias Current
Analog Input DC Bias Current Drift
Analog Input DC Offset Current

2

2

50 nA max

2

100 pA/°C typ
10 nA max

Analog Input DC Offset Current Drift250 pA/°C typ

STATIC PERFORMANCE (CHP = 0)

2

No Missing Codes 24 Bits min SKIP = 0
Output Noise and Update Rates See Tables III & IV
Integral Nonlinearity 18 ppm of FSR max
Offset Error See Note 3 Offset Error and Offset Drift Refer to Both
Offset Drift vs. Temperature
Offset Drift vs. Time
Positive Full-Scale Error
Positive Full-Scale Drift vs. Temp
Positive Full-Scale Drift vs. Time
Gain Error
Gain Drift vs. Temperature
Gain Drift vs. Time

8

4

6

4

5

6, 7

4

6, 9

0.5 µV/°C typ Unipolar Offset and Bipolar Zero Errors

2.5 µV/1000 Hours typ
See Note 3

0.6 µV/°C typ
3 µV/1000 Hours typ
See Note 3
2 ppm/°C typ

10 ppm/1000 Hours typ
Bipolar Negative Full-Scale Error See Note 3
Negative Full-Scale Drift vs. Temp 0.6 µV/°C typ
Power Supply Rejection 90 dB typ Measured with Zero Differential Voltage
Common-Mode Rejection (CMR) on AIN 100 dB typ At DC. Measured with Zero Differential Voltage
CMR on REF IN 120 dB typ At DC. Measured with Zero Differential Voltage
Analog Input DC Bias Current 60 nA max
Analog Input DC Bias Current Drift 150 pA/°C typ
Analog Input DC Offset Current 30 nA max
Analog Input DC Offset Current Drift 100 pA/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
Analog Inputs

Differential Input Voltage Ranges

2
2

2
2

88 dB min From 49 Hz to 51 Hz

88 dB min From 59 Hz to 61 Hz

120 dB min From 49 Hz to 51 Hz

120 dB min From 59 Hz to 61 Hz

11

0 to +10 or ±10 mV nom Gain = 250

0 to +20 or ±20 mV nom Gain = 125

0 to +40 or ±40 mV nom Gain = 62.5

0 to +80 or ±80 mV nom Gain = 31.25

12

Absolute/Common-Mode Voltage

AGND + 1.2 V V min

– 0.95 V V max

AV

DD

Reference Input

REF IN(+) – REF IN(–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0
REF IN(+) – REF IN(–) Voltage +5 V nom HIREF Bit of Mode Register = 1
Absolute/Common-Mode Voltage

13

AGND – 30 mV V min

+ 30 mV V max

AV

DD

NO REF Trigger Voltage 0.3 V min NO REF Bit Active If V

0.65 V max NO REF Bit Inactive If V

= 4.9152 MHz. All specifications T

CLK IN

MIN

to T

MAX

Units Conditions/Comments

10

Assuming 2.5 V or 5 V Reference with
HIREF Bit Set Appropriately

unless otherwise noted.)

Below This Voltage

REF

Above This Voltage

REF

–2–

REV. A

AD7730/AD7730L

Parameter B Version

1

Units Conditions/Comments

LOGIC INPUTS

Input Current ±10 µA max
All Inputs Except SCLK and MCLK IN

, Input Low Voltage 0.8 V max DVDD = +5 V

V

INL

, Input Low Voltage 0.4 V max DVDD = +3 V

V

INL

, Input High Voltage 2.0 V min

V

INH

SCLK Only (Schmitt Triggered Input)

V

T+

V

T+

V

T–

V

T–

– V

V

T+

T–

– V

V

T+

T–

1.4/3 V min to V max DVDD = +5 V
1/2.5 V min to V max DVDD = +3 V

0.8/1.4 V min to V max DVDD = +5 V

0.4/1.1 V min to V max DVDD = +3 V

0.4/0.8 V min to V max DVDD = +5 V

0.4/0.8 V min to V max DVDD = +3 V

MCLK IN Only

, Input Low Voltage 0.8 V max DVDD = +5 V

V

INL

, Input Low Voltage 0.4 V max DVDD = +3 V

V

INL

, Input High Voltage 3.5 V min DVDD = +5 V

V

INH

V

, Input High Voltage 2.5 V min DVDD = +3 V

INH

LOGIC OUTPUTS (Including MCLK OUT)

V

, Output Low Voltage I

OL

0.4 V max V

, Output Low Voltage I

V

OL

0.4 V max V

, Output High Voltage I

V

OH

4.0 V min V

, Output High Voltage I

V

OH

Floating State Leakage Current ±10 µA max
Floating State Output Capacitance

2

– 0.6 V V min V

V

DD

6 pF typ

= 800 µA Except for MCLK OUT14;

SINK

15

= +5 V

DD

= 100 µA Except for MCLK OUT14;

SINK

15

= +3 V

DD

= 200 µA Except for MCLK OUT14;

SOURCE

15

= +5 V

DD

= 100 µA Except for MCLK OUT14;

SOURCE

15

= +3 V

DD

TRANSDUCER BURNOUT

AIN1(+) Current –100 nA nom
AIN1(–) Current 100 nA nom
Initial Tolerance @ 25°C ±10 % typ

2

Drift

0.1 %/°C typ

OFFSET (TARE) DAC

Resolution 6 Bit
LSB Size 2.3/2.6 mV min/mV max 2.5 mV Nominal with 5 V Reference (REF IN/2000)
DAC Drift
DAC Drift vs. Time

16

4, 16

2.5 ppm/°C max
25 ppm/1000 Hours typ

Differential Linearity –0.25/+0.75 LSB max Guaranteed Monotonic

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit

Offset Calibration Limit
Input Span

17

18

17

17

1.05 × FS V max FS Is the Nominal Full-Scale Voltage
(10 mV, 20 mV, 40 mV or 80 mV)

–1.05 × FS V max
–1.05 × FS V max

0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS

Power Supply Voltages

– AGND Voltage +4.75 to +5.25 V min to V max

AV

DD

Voltage +2.7 to +5.25 V min to V max With AGND = 0 V

DV

DD

Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV

DD

AVDD Current (Normal Mode) 10.3 mA max All Input Ranges Except 0 mV to +10 mV and ± 10 mV

Current (Normal Mode) 22.3 mA max Input Ranges of 0 mV to +10 mV and ± 10 mV Only

AV

DD

Current (Normal Mode) 1.3 mA max DVDD of 2.7 V to 3.3 V

DV

DD

Current (Normal Mode) 2.7 mA max DVDD of 4.75 V to 5.25 V

DV

DD

+ DVDD Current (Standby Mode) 25 µA max Typically 10 µA. External MCLK IN = 0 V or DV

AV

DD

Power Dissipation AV

DD

= DV

= +5 V. Digital I/Ps = 0 V or DV

DD

DD

Normal Mode 65 mW max All Input Ranges Except 0 mV to +10 mV and ±10 mV

125 mW max Input Ranges of 0 mV to +10 mV and ±10 mV Only

Standby Mode 125 µW max Typically 50 µW. External MCLK IN = 0 V or DV

DD

DD

REV. A

–3–

AD7730/AD7730L

NOTES

11

Temperature range: –40°C to +85°C.

12

Sample tested during initial release.

13

The offset (or zero) numbers with CHP = 1 are typically 3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. Offset numbers with CHP = 0 can be up to
1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the
noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than
100 ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of
the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors.

14

These numbers are generated during life testing of the part.

15

Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.

16

Recalibration at any temperature will remove these errors.

17

Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

18

Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain
error are positive full scale and negative full scale. See Terminology.

19

Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.

10

No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal.

11

The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively.

12

The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

13

The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.

14

These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

15

VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AVDD.

16

This number represents the total drift of the channel with a zero input and the DAC output near full scale.

17

After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s.

18

These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the
bipolar zero point.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

MIN

(AVDD = +4.75 V to +5.25 V; DVDD = +2.7 V to +5.25 V; AGND = DGND = 0 V; f

1, 2

Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted).

to T

MAX

= 4.9152 MHz;

CLK IN

Parameter (B Version) Units Conditions/Comments

Master Clock Range 1 MHz min For Specified Performance

5 MHz max

t

1

t

2

50 ns min SYNC Pulsewidth
50 ns min RESET Pulsewidth

Read Operation

t

3

t

4

4

t

5

0 ns min RDY to CS Setup Time
0 ns min CS Falling Edge to SCLK Active Edge Setup Time
0 ns min SCLK Active Edge to Data Valid Delay

3

3

60 ns max DVDD = +4.75 V to +5.25 V

4, 5

t

5A

80 ns max DV
0 ns min CS Falling Edge to Data Valid Delay
60 ns max DV
80 ns max DV

t

6

t

7

t

8

6

t

9

100 ns min SCLK High Pulsewidth
100 ns min SCLK Low Pulsewidth
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
10 ns min Bus Relinquish Time after SCLK Inactive Edge
80 ns max

t

10

100 ns max SCLK Active Edge to RDY High

Write Operation

t

11

t

12

t

13

t

14

t

15

t

16

NOTES

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figures 18 and 19.

3

SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.

4

These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.

5

This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for
interfacing to DSP machines.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

7

RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.

0 ns min CS Falling Edge to SCLK Active Edge Setup Time
30 ns min Data Valid to SCLK Edge Setup Time
25 ns min Data Valid to SCLK Edge Hold Time
100 ns min SCLK High Pulsewidth
100 ns min SCLK Low Pulsewidth
0 ns min CS Rising Edge to SCLK Edge Hold Time

= +2.75 V to +3.3 V

DD

= +4.75 V to +5.25 V

DD

= +2.7 V to +3.3 V

DD

3

3

3, 7

3

–4–

REV. A

AD7730/AD7730L

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

DV

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5 V to +0.3 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V

DD

Analog Input Voltage to AGND . . . . –0.3 V to AV

Reference Input Voltage to AGND . . –0.3 V to AV

DD
DD

+ 0.3 V

+ 0.3 V

AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV

+ 0.3 V

DD

+ 0.3 V

DD

Output Voltage (ACX, ACX, D0, D1) to DGND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

AD7730BN –40°C to +85°C Plastic DIP N-24
AD7730BR –40°C to +85°C Small Outline R-24
AD7730BRU –40°C to +85°C Thin Shrink Small Outline RU-24
EVAL-AD7730EB Evaluation Board
AD7730LBR –40°C to +85°C Small Outline R-24
AD7730LBRU –40°C to +85°C Thin Shrink Small Outline RU-24
EVAL-AD7730LEB Evaluation Board

Plastic DIP Package, Power Dissipation . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . 105°C/W

JA

Lead Temperature (Soldering, 10 sec) . . . . . . . +260°C

TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.

I

TO OUTPUT

PIN

50pF

(800mA AT DV

SINK

100mA AT DV

(200mA AT DVDD = +5V

I

SOURCE

100mA AT DV

+1.6V

DD

DD

= +5V
= +3V)

= +3V)

DD

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7730 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD7730/AD7730L

,

PRESENTS A HIGH IMPEDANCE
INPUT STAGE FOR THE ANALOG
INPUTS ALLOWING SIGNIFICANT

BURNOUT CURRENTS

TWO 100nA BURNOUT

CURRENTS ALLOW THE USER

TO EASILY DETECT IF A

TRANSDUCER HAS BURNT

OUT OR GONE OPEN-CIRCUIT

SEE PAGE 25

AIN2(+)/D1
AIN2(–)/D0

ANALOG MULTIPLEXER

A TWO-CHANNEL DIFFERENTIAL

MULTIPLEXER SWITCHES ONE OF

THE TWO DIFFERENTIAL INPUT

CHANNELS TO THE BUFFER

AMPLIFIER. THE MULTIPLEXER IS

CONTROLLED VIA THE SERIAL

INTERFACE

SEE PAGE 24

AC EXCITATION

FOR AC-EXCITED BRIDGE

APPLICATIONS, THE ACX

OUTPUTS PROVIDE SIGNALS
THAT CAN BE USED TO SWITCH
THE POLARITY OF THE BRIDGE

EXCITATION VOLTAGE

SEE PAGE 41

BUFFER AMPLIFIER

THE BUFFER AMPLIFIER

EXTERNAL SOURCE

IMPEDANCES

SEE PAGE 24

VBIAS

AIN1(+)
AIN1(–)

ACX

ACX

RECONFIGURED TO BECOME TWO

PROGRAMMABLE GAIN

AMPLIFIER

THE PROGRAMMABLE GAIN

AMPLIFIER ALLOWS FOUR

UNIPOLAR AND FOUR BIPOLAR

INPUT RANGES FROM

+10mV TO +80mV

SEE PAGE 24

AV

DV

AV

DD

DD

DD

MUX

BUFFER

6-BIT

AGND

DAC

AC

EXCITATION

CLOCK

OUTPUT DRIVERS

THE SECOND ANALOG INPUT

CHANNEL CAN BE

OUTPUT DIGITAL PORT LINES
WHICH CAN BE PROGRAMMED
OVER THE SERIAL INTERFACE

SEE PAGE 33

THE REFERENCE INPUT TO THE

VOLTAGE CAN BE SELECTED TO

REF IN(–)

REF IN(+)

REFERENCE DETECT

+

PGA

+/–

SERIAL INTERFACE

AND CONTROL LOGIC

CALIBRATION

MICROCONTROLLER

DGNDAGND

POL

OFFSET/TARE DAC

ALLOWS A PROGRAMMED

VOLTAGE TO BE EITHER ADDED

OR SUBTRACTED FROM THE

ANALOG INPUT SIGNAL BEFORE

IT IS APPLIED TO THE PGA

SEE PAGE 24

DIFFERENTIAL

REFERENCE

PART IS DIFFERENTIAL AND
FACILITATES RATIOMETRIC

OPERATION. THE REFERENCE

BE NOMINALLY +2.5V OR +5V

SEE PAGE 25

AD7730

SIGMA-DELTA A/D CONVERTER

SIGMA­DELTA

MODULATOR

PROGRAMMABLE

REGISTER BANK

RDY

DIGITAL

FILTER

GENERATION

THIRTEEN REGISTERS CONTROL

ALL FUNCTIONS ON THE PART AND

PROVIDE STATUS INFORMATION

SIGMA-DELTA ADC

SIGMA DELTA ADC

THE SIGMA-DELTA

THE SIGMA DELTA
ARCHITECTURE ENSURES 24 BITS
ARCHITECTURE ENSURES 24 BITS

NO MISSING CODES. THE

NO MISSING CODES. THE
ENTIRE SIGMA-DELTA ADC CAN
ENTIRE SIGMA DELTA. ADC CAN
BE CHOPPED TO REMOVE DRIFT
BE CHOPPED TO REMOVE DRIFT

ERRORS
ERRORS

SEE PAGE 26

SEE PAGE

STANDBY

SYNC

CLOCK

MCLK IN
MCLK OUT

SCLK

CS

DIN
DOUT

RESET

REGISTER BANK

AND CONVERSION RESULTS

SEE PAGE 11

*SPI IS A TRADEMARK OF MOTOROLA

PROGRAMMABLE

DIGITAL FILTER

TWO STAGE FILTER THAT
ALLOWS PROGRAMMING OF
OUTPUT UPDATE RATE AND

SETTLING TIME AND WHICH HAS

A FAST STEP MODE

(SEE FIGURE 3)

SEE PAGE 26

STANDBY MODE

THE STANDBY MODE REDUCES
POWER CONSUMPTION TO 5mA

SEE PAGE 33

CLOCK OSCILLATOR

CIRCUIT

THE CLOCK SOURCE FOR THE

PART CAN BE PROVIDED BY AN

EXTERNALLY-APPLIED CLOCK OR

BY CONNECTING A CRYSTAL OR

CERAMIC RESONATOR ACROSS

THE CLOCK PINS

SEE PAGE 32

SERIAL INTERFACE

SPI*-COMPATIBLE OR DSP­COMPATIBLE SERIAL INTERFACE
WHICH CAN BE OPERATED FROM

JUST THREE WIRES. ALL

FUNCTIONS ON THE PART

CAN BE ACCESSED VIA
THE SERIAL INTERFACE

SEE PAGE 35

INC.

Figure 2. Detailed Functional Block Diagram

–6–

REV. A

AD7730/AD7730L

INPUT CHOPPING

THE ANALOG INPUT TO THE PART CAN BE

CHOPPED. IN CHOPPING MODE, WITH

AC EXCITATION DISABLED, THE INPUT

CHOPPING IS INTERNALTO THE DEVICE. IN

CHOPPING MODE, WITH AC EXCITATION

ENABLED, THE CHOPPING IS ASSUMED

TO BE PERFORMED EXTERNAL TO THE PART

AND NO INTERNAL INPUT CHOPPING IS

PERFORMED. THE INPUT CHOPPING CAN

BE DISABLED, IF DESIRED.

SEE PAGE 26

ANALOG

INPUT

BUFFER

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED TO

THE SAMPLING CAPACITOR OF THE

SIGMA-DELTA MODULATOR. THIS

ISOLATES THE SAMPLING CAPACITOR

CHARGING CURRENTS FROM THE

ANALOG INPUT PINS.

SEE PAGE 24

THE FIRST STAGE OF THE DIGITAL FILTERING

ON THE PART IS THE SINC

OUTPUT UPDATE RATE AND BANDWIDTH

OF THIS FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC

ONLY FILTERING PERFORMED ON THE PART.

CHOP

BUFFER

PGA + SIGMA-DELTA MODULATOR

THE PROGRAMMABLE GAIN CAPABILITY

OF THE PART IS INCORPORATED

AROUND THE SIGMA-DELTA MODULATOR.

THE MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

SEE PAGE 26

SINC3 FILTER

IN SKIP MODE, THERE IS NO SECOND

STAGE OF FILTERING ON THE PART. THE

3

SINC

FILTER IS THE ONLY FILTERING

PERFORMED ON THE PART.

CHOP

SEE PAGE 26

PGA +

SIGMA-DELTA

MODULATOR

3

FILTER. THE

3

FILTER IS THE

SINC3 FILTER

OUTPUT CHOPPING

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. IN CHOPPING MODE,

REGARDLESS OF WHETHER AC

EXCITATION IS ENABLED OR DISABLED,

THE OUTPUT CHOPPING IS

PERFORMED. THE CHOPPING CAN

BE DISABLED, IF DESIRED.

SEE PAGE 26

Figure 3. Signal Processing Chain

SKIP MODE

SECOND STAGE OF THE DIGITAL FILTERING

FILTER. IN SKIP MODE, THIS FIR FILTER IS

SEE PAGE 29

DETECTED, THE SECOND STAGE FILTERING

SKIP

22-TAP

FIR FILTER

FASTSTEP

FILTER

THE OUTPUT WORD FROM THE DIGITAL

FILTER IS SCALED BY THE CALIBRATION

COEFFICIENTS BEFORE BEING PROVIDED

FASTSTEP FILTER

WHEN FASTSTEP MODE IS ENABLED

AND A STEP CHANGE ON THE INPUT
HAS BEEN DETECTED, THE SECOND

STAGE FILTERING IS PERFORMED BY THE

FASTSTEP FILTER UNTIL THE FIR

FILTER HAS FULLY SETTLED.

SEE PAGE 29

22-TAP FIR FILTER

IN NORMAL OPERATING MODE, THE

ON THE PART IS A FIXED 22-TAP FIR

BYPASSED. WHEN FASTSTEP™

ENABLED AND A STEP INPUT IS
IS PERFORMED BY THE FILTER

UNTIL THE OUTPUT OF THIS FILTER

HAS FULLY SETTLED.

SEE PAGE 27

OUTPUT
SCALING

OUTPUT SCALING

AS THE CONVERSION RESULT.

SEE PAGE 29

MODE IS

DIGITAL
OUTPUT

PIN CONFIGURATION

1

SCLK

MCLK IN

MCLK OUT

POL

SYNC

RESET

V

BIAS

AGND

AV
AIN1(+)
AIN1(–)

AIN2(+)/D1

2
3

4
5

AD7730

6

TOP VIEW

7

(Not to Scale)

8
9

DD

10
11
12 13

DGND

24

DV

23
22

DIN

21

DOUT

20

RDY

19

CS

18

STANDBY

17

ACX

ACX

16

REF IN(–)

15
14

REF IN(+)
AIN2(–)/D0

DD

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial

data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con­tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted
to or from the AD7730 in smaller batches of data.

2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A

crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin
can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified
with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of

2.4576 MHz.

REV. A

–7–

AD7730/AD7730L

Pin
No. Mnemonic Function

3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN

and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig­nal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving
one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLKDIS bit of the Mode
Register. This ensures that the part is not burning unnecessary power driving capacitance on the MCLK OUT pin.

4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces-

sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the
DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA
IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial
clock (such as most microcontroller applications), this means that the serial clock should idle low between
data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high.
In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a high-to-low transi­tion of SCLK and clocks in data from the DATA IN line in a write operation on a low-to-high transition of
SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this
means that the serial clock should idle high between data transfers.

5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number

of AD7730s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital
interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up
for a subsequent operation which will commence when the SYNC pin is deasserted.

6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and

all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock
oscillator is reset when the RESET pin is exercised.

7V

BIAS

8 AGND Ground reference point for analog circuitry.
9AV

DD

10 AIN1(+) Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. The

11 AIN1(–) Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair.
12 AIN2(+)/D1 Analog Input Channel 2 or Digital Output 1. This pin can be used either as part of a second analog input

13 AIN2(–)/D0 Analog Input Channel 2 or Digital Output 0. This pin can be used either as part of a second analog input channel

14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie

15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7730. The REF IN(–) poten-

16 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-

17 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-

Analog Output. This analog output is an internally-generated voltage used as an internal operating bias point.
This output is not for use external to the AD7730 and it is recommended that the user does not connect any­thing to this pin.

Analog Positive Supply Voltage. The AVDD to AGND differential is 5 V nominal.
differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV

in unipolar mode, and ±10 mV, ± 20 mV, ±40 mV and ±80 mV in bipolar mode.

channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an
analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. The
analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo­lar mode and ±10 mV, ±20 mV, ± 40 mV and ±80 mV in bipolar mode. When selected as a digital output,
this output can programmed over the serial interface using bit D1 of the Mode Register.

or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it
is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital
output, this output can programmed over the serial interface using bit D0 of the Mode Register.

anywhere between AV

and AGND. The nominal reference voltage (the differential voltage between REF

DD

IN(+) and REF IN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the
HIREF bit of the Mode Register is 0.

tial can lie anywhere between AV

and AGND.

DD

excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is
low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode
turned off), the ACX output remains high.

excited bridge applications. This output is the complement of ACX. In ac mode, this means that it toggles in
anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the ACX output
remains low. When toggling, it is guaranteed to be nonoverlapping with ACX. The non-overlap interval, when
both ACX and ACX are low, is one master clock cycle.

–8–

REV. A

AD7730/AD7730L

Pin
No. Mnemonic Function

18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to

the 5 µA range. The on-chip registers retain all their values when the part is in standby mode.

19 CS Chip Select. Active low Logic Input used to select the AD7730. With this input hardwired low, the AD7730

can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS
can be used to select the device in systems with more than one device on the serial bus or as a frame synchro­nization signal in communicating with the AD7730.

20 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a

logic low on this output indicates that a new output word is available from the AD7730 data register. The
RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken
place after an output update, the RDY line will return high prior to the next output update, remain high while
the update is taking place and return low again. This gives an indication of when a read operation should not
be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY
goes high when calibration is initiated and it returns low to indicate that calibration is complete. A number of
different events on the AD7730 set the RDY high and these are outlined in Table XVIII.

21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift

register can contain information from the calibration registers, mode register, status register, filter register,
DAC register or data register, depending on the register selection bits of the Communications Register.

22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input

shift register is transferred to the calibration registers, mode register, communications register, DAC register
or filter registers depending on the register selection bits of the Communications Register.

23 DV

DD

24 DGND Ground reference point for digital circuitry.

Digital Supply Voltage, +3 V or +5 V nominal.

TERMINOLOGY

INTEGRAL NONLINEARITY

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi­tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.

POSITIVE FULL-SCALE ERROR

Positive Full-Scale Error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V

/GAIN – 3/2 LSBs). It applies to both unipolar

REF

and bipolar analog input ranges. Positive full-scale error is a
summation of offset error and gain error.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper­ating in the unipolar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)
when operating in the bipolar mode.

GAIN ERROR

This is a measure of the span error of the ADC. It is a measure
of the difference between the measured and the ideal span be­tween any two points in the transfer function. The two points
used to calculate the gain error are full scale and zero scale.

REV. A

–9–

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V

/GAIN + 0.5 LSB) when operat-

REF

ing in the bipolar mode. Negative full-scale error is a summation
of zero error and gain error.

POSITIVE FULL-SCALE OVERRANGE

Positive Full-Scale Overrange is the amount of overhead avail­able to handle input voltages on AIN(+) input greater than
AIN(–) + V

/GAIN (for example, noise peaks or excess volt-

REF

ages due to system gain errors in system calibration routines) with­out introducing errors due to overloading the analog modulator
or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V

/GAIN without overloading the

REF

analog modulator or overflowing the digital filter.

OFFSET CALIBRATION RANGE

In the system calibration modes, the AD7730 calibrates its
offset with respect to the analog input. The Offset Calibration
Range specification defines the range of voltages the AD7730
can accept and still accurately calibrate offset.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7730 can accept in the
system calibration mode and still calibrate full scale correctly.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence
to the AD7730’s analog input define the analog input range.
The input span specification defines the minimum and maxi­mum input voltages, from zero to full scale, the AD7730 can
accept and still accurately calibrate gain.

AD7730/AD7730L

OUTPUT NOISE AND RESOLUTION SPECIFICATION

The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or
dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These
options are discussed in more detail in later sections. The chop mode has the advantage of lower drift numbers and better noise im­munity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the majority
of weigh-scale users of the AD7730 will operate the part in chop mode to avail themselves of the excellent drift performance and
noise immunity when chopping is enabled. The following tables outline the noise performance of the part in both chop and nonchop
modes over all input ranges for a selection of output rates. Settling time refers to the time taken to get an output that is 100% settled
to new value.

Output Noise (CHP = 1)

This mode is the primary mode of operation of the device. Table I shows the output rms noise for some typical output update rates
and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of

4.9152 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is
selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to-peak resolution in counts for
the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5
LSB). It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a
six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges while the
numbers in Table II will change. To calculate the numbers for Table II for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.

Table I. Output Noise vs. Input Range and Update Rate (CHP = 1)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 680 mV = 640 mV = 620 mV = 610 mV

50 Hz 1.97 Hz 2048 460 ms 60 ms 115 75 55 40
100 Hz 3.95 Hz 1024 230 ms 30 ms 155 105 75 60
150 Hz 5.92 Hz 683 153 ms 20 ms 200 135 95 70
200 Hz* 7.9 Hz 512 115 ms 15 ms 225 145 100 80
400 Hz 15.8 Hz 256 57.5 ms 7.5 ms 335 225 160 110

*Power-On Default

Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1)

Peak-to-Peak Resolution in Counts (Bits)

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 680 mV = 640 mV = 620 mV = 610 mV

50 Hz 1.97 Hz 2048 460 ms 60 ms 230k (18) 175k (17.5) 120k (17) 80k (16.5)
100 Hz 3.95 Hz 1024 230 ms 30 ms 170k (17.5) 125k (17) 90k (16.5) 55k (16)
150 Hz 5.92 Hz 683 153 ms 20 ms 130k (17) 100k (16.5) 70k (16) 45k (15.5)
200 Hz* 7.9 Hz 512 115 ms 15 ms 120k (17) 90k (16.5) 65k (16) 40k (15.5)
400 Hz 15.8 Hz 256 57.5 ms 7.5 ms 80k (16.5) 55k (16) 40k (15.5) 30k (15)

*Power-On Default

Output Noise (CHP = 0)

Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in non­chopping mode (CHP of Filter Register = 0) with a master clock frequency of 4.9152 MHz. These numbers are typical and are gen­erated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register.
Table IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets
are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table
IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms
noise, but on peak-to-peak noise.

The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the
same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges while the
numbers in Table IV will change. To calculate the number for Table IV for unipolar input ranges simply divide the peak-to-peak
resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits.

–10–

REV. A

AD7730/AD7730L

Table III. Output Noise vs. Input Range and Update Rate (CHP = 0)

Typical Output RMS Noise in nV

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 680 mV = 640 mV = 620 mV = 610 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 160 110 80 60
200 Hz 7.8 Hz 1536 125 ms 20 ms 190 130 95 75
300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 235 145 100 80
600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 300 225 135 110
1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 435 315 210 150

Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0)

Peak-to-Peak Resolution in Counts (Bits)

Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range
Data Rate Frequency Word Normal Mode Fast Mode = 680 mV = 640 mV = 620 mV = 610 mV

150 Hz 5.85 Hz 2048 166 ms 26.6 ms 165k (17.5) 120k (17) 80k (16.5) 55k (16)
200 Hz 7.8 Hz 1536 125 ms 20 ms 140k (17) 100k (16.5) 70k (16) 45k (15.5)
300 Hz 11.7 Hz 1024 83.3 ms 13.3 ms 115k (17) 90k (16.5) 65k (16) 40k (15.5)
600 Hz 23.4 Hz 512 41.6 ms 6.6 ms 90k (16.5) 60k (16) 50k (15.5) 30k (15)
1200 Hz 46.8 Hz 256 20.8 ms 3.3 ms 60k (16) 43k (15.5) 32k (15) 20k (14.5)

ON-CHIP REGISTERS

The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized
in Figure 4 and in Table V and described in detail in the following sections.

DIN

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DIN

DIN

DIN

DIN

DIN

DIN

DIN

COMMUNICATIONS REGISTER

RS2 RS1 RS0

STATUS REGISTER

DATA REGISTER

MODE REGISTER

FILTER REGISTER

DAC REGISTER

OFFSET REGISTER (x3)

GAIN REGISTER (x3)

TEST REGISTER

REGISTER

SELECT

DECODER

REV. A

Figure 4. Register Overview

–11–

AD7730/AD7730L

Table V. Summary of On-Chip Registers

Power-On/Reset

Register Name Type Size Default Value Function

Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through
Register the Communications Register. This controls whether

WEN ZERO RW1 RW0 ZERO RS2 RS1 RS0

Status Register Read Only 8 Bits CX Hex Provides status information on conversions, calibra-

RDY STDY STBY NOREF MS3 MS2 MS1 MS0

Data Register Read Only 16 Bits or 24 Bits 000000 Hex Provides the most up-to-date conversion result from

Mode Register Read/Write 16 Bits 01B0 Hex Controls functions such as mode of operation, uni-

MD2 MD1 MD0 B/U DEN D1 D0 WL

HIREF ZERO RN1 RN0 CLKDIS BO CH1 CH0

subsequent operations are read or write operations
and also selects the register for that subsequent
operation. Most subsequent operations return con­trol to the Communications Register except for the
continuous read mode of operation.

tions, settling to step inputs, standby operation and
the validity of the reference voltage.

the part. Register length can be programmed to be
16 bits or 24 bits.

polar/bipolar operation, controlling the function of
AIN2(+)/D1 and AIN2(-)/D0, burnout current,
Data Register word length and disabling of MCLK
OUT. It also contains the reference selection bit, the
range selection bits and the channel selection bits.

Filter Register Read/Write 24 Bits 200010 Hex Controls the amount of averaging in the first stage

filter, selects the fast step and skip modes and con-

SF11 SF10 SF9 SF8 SF7 SF6 SF5 SF4
SF3 SF2 SF1 SF0 ZERO ZERO SKIP FAST
ZERO ZERO AC CHP DL3 DL2 DL1 DL0

trols the ac excitation and chopping modes on the
part.

DAC Register Read/Write 8 Bits 20 Hex Provides control of the amount of correction per-

formed by the Offset/TARE DAC.

ZERO ZERO DAC5 DAC4 DAC3 DAC2 DAC1 DAC0

Offset Register Read/Write 24 Bits 800000 Hex Contains a 24-bit word which is the offset calibration

coefficient for the part. The contents of this register
are used to provide offset correction on the output
from the digital filter. There are three Offset Regis­ters on the part and these are associated with the
input channels as outlined in Table XIII.

Gain Register Read/Write 24 Bits 59AEE7 Hex Contains a 24-bit word which is the gain calibration

coefficient for the part. The contents of this register
are used to provide gain correction on the output
from the digital filter. There are three Gain Registers
on the part and these are associated with the input
channels as outlined in Table XIII.

Test Register Read/Write 24 Bits 000000 Hex Controls the test modes of the part which are used

when testing the part. The user is advised not to

change the contents of this register.

–12–

REV. A

AD7730/AD7730L

Communications Register (RS2–RS0 = 0, 0, 0)

The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, the type of read operation, and to which register this operation takes place. For single-shot read or write operations,
once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op­eration to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7730
is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is
lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7730 to this default state by resetting the
part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denot­ing the bits are in the Communications Register. CR7 denotes the first bit of the data stream.

Table VI. Communications Register

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN ZERO RW1 RW0 ZERO RS2 RS1 RS0

Bit Bit
Location Mnemonic Description

CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications

Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent
bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is writ-

ten to the WEN bit, the next seven bits will be loaded to the Communications Register.
CR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7730.
CR5, CR4 RW1, RW0 Read/Write Mode Bits. These two bits determine the nature of the subsequent read/write opera-

tion. Table VII outlines the four options.

Table VII. Read/Write Mode

RW1 RW0 Read/Write Mode

0 0 Single Write to Specified Register
0 1 Single Read of Specified Register
1 0 Start Continuous Read of Specified Register
1 1 Stop Continuous Read Mode

With 0, 0 written to these two bits, the next operation is a write operation to the register specified by

bits RS2, RS1, RS0. Once the subsequent write operation to the specified register has been com-

pleted, the part returns to where it is expecting a write operation to the Communications Register.

With 0,1 written to these two bits, the next operation is a read operation of the register specified

by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been

completed, the part returns to where it is expecting a write operation to the Communications

Register.

Writing 1,0 to these bits, sets the part into a mode of continuous reads from the register speci-

fied by bits RS2, RS1, RS0. The most likely registers with which the user will want to use this

function are the Data Register and the Status Register. Subsequent operations to the part will

consist of read operations to the specified register without any intermediate writes to the Com-

munications Register. This means that once the next read operation to the specified register has

taken place, the part will be in a mode where it is expecting another read from that specified

register. The part will remain in this continuous read mode until 30 Hex has been written to the

Communications Register.

When 1,1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous read

mode is stopped and the part returns to where it is expecting a write operation to the Communi-

cations Register. Note, the part continues to look at the DIN line on each SCLK edge during

continuous read mode to determine when to stop the continuous read mode. Therefore, the user

must be careful not to inadvertently exit the continuous read mode or reset the AD7730 by

writing a series of 1s to the part. The easiest way to avoid this is to place a logic 0 on the DIN

line while the part is in continuous read mode. Once the part is in continuous read mode, the

user should ensure that an integer multiple of 8 serial clocks should have taken place before

attempting to take the part out of continuous read mode.

REV. A

–13–

AD7730/AD7730L

Bit Bit
Location Mnemonic Description

CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7730.
CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select

which register type the next read or write operation operates upon as shown in Table VIII.

Table VIII. Register Selection

RS2 RS1 RS0 Register

0 0 0 Communications Register (Write Operation)
0 0 0 Status Register (Read Operation)
0 0 1 Data Register
0 1 0 Mode Register
0 1 1 Filter Register
1 0 0 DAC Register
1 0 1 Offset Register
1 1 0 Gain Register
1 1 1 Test Register

Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex

The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig­nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7
denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number
in brackets indicates the power-on/reset default status of that bit.

Table IX. Status Register

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY (1) STDY (1) STBY (0) NOREF (0) MS3 (X) MS2 (X) MS1 (X) MS0 (X)

Bit Bit
Location Mnemonic Description

SR7 RDY Ready Bit. This bit provides the status of the RDY flag from the part. The status and function of

this bit is the same as the RDY output pin. A number of events set the RDY bit high as indi­cated in Table XVIII.

SR6 STDY Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter is

in

FASTStep

remains high as the initial conversion results become available. The RDY output and bit are set
low on these initial conversions to indicate that a result is available. If the STDY is high, however,
it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the
FIR filter has fully settled, the STDY bit will go low coincident with RDY. If the part is never placed
into its
not cleared by subsequent Data Register reads.

A number of events set the STDY bit high as indicated in Table XVIII. STDY is set high along
with RDY by all events in the table except a Data Register read.

SR5 STBY Standby Bit. This bit indicates whether the AD7730 is in its Standby Mode or normal mode of

operation. The part can be placed in its standby mode using the STANDBY input pin or by
writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit
is 0 assuming the STANDBY pin is high.

SR4 NOREF No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.3 V, or

either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on comple­tion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion
of a calibration, updating of the calibration registers is inhibited.

SR3–SR0 MS3–MS0 These bits are for factory use. The power-on/reset status of these bits vary, depending on the

factory-assigned number.

mode (see Filter Register section) and responding to a step input, the STDY bit

FASTStep

mode, the STDY bit will go low at the first Data Register read and it is

–14–

REV. A

AD7730/AD7730L

Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex

The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig­ure 5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24bits
wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low
when the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16bits or
24 bits) have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit
will go high for at least 100 × t
the Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low.

If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter­face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7730.

Mode Register (RS2–RS0 = 0, 1, 0); Power On/Reset Status: 01B0 Hex

The Mode Register is a 16-bit register from which data can be read or to which data can be written. This register configures
the operating modes of the AD7730, the input range selection, the channel selection and the word length of the Data Register.
Table X outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are
in the Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default
status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writ­ing to the registers on the part.

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

MD2 (0) MD1 (0) MD0 (0) B/U (0) DEN (0) D1 (0) D0 (0) WL (1)

, indicating when a read from the Data Register should not be initiated to avoid a transfer from

CLK IN

Table X. Mode Register

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

HIREF (1) ZERO (0) RN1 (1) RN0 (1) CLKDIS (0) BO (0) CH1 (0) CH0 (0)

Bit Bit
Location Mnemonic Description

MR15–MR13 MD2–MD0 Mode Bits. These three bits determine the mode of operation of the AD7730 as outlined in

Table XI. The modes are independent, such that writing new mode bits to the Mode Register
will exit the part from the mode in which it is operating and place it in the new requested mode
immediately after the Mode Register write. The function of the mode bits is described in more
detail below.

Table XI. Operating Modes

MD2 MD1 MD0 Mode of Operation

0 0 0 Sync (Idle) Mode Power-On/Reset Default
0 0 1 Continuous Conversion Mode
0 1 0 Single Conversion Mode
0 1 1 Power-Down (Standby) Mode
1 0 0 Internal Zero-Scale Calibration
1 0 1 Internal Full-Scale Calibration
1 1 0 System Zero-Scale Calibration
1 1 1 System Full-Scale Calibration

REV. A

–15–

AD7730/AD7730L

MD2 MD1 MD0 Operating Mode

0 0 0 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not

processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC
input pin. However, exerting the SYNC pin does not actually force these mode bits to 0, 0, 0. The part
returns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the
default condition of these bits after Power-On/Reset.

0 0 1 Continuous Conversion Mode. In this mode, the AD7730 is continuously processing data and providing

conversion results to the Data Register at the programmed output update rate (as determined by the
Filter Register). For most applications, this would be the normal operating mode of the AD7730.

0 1 0 Single Conversion Mode. In this mode, the AD7730 performs a single conversion, updates the Data

Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion
on the AD7730 in this mode will not be provided until the full settling time of the filter has elapsed.

0 1 1 Power-Down (Standby) Mode. In this mode, the AD7730 goes into its power-down or standby state.

Placing the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting
STANDBY does not actually force these mode bits to 0, 1, 1.

1 0 0 Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by

CH1 and CH0 of the Mode Register. This zero-scale self-calibration is performed at the selected gain on
internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the part updates the
contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2, MD1 and
MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low
when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready
for further operations.

1 0 1 Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by

CH1 and CH0 of the Mode Register. This full-scale self-calibration is performed at the selected gain on
an internally-generated full-scale signal. When this full-scale self-calibration is complete, the part updates
the contents of the appropriate Gain Calibration Register and Offset Calibration Register and returns to
Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when
calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the
part is back in Sync Mode and ready for further operations.

1 1 0 Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected

by CH1 and CH0 of the Mode Register. Calibration is performed at the selected gain on the input volt­age provided at the analog input during this calibration sequence. This input voltage should remain
stable for the duration of the calibration. When this zero-scale system calibration is complete, the part
updates the contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2,
MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and
return low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and
ready for further operations.

1 1 1 Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input

channel. Calibration is performed at the selected gain on the input voltage provided at the analog input
during this calibration sequence. This input voltage should remain stable for the duration of the calibra­tion. When this full-scale system calibration is complete, the part updates the contents of the appropriate
Gain Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0.
The RDY output and bit go high when calibration is initiated and return low when this full-scale calibra­tion is complete to indicate that the part is back in Sync Mode and ready for further operations.

–16–

REV. A