Analog Devices AD73411 Datasheet

Low-Power

a

Analog Front End with DSP Microcomputer

FEATURES

AFE PERFORMANCE
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
76 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 ␮s Typ per ADC Channel,

50 ␮s Typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference

DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS

Sustained Performance
AD73411-80

80K Bytes of On-Chip RAM, Configured as 16K Words

Program Memory RAM and 16K Words

Data Memory RAM
AD73411-40

40K Bytes of On-Chip RAM, Configured as 8K Words

Program Memory RAM and 8K Words

Data Memory RAM

DATA

ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

AD73411

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTERMACALU

REF

MEMORY

16K PM

(OPTIONAL

(OPTIONAL

8K)

SERIAL PORTS

SPORT 0

SPORT 1

SERIAL PORT

SPORT 2

ADC DAC

ANALOG FRONT END

SECTION

16K DM

8K)

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

GENERAL DESCRIPTION

The AD73411 is a single device incorporating a single analog front
end (AFE) and a microcomputer optimized for digital signal
processing (DSP) and other high-speed numeric processing
applications.

The AD73411’s analog front end (AFE) section is suitable for
general-purpose applications including speech and telephony.
The AFE section features a 16-bit A/D converter and a 16-bit
D/A converter. Each converter provides 76 dB signal-to-noise
ratio over a voiceband signal bandwidth.

The AD73411 is particularly suitable for a variety of applications
in the speech and telephony area, including low bit rate, high­quality compression, speech enhancement, recognition, and
synthesis. The low group delay characteristic of the AFE makes
it suitable for single or multichannel active control applications.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges of 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single supply
operation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The sampling rate of the AFE is programmable with four sepa­rate settings offering 64, 32, 16, and 8 kHz sampling rates (from
a master clock of 16.384 MHz) while the serial port (SPORT2)
allows easy expansion of the number of I/O channels by cascad­ing extra AFEs external to the AD73411.

The AD73411’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen­erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.

The AD73411-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73411-40 integrates
40K bytes of on-chip memory configured as 8K words (24­bit) of program RAM, and 8K words (16-bit) of data RAM.
Power-down circuitry is also provided to meet the low power
needs of battery-operated portable equipment. The AD73411
is available in a 119-ball PBGA package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD73411–SPECIFICATIONS

(AVDD = DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f

1

f

= 64 kHz; TA = T

SAMP

MIN

to T

, unless otherwise noted.)

MAX

= 16.384 MHz,

MCLK

Parameter Min Typ Max Unit Test Conditions/Comments

AFE SECTION

REFERENCE

REFCAP

Absolute Voltage, V

REFCAP

1.08 1.2 1.32 V

REFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from

REFOUT REFCAP to AGND2

Typical Output Impedance 145 Ω

Absolute Voltage, V

REFOUT

ADC SPECIFICATIONS

Maximum Input Range at VIN

2, 3

1.08 1.2 1.32 V Unloaded

1.578 V p-p Measured Differentially
–2.85 dBm Max Input = (1.578/1.2) × V

REFCAP

Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially

(0 dBm0) –6.02 dBm

Absolute Gain

PGA = 0 dB –2.2 –0.6 +1.0 dB 1.0 kHz, 0 dBm0

PGA = 38 dB –1.0 dB 1.0 kHz, 0 dBm0
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion) Refer to Figure ?

PGA = 0 dB 71 76 dB 300 Hz to 3400 Hz;

70 74 dB 0 Hz to f

72 dB 300 Hz to 3400 Hz; f
56 dB 0 Hz to f

SAMP

SAMP

/2

/2; f

SAMP

SAMP

= 64 kHz

= 64 kHz

PGA = 38 dB 60 dB 300 Hz to 3400 Hz;

59 dB 0 Hz to f

SAMP

/2

Total Harmonic Distortion

PGA = 0 dB –85 –75 dB 300 Hz to 3400 Hz

PGA = 38 dB –85 dB 300 Hz to 3400 Hz
Intermodulation Distortion –82 dB PGA = 0 dB
Idle Channel Noise –76 dBm0 PGA = 0 dB
Crosstalk –100 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0

DAC Input at Idle
DC Offset –20 +2 +25 mV PGA = 0 dB
Power Supply Rejection –84 dB Input Signal Level at AVDD and DVDD

Group Delay
Input Resistance at PGA

4, 5

2, 4, 6

DAC SPECIFICATIONS

Maximum Voltage Output Swing

25 µsf
45 kΩ DMCLK = 16.384 MHz

2

Pins 1.0 kHz, 100 mV p-p Sine Wave

= 64 kHz

SAMP

Single-Ended 1.578 V p-p PGA = 6 dB

–2.85 dBm Max Output = (1.578/1.2) × V

REFCAP

Differential 3.156 V p-p PGA = 6 dB

3.17 dBm Max Output = 2 × ((1.578/1.2) × V

REFCAP

Nominal Voltage Output Swing (0 dBm0)

Single-Ended 1.0954 V p-p PGA = 6 dB

–6.02 dBm

Differential 2.1909 V p-p PGA = 6 dB

0 dBm

Output Bias Voltage

4

1.08 1.2 1.32 V REFOUT Unloaded
Absolute Gain –1.8 –0.7 +0.4 dB 1.0 kHz, 0 dBm0; Unloaded
Gain Tracking Error ± 0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)

PGA = 0 dB 70 77 dB 300 Hz to 3400 Hz

76 dB 300 Hz to 3400 Hz; f

SAMP

= 64 kHz

PGA = 6 dB 77 dB 300 Hz to 3400 Hz

77 dB 300 Hz to 3400 Hz; f

SAMP

= 64 kHz

Total Harmonic Distortion at 0 dBm0

PGA = 0 dB –80 –70 dB

PGA = 6 dB –80 dB
Intermodulation Distortion –76 dB PGA = 0 dB
Idle Channel Noise –82 dBm0 PGA = 0 dB
Crosstalk –100 dB ADC Input Signal Level: AGND; DAC

Output Signal Level: 1.0 kHz, 0 dBm0

–2–

REV. 0

AD73411

Parameter Min Typ Max Unit Test Conditions/Comments

DAC SPECIFICATIONS (Continued)

Power Supply Rejection –81 dB Input Signal Level at AVDD and DVDD

Group Delay

Output DC Offset

4, 5

2, 7

25 µsf
50 µsf

–30 +5 +50 mV PGA = 6 dB

LOGIC INPUTS

, Input High Voltage DVDD – 0.8 DVDD V

V

INH

, Input Low Voltage 0 0.8 V

V

INL

IIH, Input Current –10 +10 µA

LOGIC OUTPUT

VOH, Output High Voltage DVDD – 0.4 DVDD V |IOUT| ≤ 100 µA

, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µA

V

OL

Three-State Leakage Current –10 +10 µA

POWER SUPPLIES

AVDD 3.0 3.6 V
DVDD 3.0 3.6 V

9

I

DD

NOTES

1

Operating temperature range is as follows: –20°C to +85°C. Therefore, T

2

Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).

3

At input to sigma-delta modulator of ADC.

4

Guaranteed by design.

5

Overall group delay will be affected by the sample rate and the external digital filtering.

6

The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 1011)/DMCLK.

7

Between VOUTP and VOUTN.

8

At VOUT output.

9

Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.

Specifications subject to change without notice.

= –20°C and T

MIN

= +85°C.

MAX

Pins: 1.0 kHz, 100 mV p-p Sine Wave

= 64 kHz; Interpolator Bypassed

SAMP

= 64 kHz

SAMP

See Table I

REV. 0

–3–

AD73411–SPECIFICATIONS

(AVDD = DVDD = VDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f
f

= 64 kHz; TA = T

SAMP

MIN

to T

, unless otherwise noted.)

MAX

= 16.384 MHz,

MCLK

Parameter Test Conditions Min Typ Max Unit

DSP SECTION
V

IH

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

I

OZH

I

OZL

I

DD

I

DD

C

I

C

O

NOTES

1

Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

2

Input only pins: RESET, BR, DR0, DR1, PWD.

3

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

5

Although specified for TTL outputs, all AD73411 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

6

Guaranteed but not tested.

7

Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

8

0 V on BR.

9

Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.

10

VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

11

IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.

12

Applies to PBGA package type.

13

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

Hi-Level Input Voltage
Hi-Level CLKIN Voltage @ VDD = max 2.2 V
Lo-Level Input Voltage
Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Three-State Leakage Current

Three-State Leakage Current

Supply Current (Idle)

Supply Current (Dynamic)

Input Pin Capacitance

Output Pin Capacitance

1, 2

1, 3

1, 4, 5

1, 4, 5

3

3

9

3, 6, 12

6, 7, 12, 13

@ VDD = max 2.0 V

@ VDD = min 0.8 V
@ VDD = min
I

= –0.5 mA 2.4 V

OH

@ VDD = min

= –100 µA

I

OH

6

VDD – 0.3 V
@ VDD = min
I

= 2 mA 0.4 V

OL

@ VDD = max
V

= VDD max 10 µA

IN

@ VDD = max

= 0 V 10 µA

V

7

7

11

IN

@ VDD = max
V

= VDD max

IN

@ VDD = max
V

IN

@ VDD = 3.3
t

CK

t

CK

t

CK

8

= 0 V

= 19 ns
= 25 ns
= 30 ns

10

10

10

@ VDD = 3.3
T

= 25°C

AMB

t

= 19 ns

CK

= 25 ns

t

CK

t

= 30 ns

CK

10

10

10

8

10 µA

10 µA

12 mA
11 mA
10 mA

45 mA
43 mA
36 mA

@ VIN = 2.5 V

= 1.0 MHz

f

IN

T

= 25°C8pF

AMB

@ VIN = 2.5 V

= 1.0 MHz

f

IN

T

= 25°C8pF

AMB

–4–

REV. 0

AD73411

POWER CONSUMPTION

Parameter Typ Max SE MCLK On Test Conditions

AFE SECTION

ADC Only On 7 8 1 Yes REFOUT Disabled
ADC and DAC On 11 12.5 1 Yes REFOUT Disabled
REFCAP Only On 0.65 1.00 0 No REFOUT Disabled
REFCAP and 2.7 3.8 0 No

REFOUT Only On
All AFE Sections Off 0.6 0.75 0 Yes MCLK Active Levels Equal to 0 V and DVDD
All AFE Sections Off 5 µA 30 µA 0 No Digital Inputs Static and Equal to 0 V or DVDD

DSP SECTION

Idle Mode 6.4
Dynamic 43

NOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.

TIMING CHARACTERISTICS–AFE SECTION

Parameter Limit Unit Description

Clock Signals See Figure 1

t

1

t

2

t

3

Serial Port See Figures ? and ?

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

Specifications subject to change without notice.

61 ns min 16.384 MHz AMCLK Period

24.4 ns min MCLK Width High

24.4 ns min MCLK Width Low

t

1

0.4 × t

0.4 × t

1

1

ns min SCLK Period (SCLK = AMCLK)
ns min SCLK Width High

ns min SCLK Width Low
20 ns min SDI/SDIFS Setup Before SCLK Low
0 ns min SDI/SDIFS Hold After SCLK Low
10 ns max SDOFS Delay from SCLK High
10 ns min SDOFS Hold After SCLK High
10 ns min SDO Hold After SCLK High
10 ns max SDO Delay from SCLK High
30 ns max SCLK Delay from MCLK

REV. 0

–5–

AD73411

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –20°C to +85°C

Reflow Soldering

Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . . 225°C

Time at Maximum Temperature . . . . . . . . . . . . . . . . .15 sec

Maximum Temperature Ramp Rate . . . . . . . . . . . . 1.3°C/sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Storage Temperature Range . . . . . . . . . . . . –40°C to +125°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

PBGA, θ

Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W

JA

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD73411BB-80 –20°C to +85°C 119-Ball Plastic Ball Grid Array B-119
AD73411BB-40 –20°C to +85°C 119-Ball Plastic Ball Grid Array B-119

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73411 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

PBGA BALL CONFIGURATION

1

A

IRQE/ PF4

B

IRQL0/ PF5 PMS WR

IRQL1/ PF6 IOMS RD

C

IRQ2/ PF7 CMS BMS

D

DT0 TFS0 RFS0 A3/ IAD2 A2/ IAD1 A1/IAD0 A0

E

DR0 SCLK0 DT1/F0 PWDACK

F

TFS1/IRQ1 RFS1/IRQ0

G

SCLK1

H

EMS

J

K

ELOUT ELIN

BG D3 /IACK

L

EBG

M

N

BR

EBR

P

SDO SDOFS SDIFS SDI SE REFCAP REFOUT

R

T

VINP NC

AGND

U

NOTES:
VDD (INT) – DSP CORE SUPPLY
VDD (EXT) – DSP I/O DRIVER SUPPLY
BOTH VDD (INT) AND VDD (EXT) SHOULD BE POWERED FROM THE SAME SUPPLY.

23

DMS

ERESET RESET

EE ECLK D23 D22 D21 D20

D2/ IAD15

D1/IAD14 VDD (INT)

D0/ IAD13 DVDD DGND

AVDD NC NC VOUTP VOUTN NC

VDD (INT) CLKIN A11/IAD10 A7/ IAD6 A4/ IAD3

DR1/FI GND

EINT

D5/ IAL D8 D9 D12 D15

D4/ IS D7/ IWR

VINN NC NC NC NC

4

XTAL A12/ IAD11 A8/IAD7 A5 /IAD4

VDD (EXT) A13/ IAD12 A9/ IAD8 GND

CLKOUT GND A10 /IAD9 A6/ IAD5

PF3 FL0 FL1 FL2

D19 D18 D17 D16

D6/ IRD

TOP VIEW

57

BGH

PWD

VDD (EXT) D11 D14

GND D10 D13

ARESET

6

MODE A /PF0 MODE B /PF1

VDD (EXT) MODE C /PF2

SCLK2 AMCLK

–6–

REV. 0

AD73411

PBGA BALL FUNCTION DESCRIPTIONS

BGA

Mnemonic Location Function

VINP T1 This pin allows direct access to the positive input of the sigma-delta modulator.
VINN T3 This pin allows direct access to the negative input of the sigma-delta modulator.
REFOUT R7 Buffered Reference Output, which has a nominal value of 1.2 V.
REFCAP R6 A Bypass Capacitor to AGND of 0.1 µF is required for the on-chip reference. The capacitor should be

fixed to this pin.
DGND P4 AFE Digital Ground/Substrate Connection.
DVDD P3 AFE Digital Power Supply Connection.
ARESET P5 Active Low Reset Signal. This input resets the entire analog front end, resetting the control registers and

clearing the digital circuitry.
SCLK2 P6 Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data

or control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the

frequency of the master clock (AMCLK) divided by an integer number—this integer number being the product

of the external master clock rate divider and the serial clock rate divider.
AMCLK P7 AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP

and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the

DSP section.
SDO R1 Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on

the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS R2 Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK

period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.

SDOFS is in three-state when SE is low.
SDIFS R3 Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK

period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and

is ignored when SE is low.
SDI R4 Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked

on the negative edge of SCLK. SDI is ignored when SE is low.
SE R5 SPORT2 Enable. Asynchronous input enable pin for SPORT2. When SE is set low by the DSP, the output

pins of SPORT2 are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order

to decrease power dissipation. When SE is brought high, the control and data registers of SPORT2 are at

their original values (before SE was brought low), however the timing counters and other internal regis-

ters are at their reset values.
AGND U1 AFE Analog Ground/Substrate Connection.
AVDD U2 AFE Analog Power Supply Connection.
VOUTP U5 Analog Output from the Positive Terminal of the Output.
VOUTN U6 Analog Output from the Negative Terminal of the Output.

RESET H3 (Input) Processor Reset Input.
BR N1 (Input) Bus Request Input.
BG L1 (Output) Bus Grant Output.
BGH F5 (Output) Bus Grant Hung Output.
DMS A2 (Output) Data Memory Select Output.
PMS B2 (Output) Program Memory Select Output.
IOMS C2 (Output) Memory Select Output.
BMS D3 (Output) Byte Memory Select Output.
CMS D2 (Output) Combined Memory Select Output.
RD C3 (Output) Memory Read Enable Output.
WR B3 (Output) Memory Write Enable Output.
IRQ2/ (Input) Edge- or Level-Sensitive Interrupt Request

PF7 D1 (Input/Output)

IRQL1/ (Input) Level-Sensitive Interrupt Requests

PF6 C1 (Input/Output) Programmable I/O Pin.

Programmable I/O Pin.

1

1

.

.

REV. 0

–7–

AD73411

PBGA BALL FUNCTION DESCRIPTIONS (Continued)

Mnemonic Location Function

BGA

1

IRQL0/ (Input) Level-Sensitive Interrupt Requests
PF5 B1 (Input/Output) Programmable I/O Pin.
IRQE/ (Input) Edge-Sensitive Interrupt Requests

.

1

.

PF4 A1 (Input/Output) Programmable I/O Pin.
PF3 H4 (Input/Output) Programmable I/O Pin During Normal Operation.

Mode C/ (Input) Mode Select Input—Checked Only During RESET.
PF2 G7 (Input/Output) Programmable I/O Pin During Normal Operation.
Mode B/ (Input) Mode Select Input—Checked Only During RESET .
PF1 F7 (Input/Output) Programmable I/O Pin During Normal Operation.
Mode A/ (Input) Mode Select Input—Checked Only During RESET.
PF0 F6 (Input/Output) Programmable I/O Pin During Normal Operation.
CLKIN A4 (Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation
XTAL B4 nor operated below 10 MHz during normal operation.
CLKOUT D4 (Output) Processor Clock Output.
SPORT0

TFS0 E2 (Input/Output) SPORT0 Transmit Frame Sync.
RFS0 E3 (Input/Output) SPORT0 Receive Frame Sync.
DT0 E1 (Output) SPORT0 Transmit Data.
DR0 F1 (Input) SPORT0 Receive Data.
SCLK0 F2 (Input/Output) SPORT0 Serial Clock.

SPORT1

TFS1/ (Input/Output) SPORT1 Transmit Frame Sync.
IRQ1 G1 (Input) Edge or Level Sensitive Interrupt.
RFS1 (Input/Output) SPORT1 Receive Frame Sync.
IRQ0 G2 (Input) Edge or Level Sensitive Interrupt.
DT1/ (Output) SPORT1 Transmit Data.
FO F3 (Output) Flag Out
DR1/ (Input) SPORT1 Receive Data.
FI G3 (Input) Flag In

2

.

2

.

SCLK1 H1 (Input/Output) SPORT1 Serial Clock.
FL0 H5 (Output) Flag 0.
FL1 H6 (Output) Flag 1.
FL2 H7 (Output) Flag 2.
VDD(INT) A3 (Input) DSP Core Supply.

N3

VDD(EXT) C4 (Input) DSP I/O Interface Supply.

G6
M5

GND C7 DSP Ground.

D5
G4
N5

EZ-ICE Port

ERESET H2

EMS J1

EE J2

ECLK J3

ELOUT K1

ELIN K2

EINT K3

EBR P1

EBG M1

A

ddress Bus A0–E7; A1/IAD0–E6; A2/IAD1–E5; A3/IAD2–E4; A4/IAD3–A7; A5/IAD4–B7; A6/IAD5–D7; A7/IAD6–A6;

A8/IAD7–B6; A9/IAD8–C6; A10/IAD9–D6; A11/IAD10–A5; A12/IAD11–B5; A13/IAD12–C5

Data Bus D0/IAD13–P2; D1/IAD14–N2; D2/IAD15–M2; D3/IACK–L2; D4/IS–M3; D5/IAL–L3; D6/IRD–N4; D7/IWR–M4;

D8–L4; D9–L5; D10–N6; D11–M6; D12–L6; D13–N7; D14–M7; D15–L7; D16–K7; D17–K6; D18–K5;
D19–K4; D20–J7; D21–J6; D22–J5; D23–J4

NOTES

1

Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt

vector address when the pin is asserted, either by external devices, or set as a programmable flag.

2

SPORT configuration determined by the DSP System Control Register. Software configurable.

–8–

REV. 0

AD73411

ARCHITECTURE OVERVIEW

The AD73411 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro­cessor cycle. The AD73411 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.

DATA

ADDRESS

GENERATORS

DAG 2

DAG 1

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTERMACALU

REF

POWER-DOWN

CONTROL

MEMORY

16K DM

16K PM

(OPTIONAL

(OPTIONAL

SPORT 0

ANALOG FRONT END

8K)

SERIAL PORTS

SPORT 1

SERIAL PORT

SPORT 2

ADC DAC

SECTION

8K)

PROGRAMMABLE

I/O

AND

FLAGS

TIMER

FULL MEMORY

MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the AD73411. The pro­cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units directly process 16-bit data and have provi­sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi­tives are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations with 40 bits of
accumulation. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.

The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these com­putational units. The sequencer supports conditional jumps,
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73411 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The AD73411 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-sensitive,
and three configurable), and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.

Each port can generate an internal programmable serial clock or
accept an external serial clock.

The AD73411 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro­cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Analog Front End

The AFE section is configured as a separate block that is normally
connected to either SPORT0 or SPORT1 of the DSP section.
As it is not hardwired to either SPORT, users have total flexibil­ity in how they wish to allocate system resources to support the
AFE. It is also possible to further expand the number of analog
I/O channels connected to the SPORT by cascading other single
or dual channel AFEs (AD73311 or AD73322) external to the
AD73411.

REV. 0

–9–

AD73411

DVDDAVDD2AVDD1

VINP

VINN

VOUTP

VOUTN

REFCAP

REFOUT

ANALOG

LOOPBACK/

SINGLE-ENDED

ENABLE

+6/–15dB

PGA

0/38dB

PGA

CONTINUOUS

TIME

LOW-PASS FILTER

REFERENCE

AGND1

AGND2

ANALOG

SIGMA-DELTA

MODULATOR

SWITCHED­CAPACITOR

LOW-PASS FILTER

Figure 2. Functional Block Diagram of Analog Front End Section

The AFE is configured as a single I/O channel (similar to that of
the discrete AD73311L; refer to the AD73311L data sheet for
more details) having a 16-bit sigma-delta-based ADC and DAC.
Both ADC and DAC share a common reference whose nominal
value is 1.2 V. Figure 2 shows a block diagram of the AFE sec­tion of the AD73411. It shows an ADC and DAC as well as a
common reference. Communication to both channels is handled
by the SPORT2 block which interfaces to either SPORT0 or
SPORT1 of the DSP section.

The I/O channel features fully differential inputs and outputs.
The input section allows direct connection to the internal Pro­grammable Gain Amplifier at the input of the sigma-delta
ADC section. The input section also features programmable differ­ential channel inversion and configuration of the differential
input as two separate single-ended inputs. The ADC features a
second order sigma-delta modulator which samples at MCLK/8.
Its bitstream output is filtered and decimated by a Sinc-cubed
decimator to provide a sample rate selectable from 64 kHz,
32 kHz, 16 kHz or 8 kHz (based on an MCLK of 16.384 MHz).

The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of MCLK/8. The digital sigma-delta
modulator’s output bitstream is fed to a single-bit DAC whose
output is reconstructed/filtered by two stages of low-pass filtering
(switched capacitor and continuous time) before being applied
to the differential output driver.

FUNCTIONAL DESCRIPTION
Encoder Channel

The encoder channel consists of an input configuration block, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti­alias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.

Input Configuration Block

The input configuration block consists of a multiplexing arrange­ment that allows selection of various input configurations. This
includes ADC input selection from either the VINP, VINN pins

SDI

1-BIT

DAC

AD73411

DIGITAL

SIGMA-DELTA

MODULATOR

DECIMATOR

INTERPOLATOR

DGND

SERIAL

I/O

PORT

SDIFS

SCLK

SDO

SDOFS

SE

MCLK

RESET

or from the DAC output via the Analog Loop-Back (ALB)
arrangement. Differential inputs can be inverted and it is also
possible to use the device in single-ended mode, which allows
the option of using the VINP, VINN pins as two separate
single-ended inputs, either of which can be selected under soft­ware control.

Programmable Gain Amplifier

The encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.

The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in Control Register D.

Table I. PGA Settings for the Encoder Channel

IGS2 IGS1 IGS0 Gain (dB)

00 0 0
00 1 6
01 0 12
01 1 18
10 0 20
10 1 26
11 0 32
11 1 38

ADC

The ADC consists of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu­lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima­tion filter reduces the sample rate and increases the resolution.

–10–

REV. 0

AD73411

Analog Sigma-Delta Modulator

The AD73411 input channel employs a sigma-delta conver­sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over­sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73411, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f

/2 = DMCLK/16

S

(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina­tion of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 3c).

BAND

OF

INTEREST

fS/2

DMCLK/16

multiple of DMCLK/256, which is the decimation filter update
rate. The final detail in Figure 4d shows the application of a
final antialias filter in the DSP engine. This has the advantage of
being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 4a through 4c is imple­mented in the AD73411.

FB = 4kHz F

SINIT

= DMCLK/8

a. Analog Antialias Filter Transfer Function

SIGNAL TRANSFER FUNCTION

NOISE TRANSFER FUNCTION

FB = 4kHz

F

SINIT

= DMCLK/8

b. Analog Sigma-Delta Modulator Transfer Function

a

.

NOISE-SHAPING

BAND

OF

INTEREST

f

/2

S

DMCLK/16

b.

DIGITAL FILTER

BAND

OF

INTEREST

f

/2

S

DMCLK/16

c.

Figure 3. Sigma-Delta Noise Reduction

Figure 4 shows the various stages of filtering that are employed
in a typical AD73411 application. In Figure 4a we see the
transfer function of the external analog antialias filter. Even
though it is a single RC pole, its cutoff frequency is sufficiently
far away from the initial sampling frequency (DMCLK/8) that it
takes care of any signals that could be aliased by the sampling
frequency. This also shows the major difference between the
initial oversampling rate and the bandwidth of interest. In Figure
4b, the signal and noise-shaping responses of the sigma-delta
modulator are shown. The signal response provides further
rejection of any high frequency signals while the noise-shaping
will push the inherent quantization noise to an out-of-band
position. The detail of Figure 4c shows the response of the
digital decimation filter (Sinc-cubed response) with nulls every

REV. 0

–11–

FB = 4kHz F

SINTER

= DMCLK/256

c. Digital Decimator Transfer Function

FB = 4kHz

F

SFINAL

= 8kHz

F

SINTER

= DMCLK/256

d. Final Filter LPF (HPF) Transfer Function

Figure 4. AD73411 ADC Frequency Responses

Decimation Filter

The digital filter used in the AD73411 carries out two impor­tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high-frequency bitstream to a lower rate 15-bit word.

The antialiasing decimation filter is a sinc-cubed digital filter that
reduces the sampling rate from DMCLK/8 at the modulator to
an output rate at the SPORT of DMCLK/M (where M depends
on the sample rate setting—M = 256 @ 64 kHz; M = 512 @
32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and increases
the resolution from a single bit to 15 bits. Its Z transform is given
as: [(1–Z–N)/(1–Z–1)]3 where N is determined by the sampling rate
(N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N =
256 @ 8 kHz). This ensures a minimal group delay of 25 µs at the
64 kHz sampling rate.