Analog Devices AD620AR-REEL7, AD620AR-REEL, AD620AR, AD620BR-REEL7, AD620BR-REEL Datasheet

Low Cost, Low Power

a

FEATURES
EASY TO USE
Gain Set with One External Resistor

(Gain Range 1 to 1000)
Wide Power Supply Range (62.3 V to 618 V)
Higher Performance than Three Op Amp IA Designs
Available in 8-Lead DIP and SOIC Packaging
Low Power, 1.3 mA max Supply Current

EXCELLENT DC PERFORMANCE (“B GRADE”)
50 mV max, Input Offset Voltage

0.6 mV/8C max, Input Offset Drift

1.0 nA max, Input Bias Current
100 dB min Common-Mode Rejection Ratio (G = 10)

LOW NOISE

9 nV/√Hz, @ 1 kHz, Input Voltage Noise

0.28 mV p-p Noise (0.1 Hz to 10 Hz)

EXCELLENT AC SPECIFICATIONS
120 kHz Bandwidth (G = 100)
15 ms Settling Time to 0.01%

APPLICATIONS
Weigh Scales
ECG and Medical Instrumentation
Transducer Interface
Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment

PRODUCT DESCRIPTION

The AD620 is a low cost, high accuracy instrumentation ampli­fier that requires only one external resistor to set gains of 1 to

Instrumentation Amplifier

AD620

CONNECTION DIAGRAM

8-Lead Plastic Mini-DIP (N), Cerdip (Q)

and SOIC (R) Packages

1

R

G

2

–IN

3

+IN

–V

4

S

AD620

TOP VIEW

1000. Furthermore, the AD620 features 8-lead SOIC and DIP
packaging that is smaller than discrete designs, and offers lower
power (only 1.3 mA max supply current), making it a good fit
for battery powered, portable (or remote) applications.

The AD620, with its high accuracy of 40 ppm maximum

nonlinearity, low offset voltage of 50 µV max and offset drift of

0.6 µV/°C max, is ideal for use in precision data acquisition

systems, such as weigh scales and transducer interfaces. Fur­thermore, the low noise, low input bias current, and low power
of the AD620 make it well suited for medical applications such
as ECG and noninvasive blood pressure monitors.

The low input bias current of 1.0 nA max is made possible with
the use of Superβeta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of

9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,

0.1 pA/√Hz input current noise. Also, the AD620 is well suited
for multiplexed applications with its settling time of 15 µs to

0.01% and its cost is low enough to enable designs with one in­amp per channel.

8

7

6

5

R

G

+V

S

OUTPUT

REF

30,000

25,000

20,000

15,000

AD620A

10,000

5,000

TOTAL ERROR, PPM OF FULL SCALE

R

G

0

0 5 10 15 20

SUPPLY CURRENT – mA

3 OP-AMP
IN-AMP
(3 OP-07s)

Figure 1. Three Op Amp IA Designs vs. AD620

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

10,000

1,000

TYPICAL STANDARD
BIPOLAR INPUT

100

10

(0.1 – 10Hz) – mV p-p

RTI VOLTAGE NOISE

1

0.1

IN-AMP

G = 100

SOURCE RESISTANCE – V

AD620 SUPERbETA
BIPOLAR INPUT
IN-AMP

100M10k1k 10M1M100k

Figure 2. Total Voltage Noise vs. Source Resistance

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD620–SPECIFICATIONS

(Typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)

AD620A AD620B AD620S

1

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

GAIN G = 1 + (49.4 k/RG)

Gain Range 1 10,000 1 10,000 1 10,000
Gain Error

2

G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %

V

OUT

= ±10 V

G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %

Nonlinearity, V

G = 1–1000 R
G = 1–100 R

Gain vs. Temperature

VOLTAGE OFFSET (Total RTI Error = V

Input Offset, V

Over Temperature V

OSI

Average TC V

Output Offset, V

OSO

Over Temperature V
Average TC V

Offset Referred to the

= –10 V to +10 V,

OUT

= 10 kΩ 10 40 10 40 10 40 ppm

L

= 2 kΩ 10 95 10 95 10 95 ppm

L

G =1 10 10 10 ppm/°C

2

Gain >1

+ V

OSO

/G)

V

= ±5 V to ±15 V 30 125 15 50 30 125 µV

S

= ±5 V to ±15 V 185 85 225 µV

S

= ±5 V to ±15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C

S

V

= ±15 V 400 1000 200 500 400 1000 µV

S

V

= ±5 V 1500 750 1500 µV

S

= ±5 V to ±15 V 2000 1000 2000 µV

S

= ± 5 V to ±15 V 5.0 15 2.5 7.0 5.0 15 µV/°C

S

OSI

–50 –50 –50 ppm/°C

Input vs.
Supply (PSR) V

G = 1 80 100 80 100 80 100 dB

= ±2.3 V to ±18 V

S

G = 10 95 120 100 120 95 120 dB
G = 100 110 140 120 140 110 140 dB
G = 1000 110 140 120 140 110 140 dB

INPUT CURRENT

Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA

Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C

Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA

Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C

INPUT

Input Impedance

Differential 10i210i210i2GΩipF
Common-Mode 10i210i210i2GΩipF

Input Voltage Range

Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V

Over Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V

3

V

= ±2.3 V to ±5 V –V

S

V

= ±5 V to ±18 V –V

S

+ 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V

S

+ 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V

S

Common-Mode Rejection

Ratio DC to 60 Hz with
I kΩ Source Imbalance VCM = 0 V to ±10 V

G = 1 7390 8090 7390 dB
G = 10 93 110 100 110 93 110 dB
G = 100 110 130 120 130 110 130 dB
G = 1000 110 130 120 130 110 130 dB

OUTPUT

Output Swing R

Over Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V

Over Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V

= 10 kΩ,

L

V

= ±2.3 V to ±5 V –V

S

V

= ±5 V to ±18 V –V

S

+ 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V

S

+ 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V

S

Short Current Circuit ±18 ±18 ± 18 mA

–2–

REV. E

AD620

Model Conditions Min Typ Max Min Typ Max Min Typ Max Units

AD620A AD620B AD620S

DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth

G = 1 1000 1000 1000 kHz
G = 10 800 800 800 kHz
G = 100 120 120 120 kHz
G = 1000 12 12 12 kHz

Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step

G = 1–100 15 15 15 µs
G = 1000 150 150 150 µs

NOISE

Voltage Noise, 1 kHz

Input, Voltage Noise, e
Output, Voltage Noise, e

RTI, 0.1 Hz to 10 Hz

Total RTI Noise = (e

ni

no

2

)+( e

ni

2

/ G)

no

913 913 913 nV/√Hz
72 100 72 100 72 100 nV/√Hz

G = 1 3.0 3.0 6.0 3.0 6.0 µV p-p
G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p
G = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p

Current Noise f = 1 kHz 100 100 100 fA/√Hz

0.1 Hz to 10 Hz 10 10 10 pA p-p

REFERENCE INPUT

R

IN

I

IN

Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 V

V

, V

= 0 +50 +60 +50 +60 +50 +60 µA

IN+

REF

20 20 20 kΩ

Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001

POWER SUPPLY

Operating Range
Quiescent Current V

Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA

4

= ±2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA

S

±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V

TEMPERATURE RANGE

For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C

NOTES

1

See Analog Devices military data sheet for 883B tested specifications.

2

Does not include effects of external resistor RG.

3

One input grounded. G = 1.

4

This is defined as the same supply range which is used to specify PSR.

Specifications subject to change without notice.

1

REV. E

–3–

AD620

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . . . 650 mW

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

1

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±25 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C

Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C

Operating Temperature Range

AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to +125°C

Lead Temperature Range

(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead Plastic Package: θ
8-Lead Cerdip Package: θ
8-Lead SOIC Package: θ

= 95°C/W

JA

= 110°C/W

JA

= 155°C/W

JA

METALIZATION PHOTOGRAPH

Dimensions shown in inches and (mm).

Contact factory for latest dimensions.

RG*

+V

S

ORDERING GUIDE

Model Temperature Ranges Package Options*

AD620AN –40°C to +85°C N-8
AD620BN –40°C to +85°C N-8
AD620AR –40°C to +85°C SO-8
AD620AR-REEL – 40°C to +85°C 13" REEL
AD620AR-REEL7 –40°C to +85°C 7" REEL
AD620BR – 40°C to +85°C SO-8
AD620BR-REEL – 40°C to +85°C 13" REEL
AD620BR-REEL7 – 40°C to +85°C 7" REEL
AD620ACHIPS –40°C to +85°C Die Form
AD620SQ/883B –55°C to +125°C Q-8

*N = Plastic DIP; Q = Cerdip; SO = Small Outline.

OUTPUT

8

8

1

+IN

3

.

G

1

2

RG*

*FOR CHIP APPLICATIONS: THE PADS 1R
TO THE EXTERNAL GAIN REGISTER R
UNITY GAIN APPLICATIONS WHERE R
BE BONDED TOGETHER, AS WELL AS THE PADS 8R

–IN

0.125

(3.180)

AND 8RG MUST BE CONNECTED IN PARALLEL

G

. DO NOT CONNECT THEM IN SERIES TO RG. FOR

G

IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY

G

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

67

5

REFERENCE

0.0708
(1.799)

4

–V

S

–4–

REV. E

AD620

TEMPERATURE – 8C

INPUT BIAS CURRENT – nA

+I

B

–I

B

2.0

–2.0

175

–1.0

–1.5

–75

–0.5

0

0.5

1.0

1.5

1257525–25

FREQUENCY – Hz

1000

1

1 100k

100

10

10k1k100

VOLTAGE NOISE – nV/!Hz

GAIN = 1

GAIN = 10

10

GAIN = 100, 1,000

GAIN = 1000
BW LIMIT

Typical Characteristics

50

SAMPLE SIZE = 360

40

30

20

PERCENTAGE OF UNITS

10

0

–80

–40 0 +40 +80

INPUT OFFSET VOLTAGE – mV

(@ +258C, VS = 615 V, RL = 2 kV, unless otherwise noted)

Figure 3. Typical Distribution of Input Offset Voltage

50

SAMPLE SIZE = 850

40

30

20

Figure 6. Input Bias Current vs. Temperature

2

1.5

1

PERCENTAGE OF UNITS

10

0

–1200 +1200

–600 0 +600

INPUT BIAS CURRENT – pA

Figure 4. Typical Distribution of Input Bias Current

50

SAMPLE SIZE = 850

40

30

20

REV. E

PERCENTAGE OF UNITS

10

–400

–200 0 +200 +400

INPUT OFFSET CURRENT – pA

0

Figure 5. Typical Distribution of Input Offset Current

0.5

CHANGE IN OFFSET VOLTAGE – mV

0

051

WARM-UP TIME – Minutes

432

Figure 7. Change in Input Offset Voltage vs.
Warm-Up Time

Figure 8. Voltage Noise Spectral Density vs. Frequency,
(G = 1–1000)

–5–

AD620–Typical Characteristics

1000

100

CURRENT NOISE – fA/!Hz

10

1

10

FREQUENCY – Hz

100

Figure 9. Current Noise Spectral Density vs. Frequency

1000

Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div

100,000

10,000

FET INPUT

1000

IN-AMP

RTI NOISE – 2.0 mV/DIV

TIME – 1 SEC/DIV

Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

RTI NOISE – 0.1mV/DIV

TIME – 1 SEC/DIV

100

TOTAL DRIFT FROM 258C TO 858C, RTI – mV

10

1k 10M

10k 1M100k

SOURCE RESISTANCE – V

AD620A

Figure 12. Total Drift vs. Source Resistance

+160

+140

+120

+100

+80

CMR – dB

+60

+40

+20

G = 1000

G = 100

G = 10

G = 1

0

0.1

1

FREQUENCY – Hz

100k10k1k10010

1M

Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

Figure 13. CMR vs. Frequency, RTI, Zero to 1 kΩ Source
Imbalance

–6–

REV. E

180

OUTPUT VOLTAGE – Volts p-p

FREQUENCY – Hz

35

0

1M

15

5

10k

10

1k

30

20

25

100k

G = 10, 100, 1000

G = 1

G = 1000

G = 100

BW LIMIT

160

AD620

140

120

100

PSR – dB

80

60

40

20

0.1

1

FREQUENCY – Hz

G = 1000

G = 100

G = 10

G = 1

100k10k1k10010

1M

Figure 14. Positive PSR vs. Frequency, RTI (G = 1–1000)

180

160

140

120

100

PSR – dB

80

60

40

20

0.1

1

FREQUENCY – Hz

G = 1000

G = 100

G = 10

G = 1

100k10k1k10010

1M

Figure 15. Negative PSR vs. Frequency, RTI (G = 1–1000)

Figure 17. Large Signal Frequency Response

+VS –0.0

–0.5

–1.0

–1.5

+1.5

+1.0

INPUT VOLTAGE LIMIT – Volts

(REFERRED TO SUPPLY VOLTAGES)

+0.5

–VS +0.0

50

SUPPLY VOLTAGE 6 Volts

1510

20

Figure 18. Input Voltage Range vs. Supply Voltage, G = 1

1000

100

10

GAIN – V/V

REV. E

0.1

1

100 10M

1k

FREQUENCY – Hz

100k 1M10k

Figure 16. Gain vs. Frequency

+VS –0.0

–0.5

–1.0

–1.5

+1.5

+1.0

OUTPUT VOLTAGE SWING – Volts

+0.5

(REFERRED TO SUPPLY VOLTAGES)

–V

+0.0

S

0

5

SUPPLY VOLTAGE 6 Volts

RL = 2kV

RL = 10kV

RL = 10kV

RL = 2kV

Figure 19. Output Voltage Swing vs. Supply Voltage,
G = 10

–7–

1510

20

AD620

30

VS = 615V
G = 10

20

10

OUTPUT VOLTAGE SWING – Volts p-p

0

0

100 1k
LOAD RESISTANCE – V

10k

Figure 20. Output Voltage Swing vs. Load Resistance

........ ................................

............ ............................

............ ............................

Figure 23. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)

........ ................................

........ ................................

Figure 21. Large Signal Pulse Response and Settling Time
G = 1 (0.5 mV = 0.01%)

............ ............................

............ ............................

........ ................................

Figure 24. Small Signal Response, G = 10, RL = 2 kΩ,

= 100 pF

C

L

............ ............................

............ ............................

Figure 22. Small Signal Response, G = 1, RL = 2 kΩ,

= 100 pF

C

L

Figure 25. Large Signal Response and Settling Time,
G = 100 (0.5 mV = 0.01%)

–8–

REV. E

............ ............................

OUTPUT STEP SIZE – Volts

SETTLING TIME – ms

TO 0.01%

TO 0.1%

20

0

020

15

5

5

10

10

15

............ ............................

AD620

Figure 26. Small Signal Pulse Response, G = 100,
R

= 2 kΩ, CL = 100 pF

L

........ ................................

........ ................................

Figure 27. Large Signal Response and Settling Time,
G = 1000 (0.5 mV = 0.01%)

Figure 29. Settling Time vs. Step Size (G = 1)

1000

100

10

SETTLING TIME – ms

1

1 1000

10 100

GAIN

Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step

............ ............................

Figure 28. Small Signal Pulse Response, G = 1000,

R

REV. E

............ ............................

= 2 kΩ, CL = 100 pF

L

–9–

........ ................................

........ ................................

Figure 31a. Gain Nonlinearity, G = 1, RL = 10 k
(10 µV = 1 ppm)

Ω

AD620

............ ............ ................

............ ............ ................

Figure 31b. Gain Nonlinearity, G = 100, RL = 10 k
(100µV = 10 ppm)

................................ ........

................................ ........

Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 k
(1 mV = 100 ppm)

INPUT

10V p-p

100kV

11kV 1kV 100 V

G=1000

49.9V

*ALL RESISTORS 1% TOLERANCE

G=100

499V

10kV*

G=1

G=10

5.49kV

1kV

2
1

AD620

8
3

10T

10kV

+V

S

7

5

4

–V

S

Figure 32. Settling Time Test Circuit

– IN

R3

400V

20mA

I1

Q1

A1 A2

C1

R1

GAIN

SENSE

R

–V

V

B

G

R2

GAIN

SENSE

S

20mA

C2

Q2

I2

10kV

10kV

10kV

400V

A3

R4

10kV

+IN

OUTPUT

REF

Figure 33. Simplified Schematic of AD620

Ω

THEORY OF OPERATION

The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to

0.15% at G = 100) with only one resistor. Monolithic construc­tion and laser wafer trimming allow the tight matching and
tracking of circuit components, thus ensuring the high level of
performance inherent in this circuit.

The input transistors Q1 and Q2 provide a single differential­pair bipolar input for high precision (Figure 33), yet offer 10×
lower Input Bias Current thanks to Superβeta processing. Feed­back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main­tains constant collector current of the input devices Q1, Q2
thereby impressing the input voltage across the external gain
setting resistor R
inputs to the A1/A2 outputs given by G = (R1 + R2)/R

. This creates a differential gain from the

G

+ 1.

G

The unity-gain subtracter A3 removes any common-mode sig­nal, yielding a single-ended output referred to the REF pin
potential.

Ω

The value of R

also determines the transconductance of the

G

preamp stage. As R

is reduced for larger gains, the transcon-

G

ductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-

V

OUT

related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro­grammed gain, thus optimizing frequency response. (c) The

input voltage noise is reduced to a value of 9 nV/√Hz, deter-

mined mainly by the collector current and base resistance of the
input devices.

6

The internal gain resistors, R1 and R2, are trimmed to an abso-

lute value of 24.7 kΩ, allowing the gain to be programmed

accurately with a single external resistor.

The gain equation is then

49.4 kΩ

G =

+1

R

G

so that

–10–

49.4 kΩ

R

=

G

G −1

REV. E

AD620

Make vs. Buy: A Typical Bridge Application Error Budget

The AD620 offers improved performance over “homebrew”
three op amp IA designs, along with smaller size, fewer compo­nents and 10× lower supply current. In the typical application,
shown in Figure 34, a gain of 100 is required to amplify a bridge
output of 20 mV full scale over the industrial temperature range

of –40°C to +85°C. The error budget table below shows how to

calculate the effect various error sources have on circuit accuracy.

Regardless of the system in which it is being used, the AD620
provides greater accuracy, and at low power and price. In simple

+10V

R = 350V

R = 350V R = 350V

PRECISION BRIDGE TRANSDUCER

R = 350V

R

G

499V

SUPPLY CURRENT = 1.3mA MAX

AD620A

REFERENCE

AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100

systems, absolute accuracy and drift errors are by far the most
significant contributors to error. In more complex systems with
an intelligent processor, an autogain/autozero cycle will remove all
absolute accuracy and drift errors leaving only the resolution
errors of gain nonlinearity and noise, thus allowing full 14-bit
accuracy.

Note that for the homebrew circuit, the OP07 specifications for

input voltage offset and noise have been multiplied by √2. This

is because a three op amp type in-amp has two op amps at its
inputs, both contributing to the overall input error.

OP07D

10kV**

100V**

“HOMEBREW” IN-AMP, G = 100
*0.02% RESISTOR MATCH, 3PPM/8C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/8C TRACKING
SUPPLY CURRENT = 15mA MAX

10kV**

OP07D

10kV*

10kV*

10kV*

OP07D

10kV*

Figure 34. Make vs. Buy

Table I. Make vs. Buy Error Budget

AD620 Circuit “Homebrew” Circuit Error, ppm of Full Scale

Error Source Calculation Calculation AD620 Homebrew

ABSOLUTE ACCURACY at T

= +25°C

A

Input Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 16,250 10,607
Output Offset Voltage, µV 1000 µV/100/20 mV ((150 µV × 2)/100)/20 mV 14,500 10,150
Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 14,118 14,153

CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100 14,791 10,500

Total Absolute Error 17,558 11,310

DRIFT TO +85°C

Gain Drift, ppm/°C (50 ppm + 10 ppm) × 60°C 100 ppm/°C Track × 60°C 13,600 16,000
Input Offset Voltage Drift, µV/°C1µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 13,000 10,607
Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100/20 mV (2.5 µV/°C × 2 × 60°C)/100/20 mV 14,450 10,150

Total Drift Error 17,050 16,757

RESOLUTION

Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 14,140 10,140

Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 141,14 13,127

Total Resolution Error 14,154 101,67

Grand Total Error 14,662 28,134

G = 100, V

(All errors are min/max and referred to input.)

= ±15 V.

S

REV. E

–11–

AD620

+5V

7

3kV

3kV

1.7mA 0.10mA

3kV

3kV

G=100

499V

3
8

1
2

1.3mA

AD620B

4

MAX

20kV

6

5

10kV

Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply

Pressure Measurement

Although useful in many bridge applications such as weigh
scales, the AD620 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small size and
low power become more significant.

Figure 35 shows a 3 kΩ pressure transducer bridge powered

from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the
signal to be conditioned for only 3.8 mA of total supply current.

Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic non­invasive blood pressure measurement.

REF

20kV

AD705

IN

ADC

AGND

0.6mA
MAX

DIGITAL
DATA
OUTPUT

Medical ECG

The low current noise of the AD620 allows its use in ECG

monitors (Figure 36) where high source resistances of 1 MΩ or

higher are not uncommon. The AD620’s low power, low supply
voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery
powered data recorders.

Furthermore, the low bias currents and low current noise
coupled with the low voltage noise of the AD620 improve the
dynamic range for better performance.

The value of capacitor C1 is chosen to maintain stability of the
right leg drive loop. Proper safeguards, such as isolation, must
be added to this circuit to protect the patient from possible
harm.

PATIENT/CIRCUIT

PROTECTION/ISOLATION

R1

C1

10kV

R4

1MV

AD705J

Figure 36. A Medical ECG Monitor Circuit

R3

24.9kV

R2

24.9kV

R

G

8.25kV

+3V

AD620A

G = 7

–3V

0.03Hz
HIGH

PASS

FILTER

G = 143

OUTPUT

AMPLIFIER

OUTPUT
1V/mV

–12–

REV. E

AD620

Precision V-I Converter

The AD620, along with another op amp and two resistors, makes
a precision current source (Figure 37). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
V

of the AD620 appears across R1, which converts it to a

X

current. This current less only, the input bias current of the op
amp, then flows out to the load.

+V

S

V

IN+

R

G

V

IN–

I =

L

3
8

AD620

1

2

[(V ) – (V )] G

V

x

=

R1

7

+ V –

AD705

X

R1

I

L

LOAD

6

5

4

–V

S

IN+

IN–

R1

Figure 37. Precision Voltage-to-Current Converter

±

(Operates on 1.8 mA,

3 V)

GAIN SELECTION

The AD620’s gain is resistor programmed by RG, or more pre­cisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1%–1%
resistors. Table II shows required values of R
Note that for G = 1, the R
any arbitrary gain R

G

pins are unconnected (R

G

can be calculated by using the formula:

49.4 kΩ

R

=

G

G −1

for various gains.

G

= ∞). For

G

To minimize gain error, avoid high parasitic resistance in series
with R

; to minimize gain drift, RG should have a low TC—less

G

than 10 ppm/°C—for the best performance.

Table II. Required Values of Gain Resistors

1% Std Table Calculated 0.1% Std Table Calculated

Value of RG, V Gain Value of RG, V Gain

49.9 k 1.990 49.3 k 2.002

12.4 k 4.984 12.4 k 4.984

5.49 k 9.998 5.49 k 9.998

2.61 k 19.93 2.61 k 19.93

1.00 k 50.40 1.01 k 49.91
499 100.0 499 100.0

249 199.4 249 199.4
100 495.0 98.8 501.0

49.9 991.0 49.3 1,003

INPUT AND OUTPUT OFFSET VOLTAGE

The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total V

for a given gain is calculated as:

OS

Total Error RTI = input error + (output error/G)

Total Error RTO = (input error × G) + output error

REFERENCE TERMINAL

The reference terminal potential defines the zero output voltage,
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.

INPUT PROTECTION

The AD620 features 400 Ω of series thin film resistance at its
inputs, and will safely withstand input overloads of up to ±15 V
or ± 60 mA for several hours. This is true for all gains, and power

on and off, which is particularly important since the signal
source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (I
V

/400 Ω). For input overloads beyond the supplies, clamping

IN

IN

≤

the inputs to the supplies (using a low leakage diode such as an
FD333) will reduce the required resistance, yielding lower
noise.

RF INTERFERENCE

All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
small dc offset errors. The AD620 allows direct access to the
input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 38),

where RC < 1/(2 πf) and where f ≥ the bandwidth of the
AD620; C ≤ 150 pF. Matching the extraneous capacitance at

Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.

R

G

–IN

+IN

1

C

R

R

2

3

4

C

8

7

6

5

REV. E

Figure 38. Circuit to Attenuate RF Interference

–13–

AD620

COMMON-MODE REJECTION

Instrumentation amplifiers like the AD620 offer high CMR,
which is a measure of the change in output voltage when both
inputs are changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a speci­fied source imbalance.

For optimal CMR the reference terminal should be tied to a low
impedance point, and differences in capacitance and resistance
should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
best CMR over frequency the shield should be properly driven.
Figures 39 and 40 show active data guards that are configured
to improve ac common-mode rejections by “bootstrapping” the
capacitances of input cable shields, thus minimizing the capaci­tance mismatch between the inputs.

+V

S

AD620

–V

S

REFERENCE

V

OUT

100V

100V

AD648

– INPUT

–V

+ INPUT

R

G

S

Figure 39. Differential Shield Driver

GROUNDING

Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems by simply tying the REF pin to the appropriate “local
ground.”

In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 41). It would be conve­nient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hun­dreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensi­tive points to the system ground. These ground returns must be
tied together at some point, usually best at the ADC package as
shown.

0.1mF

AD620

ANALOG P.S.

+15V C –15V

0.1mF

AD585

S/H

1mF

DIGITAL P.S.

1

m

F

AD574A

ADC

1mF

+5VC

+

DIGITAL
DATA
OUTPUT

Figure 41. Basic Grounding Practice

+V

100V

– INPUT

AD548

+ INPUT

R

G

2

R

G

2

AD620

–V

S

REFERENCE

S

Figure 40. Common-Mode Shield Driver

V

OUT

–14–

REV. E

AD620

GROUND RETURNS FOR INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore, when amplifying “floating” input

+V

AD620

–V

S

S

REFERENCE

LOAD

TO POWER

SUPPLY

GROUND

V

OUT

– INPUT

R

+ INPUT

G

Figure 42a. Ground Returns for Bias Currents with
Transformer Coupled Inputs

– INPUT

sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figure 42.
Refer to the Instrumentation Amplifier Application Guide (free
from Analog Devices) for more information regarding in amp
applications.

+V

AD620

–V

S

S

REFERENCE

LOAD

TO POWER

SUPPLY

GROUND

V

OUT

– INPUT

+ INPUT

R

G

Figure 42b. Ground Returns for Bias Currents with
Thermocouple Inputs

+V

S

LOAD

TO POWER

SUPPLY

GROUND

V

OUT

100kV

+ INPUT

100kV

R

AD620

G

REFERENCE

–V

S

Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs

REV. E

–15–

AD620

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-8) Package

0.430 (10.92)

0.348 (8.84)

8

14

PIN 1

0.100
(2.54)

BSC

5

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

Cerdip (Q-8) Package

0.195 (4.95)

0.115 (2.93)

C1599c–0–7/99PRINTED IN U.S.A.

0.005 (0.13)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.055 (1.4)

1

PIN 1

MAX

0.100
(2.54)

BSC

MAX

5

0.310 (7.87)

0.220 (5.59)

4

0.060 (1.52)

0.015 (0.38)

0.070 (1.78)

0.030 (0.76)

MIN

8

0.405 (10.29)

SOIC (SO-8) Package

0.1968 (5.00)

0.1890 (4.80)

85

PIN 1

0.0500
(1.27)

BSC

0.2440 (6.20)

41

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.150
(3.81)
MIN

SEATING
PLANE

0.0098 (0.25)

0.0075 (0.19)

0.320 (8.13)

0.290 (7.37)

15°

0°

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.015 (0.38)

0.008 (0.20)

x 45°

0.0500 (1.27)

0.0160 (0.41)

–16–

REV. E