ANALOG DEVICES AD5726 Service Manual

Quad, 12-Bit, Serial Input,

V

A

K

FEATURES

+5 V to ±15 V operation
Unipolar or bipolar operation
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Guaranteed monotonic over temperature
Double-buffered inputs
Asynchronous
Operating temperature range: −40°C to +125°C
iCMOS process technology

APPLICATIONS

Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers

GENERAL DESCRIPTION

The AD5726 is a quad, 12-bit, serial input, voltage output
digital-to-analog converter (DAC) fabricated on Analog
Devices, Inc., iCMOS® process technology
guaranteed monotonicity and integral nonlinearity (INL)
of ±1 LSB maximum.

Output voltage swing is set by two reference inputs, V
V

. The DAC offers a unipolar positive output range when

REFN

the V

input is set to 0 V and the V

REFN

to zero scale/midscale

CLR

1

that offers

REFP

input is set to a positive

REFP

FUNCTIONAL BLOCK DIAGRAM

AV

V

DD

SS

Unipolar/Bipolar, Voltage Output DAC

AD5726

and

voltage. A similar configuration with V

at 0 V and V

REFP

negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V

V

to nonzero voltages. This method of setting output voltage

REFN

ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.

The AD5726 uses a serial interface that operates at clock rates up to
30 MHz and is compatible with DSP and microcontroller interface
standards. The asynchronous

CLR

function clears all DAC

registers to a user-selectable zero-scale or midscale output.
The AD5726 is available in 16-lead SSOP, 20-lead SSOP, and

16-lead SOIC packages. It can be operated from a wide variety
of supply and reference voltages with supplies ranging from
single +5 V to ±15 V, and references ranging from +2.5 V to
±10 V. Power dissipation is less than 240 mW with ±15 V
supplies and only 30 mW with a +5 V supply. Operation is
specified over the temperature range of −40°C to +125°C.

A similar device, also available from Analog Devices is
the AD5725, which is a quad, 12-bit, parallel input, unipolar/
bipolar, voltage output DAC.

REFP

REFP

REFN

and

at a

SDIN

SCL

CS

I/O

REGISTER

AND

CONTROL

LOGIC

AD5726

GND

12

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

12

12

12

12

CLRSEL

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

LDACCLR

12

DAC A

12

DAC B

12

DAC C

12

DAC D

V

REFN

V

V

V

V

OUTA

OUTB

OUTC

OUTD

06469-001

Figure 1.

1

For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology

platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5726

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Terminolog y .................................................................................... 12

Theory of Operation ...................................................................... 13

DAC Architecture ....................................................................... 13

Output Amplifiers ...................................................................... 13

Reference Inputs ......................................................................... 13

Serial Interface ............................................................................ 14

Applications Information .............................................................. 15

Power-Up Sequence ................................................................... 15

Reference Configuration ........................................................... 15

Power Supply Bypassing and Grounding ................................ 16

Galvanically Isolated Interface ................................................. 16

Microprocessor Interfacing ....................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

REVISION HISTORY

6/08—Rev. A to Rev. B

Added 20-Lead SSOP ......................................................... Universal

Changes to Features Section............................................................ 1

Changes to General Description Section ...................................... 1

Deleted Table 1 .................................................................................. 1

Changes to Pin Configuration and Function Descriptions

Section ................................................................................................ 8

Deleted Figure 7 ................................................................................ 9

Changes to Typical Performance Characteristics Section ........... 9

Added Figure 15 .............................................................................. 10

Changes to Figure 22 ...................................................................... 11

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

1/08—Rev. 0 to Rev. A

Changes to Figure 6, Figure 7 .......................................................... 9

Changes to Figure 12, Figure 13 ................................................... 10

Changes to Figure 19, Figure 20 ................................................... 11

Inserted New Figure 22, Renumbered Figures Sequentially .... 11

Added Major Code Transition Glitch Impulse Section ............. 12

Changes to Figure 23 ...................................................................... 13

Change to Input Shift Register Section ....................................... 14

Change to Single +5 V Supply Operation Section ..................... 16

4/07—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5726

SPECIFICATIONS

AVDD = +5 V ± 5%, AVSS = 0 V or −5 V ± 5%, V
otherwise noted.

1

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy (INL) ±1 LSB max Y grade, AVSS = −5 V, outputs unloaded
±1 LSB max Y grade, AVSS = 0 V
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Linearity Matching ±1 LSB typ
Zero-Scale Error ±6 LSB max AVSS = −5 V
Full-Scale Error ±6 LSB max AVSS = −5 V
Zero-Scale Error ±12 LSB max AVSS = 0 V
Full-Scale Error ±12 LSB max AVSS = 0 V
Zero-Scale Temperature Coefficient3±10 ppm FSR/°C typ AVSS = −5 V
Full-Scale Temperature Coefficient

3

±10 ppm FSR/°C typ AV

REFERENCE INPUT

V

REFP

Reference Input Range

4

V

REFN

AVDD − 2.5 V max
Input Current ±0.75 mA max Typically 0.25 mA

V

REFN

Reference Input Range

4

AV

SS

0 V V min AVSS = 0 V
V

REFP

Input Current −1.0 mA max Typically −0.6 mA, AVSS = −5 V

Large Signal Bandwidth

OUTPUT CHARACTERISTICS

3

160 kHz typ −3 dB, V

3

Output Current ±1.25 mA max AVSS = −5 V

DIGITAL INPUTS

Input High Voltage, VIH 2.4 V min
Input Low Voltage, VIL 0.8 V max
Input Current

3

10 μA max

Input Capacitance3 5 pF typ

POWER SUPPLY CHARACTERISTICS

3

Power Supply Sensitivity

0.002 %/% max Typically 0.0004%/%
AIDD 1.5 mA/channel max Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
AISS 1.5 mA/channel max Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
Power Dissipation 30 mW max Outputs unloaded, typically 15 mW, AVSS = 0 V

1

All supplies can be varied ±5% and operation is guaranteed. Device is tested with AVDD = 4.75 V.

2

For single-supply operation (V

3

Guaranteed by design and characterization, not production tested.

4

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= 0 V, AVSS = 0 V), due to internal offset errors, INL and DNL are measured beginning at Code 0x005.

REFN

= +2.5 V, V

REFP

= 0 V or −2.5 V, R

REFN

= −5 V

SS

+ 2.5 V min

V min

− 2.5 V max

= 2 kΩ. All specifications T

LOAD

2

2

2

= 0 V to 10 V p-p

REFP

MIN

to T

MAX

, unless

Rev. B | Page 3 of 20

AD5726

AVDD = +15 V ± 5%, AVSS = −15 V ± 5%, V

Table 2.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max Y grade
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Linearity Matching ±1 LSB max
Zero-Scale Error ±3 LSB max
Full-Scale Error ±3 LSB max
Zero-Scale Temperature Coefficient2±4 ppm FSR/°C typ
Full-Scale Temperature Coefficient

REFERENCE INPUT

V

REFP

Reference Input Range

3

AVDD − 2.5 V max
Input Current ±2 mA max Code 0x000, Code 0x555, typically 1 mA

V

REFN

Reference Input Range

3

−10 V V min

V
Input Current

Large Signal Bandwidth

OUTPUT CHARACTERISTICS

2

−3.5 mA min Code 0x000, Code 0x555, typically −2 mA

2

450 kHz typ −3 dB, V

2

Output Current ±5 mA max

DIGITAL INPUTS

Input High Voltage, VIH 2.4 V min
Input Low Voltage, VIL 0.8 V max
Input Current

2

10 μA max

Input Capacitance2 5 pF typ

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

0.002 %/% max Typically 0.0004%/%

AIDD 2 mA/channel max Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V
AISS 2 mA/channel max Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V
Power Dissipation 240 mW max

1

All supplies can be varied ±5% and operation is guaranteed.

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= +10 V, V

REFP

2

±4 ppm FSR/°C typ

V

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −10 V, R

REFN

= 2 kΩ. All specifications T

LOAD

= 0 V to 2.5 V p-p

REFP

MIN

to T

, unless otherwise noted.1

MAX

Rev. B | Page 4 of 20

AD5726

AC PERFORMANCE CHARACTERISTICS

AVDD = +5 V ± 5% or +15 V ± 5%, AVSS = −5 V ± 5% or 0 V or −15 V ± 5%, GND = 0 V, V

−10 V, R

= 2 kΩ. All specifications T

LOAD

MIN

to T

, unless otherwise noted.1

MAX

Table 3.

Parameter A Grade B Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time (tS) 13 13 μs typ To 0.01%, ±10 V voltage swing
9 9 μs typ To 0.01%, ±2.5 V voltage swing, AVDD = 5 V
Slew Rate 2.3 2.3 V/μs typ 10% to 90%, ±10 V voltage swing
2 2 V/μs typ 10% to 90%, ±2.5 V voltage swing
Analog Crosstalk 100 100 dB typ
Digital Feedthrough 0.25 0.25 nV-sec typ
Large Signal Bandwidth 90 90 kHz typ 3 dB, V
Major Code Transition Glitch Impulse 30 30 nV-sec typ Code transition = 0x7FF to 0x800 and vice versa

1

Guaranteed by design and characterization, not production tested.

= +2.5 V or +10 V, V

REFP

= 5 V + 10 V p-p, V

REFP

= −2.5 V or 0 V or

REFN

= −10 V

REFN

Rev. B | Page 5 of 20

AD5726

TIMING CHARACTERISTICS

AVDD = +15 V or +5 V, AVSS = −15 V or −5 V or 0 V, GND = 0 V; V
C

= 200 pF. All specifications T

L

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter Limit at T

MIN

, T

Unit Description

MAX

tDS 5 ns Data setup time
tDH 5 ns Data hold time
tCH 13 ns Clock pulse width high
tCL 13 ns Clock pulse width low
t

13 ns Select time

CSS

t

13 ns Deselect delay

CSH

t

20 ns Load disable time

LD1

t

20 ns Load delay

LD2

t

20 ns Load pulse width

LDW

t

20 ns Clear pulse width

CLRW

1

Guaranteed by design and characterization, not production tested.

2

All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Timing Diagrams

CS

t

CSS

SDIN

A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0

= +10 V or +2.5 V; V

REFP

1, 2

= −10 V or −2.5 V or 0 V, R

REFN

t

CSH

LOAD

= 2 kΩ,

SCLK

LDAC

SDIN

SCLK

LDAC

V

CS

OUT

t

LD1

t

t

DS

DH

t

t

CL

CH

t

CSH

t

LD2tLDW

Figure 3. Data Load Timing

t

LD2

06469-002

Figure 2. Data Load Sequence

CLRSEL

t

CLRW

CLR

t

t

S

V

±1LSB

6469-003

OUT

S

±1LSB

6469-004

Figure 4. Clear Timing

Rev. B | Page 6 of 20