ANALOG DEVICES AD5726 Service Manual

Quad, 12-Bit, Serial Input,

V

A

K

FEATURES

+5 V to ±15 V operation
Unipolar or bipolar operation
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Guaranteed monotonic over temperature
Double-buffered inputs
Asynchronous
Operating temperature range: −40°C to +125°C
iCMOS process technology

APPLICATIONS

Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers

GENERAL DESCRIPTION

The AD5726 is a quad, 12-bit, serial input, voltage output
digital-to-analog converter (DAC) fabricated on Analog
Devices, Inc., iCMOS® process technology
guaranteed monotonicity and integral nonlinearity (INL)
of ±1 LSB maximum.

Output voltage swing is set by two reference inputs, V
V

. The DAC offers a unipolar positive output range when

REFN

the V

input is set to 0 V and the V

REFN

to zero scale/midscale

CLR

1

that offers

REFP

input is set to a positive

REFP

FUNCTIONAL BLOCK DIAGRAM

AV

V

DD

SS

Unipolar/Bipolar, Voltage Output DAC

AD5726

and

voltage. A similar configuration with V

at 0 V and V

REFP

negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V

V

to nonzero voltages. This method of setting output voltage

REFN

ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.

The AD5726 uses a serial interface that operates at clock rates up to
30 MHz and is compatible with DSP and microcontroller interface
standards. The asynchronous

CLR

function clears all DAC

registers to a user-selectable zero-scale or midscale output.
The AD5726 is available in 16-lead SSOP, 20-lead SSOP, and

16-lead SOIC packages. It can be operated from a wide variety
of supply and reference voltages with supplies ranging from
single +5 V to ±15 V, and references ranging from +2.5 V to
±10 V. Power dissipation is less than 240 mW with ±15 V
supplies and only 30 mW with a +5 V supply. Operation is
specified over the temperature range of −40°C to +125°C.

A similar device, also available from Analog Devices is
the AD5725, which is a quad, 12-bit, parallel input, unipolar/
bipolar, voltage output DAC.

REFP

REFP

REFN

and

at a

SDIN

SCL

CS

I/O

REGISTER

AND

CONTROL

LOGIC

AD5726

GND

12

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

12

12

12

12

CLRSEL

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

LDACCLR

12

DAC A

12

DAC B

12

DAC C

12

DAC D

V

REFN

V

V

V

V

OUTA

OUTB

OUTC

OUTD

06469-001

Figure 1.

1

For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology

platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5726

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Terminolog y .................................................................................... 12

Theory of Operation ...................................................................... 13

DAC Architecture ....................................................................... 13

Output Amplifiers ...................................................................... 13

Reference Inputs ......................................................................... 13

Serial Interface ............................................................................ 14

Applications Information .............................................................. 15

Power-Up Sequence ................................................................... 15

Reference Configuration ........................................................... 15

Power Supply Bypassing and Grounding ................................ 16

Galvanically Isolated Interface ................................................. 16

Microprocessor Interfacing ....................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

REVISION HISTORY

6/08—Rev. A to Rev. B

Added 20-Lead SSOP ......................................................... Universal

Changes to Features Section............................................................ 1

Changes to General Description Section ...................................... 1

Deleted Table 1 .................................................................................. 1

Changes to Pin Configuration and Function Descriptions

Section ................................................................................................ 8

Deleted Figure 7 ................................................................................ 9

Changes to Typical Performance Characteristics Section ........... 9

Added Figure 15 .............................................................................. 10

Changes to Figure 22 ...................................................................... 11

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

1/08—Rev. 0 to Rev. A

Changes to Figure 6, Figure 7 .......................................................... 9

Changes to Figure 12, Figure 13 ................................................... 10

Changes to Figure 19, Figure 20 ................................................... 11

Inserted New Figure 22, Renumbered Figures Sequentially .... 11

Added Major Code Transition Glitch Impulse Section ............. 12

Changes to Figure 23 ...................................................................... 13

Change to Input Shift Register Section ....................................... 14

Change to Single +5 V Supply Operation Section ..................... 16

4/07—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5726

SPECIFICATIONS

AVDD = +5 V ± 5%, AVSS = 0 V or −5 V ± 5%, V
otherwise noted.

1

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy (INL) ±1 LSB max Y grade, AVSS = −5 V, outputs unloaded
±1 LSB max Y grade, AVSS = 0 V
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Linearity Matching ±1 LSB typ
Zero-Scale Error ±6 LSB max AVSS = −5 V
Full-Scale Error ±6 LSB max AVSS = −5 V
Zero-Scale Error ±12 LSB max AVSS = 0 V
Full-Scale Error ±12 LSB max AVSS = 0 V
Zero-Scale Temperature Coefficient3±10 ppm FSR/°C typ AVSS = −5 V
Full-Scale Temperature Coefficient

3

±10 ppm FSR/°C typ AV

REFERENCE INPUT

V

REFP

Reference Input Range

4

V

REFN

AVDD − 2.5 V max
Input Current ±0.75 mA max Typically 0.25 mA

V

REFN

Reference Input Range

4

AV

SS

0 V V min AVSS = 0 V
V

REFP

Input Current −1.0 mA max Typically −0.6 mA, AVSS = −5 V

Large Signal Bandwidth

OUTPUT CHARACTERISTICS

3

160 kHz typ −3 dB, V

3

Output Current ±1.25 mA max AVSS = −5 V

DIGITAL INPUTS

Input High Voltage, VIH 2.4 V min
Input Low Voltage, VIL 0.8 V max
Input Current

3

10 μA max

Input Capacitance3 5 pF typ

POWER SUPPLY CHARACTERISTICS

3

Power Supply Sensitivity

0.002 %/% max Typically 0.0004%/%
AIDD 1.5 mA/channel max Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
AISS 1.5 mA/channel max Outputs unloaded, typically 0.75 mA, VIL = DGND, VIH = 5 V
Power Dissipation 30 mW max Outputs unloaded, typically 15 mW, AVSS = 0 V

1

All supplies can be varied ±5% and operation is guaranteed. Device is tested with AVDD = 4.75 V.

2

For single-supply operation (V

3

Guaranteed by design and characterization, not production tested.

4

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= 0 V, AVSS = 0 V), due to internal offset errors, INL and DNL are measured beginning at Code 0x005.

REFN

= +2.5 V, V

REFP

= 0 V or −2.5 V, R

REFN

= −5 V

SS

+ 2.5 V min

V min

− 2.5 V max

= 2 kΩ. All specifications T

LOAD

2

2

2

= 0 V to 10 V p-p

REFP

MIN

to T

MAX

, unless

Rev. B | Page 3 of 20

AD5726

AVDD = +15 V ± 5%, AVSS = −15 V ± 5%, V

Table 2.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max Y grade
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Linearity Matching ±1 LSB max
Zero-Scale Error ±3 LSB max
Full-Scale Error ±3 LSB max
Zero-Scale Temperature Coefficient2±4 ppm FSR/°C typ
Full-Scale Temperature Coefficient

REFERENCE INPUT

V

REFP

Reference Input Range

3

AVDD − 2.5 V max
Input Current ±2 mA max Code 0x000, Code 0x555, typically 1 mA

V

REFN

Reference Input Range

3

−10 V V min

V
Input Current

Large Signal Bandwidth

OUTPUT CHARACTERISTICS

2

−3.5 mA min Code 0x000, Code 0x555, typically −2 mA

2

450 kHz typ −3 dB, V

2

Output Current ±5 mA max

DIGITAL INPUTS

Input High Voltage, VIH 2.4 V min
Input Low Voltage, VIL 0.8 V max
Input Current

2

10 μA max

Input Capacitance2 5 pF typ

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

0.002 %/% max Typically 0.0004%/%

AIDD 2 mA/channel max Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V
AISS 2 mA/channel max Outputs unloaded, typically 1.25 mA, VIL = DGND, VIH = 5 V
Power Dissipation 240 mW max

1

All supplies can be varied ±5% and operation is guaranteed.

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= +10 V, V

REFP

2

±4 ppm FSR/°C typ

V

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −10 V, R

REFN

= 2 kΩ. All specifications T

LOAD

= 0 V to 2.5 V p-p

REFP

MIN

to T

, unless otherwise noted.1

MAX

Rev. B | Page 4 of 20

AD5726

AC PERFORMANCE CHARACTERISTICS

AVDD = +5 V ± 5% or +15 V ± 5%, AVSS = −5 V ± 5% or 0 V or −15 V ± 5%, GND = 0 V, V

−10 V, R

= 2 kΩ. All specifications T

LOAD

MIN

to T

, unless otherwise noted.1

MAX

Table 3.

Parameter A Grade B Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time (tS) 13 13 μs typ To 0.01%, ±10 V voltage swing
9 9 μs typ To 0.01%, ±2.5 V voltage swing, AVDD = 5 V
Slew Rate 2.3 2.3 V/μs typ 10% to 90%, ±10 V voltage swing
2 2 V/μs typ 10% to 90%, ±2.5 V voltage swing
Analog Crosstalk 100 100 dB typ
Digital Feedthrough 0.25 0.25 nV-sec typ
Large Signal Bandwidth 90 90 kHz typ 3 dB, V
Major Code Transition Glitch Impulse 30 30 nV-sec typ Code transition = 0x7FF to 0x800 and vice versa

1

Guaranteed by design and characterization, not production tested.

= +2.5 V or +10 V, V

REFP

= 5 V + 10 V p-p, V

REFP

= −2.5 V or 0 V or

REFN

= −10 V

REFN

Rev. B | Page 5 of 20

AD5726

TIMING CHARACTERISTICS

AVDD = +15 V or +5 V, AVSS = −15 V or −5 V or 0 V, GND = 0 V; V
C

= 200 pF. All specifications T

L

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter Limit at T

MIN

, T

Unit Description

MAX

tDS 5 ns Data setup time
tDH 5 ns Data hold time
tCH 13 ns Clock pulse width high
tCL 13 ns Clock pulse width low
t

13 ns Select time

CSS

t

13 ns Deselect delay

CSH

t

20 ns Load disable time

LD1

t

20 ns Load delay

LD2

t

20 ns Load pulse width

LDW

t

20 ns Clear pulse width

CLRW

1

Guaranteed by design and characterization, not production tested.

2

All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Timing Diagrams

CS

t

CSS

SDIN

A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0

= +10 V or +2.5 V; V

REFP

1, 2

= −10 V or −2.5 V or 0 V, R

REFN

t

CSH

LOAD

= 2 kΩ,

SCLK

LDAC

SDIN

SCLK

LDAC

V

CS

OUT

t

LD1

t

t

DS

DH

t

t

CL

CH

t

CSH

t

LD2tLDW

Figure 3. Data Load Timing

t

LD2

06469-002

Figure 2. Data Load Sequence

CLRSEL

t

CLRW

CLR

t

t

S

V

±1LSB

6469-003

OUT

S

±1LSB

6469-004

Figure 4. Clear Timing

Rev. B | Page 6 of 20

AD5726

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents up to
100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVSS to GND +0.3 V to −17 V
AVDD to GND −0.3 V to +17 V
AVSS to AVDD −0.3 V to +34 V
AVSS to V
Current into Any Pin ±15 mA
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to +7 V
Operating Temperature Range

Industrial −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 145°C
Lead Temperature JEDEC industry standard

Soldering J-STD-020

−0.3 V to +AV

REFN

SS

− 2 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6.

Package Type θJA θ

16-Lead SSOP 151 28 °C/W
16-Lead SOIC 124.9 42.9 °C/W
20-Lead SSOP 126 46 °C/W

Unit

JC

ESD CAUTION

Rev. B | Page 7 of 20

AD5726

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AV

1

DD

V

V

V

V

V

V

V

AV

OUTD

OUTC

REFN

REFP

OUTB

OUTA

AV

DD

SS

1

2

3

AD5726

4

TOP VIEW

5

(Not to Scale)

6

7

8

NC = NO CONNECT

16

15

14

13

12

11

10

9

CLRSEL

CLR

LDAC

NC

CS

SCLK

SDIN

GND

06469-005

V

V

V

V

V

OUTD

OUTC

REFN

NC

NC

REFP

OUTB

OUTA

AV

10

SS

2

3

4

AD5726

5

TOP VIEW

(Not to Scale)

6

7

8

9

NC = NO CONNECT

Figure 5. 16-Lead SSOP and 16-Lead SOIC Pin Configuration Figure 6. 20-Lead SSOP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.
16-Lead SSOP/SOIC 20-Lead SSOP

1 1 AV
2 2 V
3 3 V
4 4 V

5 7 V

6 8 V
7 9 V
8 10 AV

Mnemonic

Positive Analog Supply Pin. Voltage range is from 5 V to 15 V.

DD

Buffered Analog Output Voltage of DAC D.

OUTD

Buffered Analog Output Voltage of DAC C.

OUTC

REFN

REFP

Buffered Analog Output Voltage of DAC B.

OUTB

Buffered Analog Output Voltage of DAC A.

OUTA

Negative Analog Supply Pin. Voltage range is from 0 V to −15 V.

SS

9 11 GND
10 12 SDIN

Description

Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale

to V

output. Allowable range is AV

SS

− 2.5 V.

REFP

Positive DAC Reference Input. The voltage applied to this pin defines the full-scale
output voltage. Allowable range is AV

− 2.5 V to V

DD

REFN

Ground Reference Pin.
Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored

when CS

is high.
11 13 SCLK Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
12 14

CS Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin

is logically OR’ed with the SCLK input and disables the serial data input when high.
13 5, 6, 15, 16, 17 NC No Internal Connection.
14 18

Active Low, Asynchronous Load DAC Input. The data currently contained in the

LDAC

serial input register is transferred out to the DAC data registers on the falling edge

15 19

CLR

of LDAC

Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or

, independent of CS. Input data must remain stable while LDAC is low.

midscale (0x800), depending on the state of CLRSEL. The data in the serial input

register is unaffected by this control.
16 20 CLRSEL

Determines the action of CLR

. If high, a clear command sets the internal DAC

registers to midscale (0x800). If low, the registers are set to zero (0x000).

20

19

18

17

16

15

14

13

12

11

+ 2.5 V.

CLRSEL

CLR

LDAC

NC

NC

NC

CS

SCLK

SDIN

GND

06469-033

Rev. B | Page 8 of 20

AD5726

TYPICAL PERFORMANCE CHARACTERISTICS

0.4

0.05

0.3

0.2

0.1

0

–0.1

INL ERROR (L SB)

–0.2

AVDD = +15V

= –15V

AV

SS

–0.3

–0.4

= +10V

V

REFP

= –10V

V

REFN

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

+125°C
+25°C
–40°C

Figure 7. INL Error vs. DAC Code

0.20

0.15

0.10

0.05

0

–0.05

DNL ERRO R (LSB)

–0.10

AVDD = +15V

= –15V

AV

SS

–0.15

–0.20

= +10V

V

REFP

= –10V

V

REFN

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 8. DNL Error vs. DAC Code

+125°C
+25°C
–40°C

0

–0.05

–0.10

–0.15

MAX DNL ERROR (LSB)

AVDD = 5V

–0.20

AV

= 0V

SS

V

= 0V

REFN

T

= 25°C

A

–0.25

1.0 3.0

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

V

(V)

V

REFP

REFP

(V)

REFP

REFP

06469-009

2

06469-010

06469-006

Figure 10. Maximum DNL Error vs. V

1.0
AVDD = +15V
AV

= –15V

0.8

SS

V

= –10V

REFN

T

= 25°C

0.6

A

0.4

0.2

0

–0.2

–0.4

MAX INL ERROR (LSB)

–0.6

–0.8

–1.0

61

7 8 9 10 11

06469-007

Figure 11. Maximum INL Error vs. V

1.0
AVDD = +15V

AV

= –15V

SS

0.8
V

= –10V

REFN

T

= 25°C

A

0.6

0.4

0.2

0

–0.2

–0.4

MAX DNL ERROR (LSB)

–0.6

–0.8

–1.0

612

7 8 9 10 11

V

(V)

REFP

Figure 9. Maximum DNL Error vs. V

REFP

06469-008

0.5
AVDD = 5V
AV

= 0V

SS

0.4
V

= 0V

REFN

T

= 25°C

A

0.3

0.2

0.1

0

–0.1

MAX INL ERROR (LSB)

–0.2

–0.3

–0.4

1.0 3.0

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

Figure 12. Maximum INL Error vs. V

Rev. B | Page 9 of 20

V

REFP

(V)

REFP

06469-011

AD5726

0

AVDD = +15V
AV
V

–0.1

REFP

V

REFN

2k LOAD

–0.2

–0.3

–0.4

–0.5

FULL-SCALE ERROR (LSB)

–0.6

–0.7

–40 –20 120100806040200

0.5
AVDD = +15V
AV

0.4
V

REFP

V

REFN

2k LOAD

0.3

0.2

0.1

0

= –15V

SS

= +10V
= –10V

DAC D

DAC B

DAC A

TEMPERATURE ( °C)

Figure 13. Full-Scale Error vs. Temperature

= –15V

SS

= +10V
= –10V

DAC D

DAC C

06469-012

DAC B

0.3

0.2

0.1

0

–0.1

INL ERROR (L SB)

–0.2

AVDD = 5V
AV

= 0V

SS

= 2.5V

V

–0.3

REFP

= 0V

V

REFN

T

= 25°C

A

–0.4

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 16. Channel-to-Channel Matching

16

14

12

10

(mA)

8

DD

AI

6

DAC A
DAC B
DAC C
DAC D

06469-015

–0.1

ZERO-SCALE ERROR (LSB)

–0.2

–0.3

–40 –20 120100806040200

DAC A

DAC C

TEMPERATURE ( °C)

Figure 14. Zero-Scale Error vs. Temperature

0.3

0.2

0.1

0

INL ERROR (L SB)

–0.1

AVDD = +15V

= –15V

AV

SS

–0.2

–0.3

= +10V

V

REFP

= –10V

V

REFN

= 25°C

T

A

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 15. Channel-to-Channel Matching

DAC A
DAC B
DAC C
DAC D

4

AVDD = +15V

= –15V

AV

SS

= –10V

V

REFN

2

DIGITAL INPUTS HIGH

= 25°C

T

A

0

–7 13

–5–3–11357911

V

(V)

06469-013

Figure 17. AIDD vs. V

REFP

1.7995

= –15V

AV

1.5995

SS

REFP

, All DACs Loaded with Full-Scale Code

V

= +10V V

REFP

REFN

= –10V TA = 25°CAVDD = +15V

06469-016

1.3995

1.1995

0.9995

(mA)

0.7995

REFP

IV

0.5995

0.3995

0.1995

–0.0005

0 4000

500 100015002000250030003500

06469-014

Figure 18. IV

DAC (Code)

vs. DAC Code

REFP

06469-017

Rev. B | Page 10 of 20

AD5726

2

0

–2

–4

–6

–8

GAIN (dB)

–10

AVDD = +15V

= –15V

AV

SS

–12

–14

–16

= 0V ± 100mV

V

REFP

V

= –10V

REFN

FULL-SCAL E CODE LOADED

= 25°C

T

A

10 10M

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 19. Small Signal Response

8

I

6

AVDD = +15V

4

AV

= –15V

SS

V

= +10V

REFP

V
T

REFN
A

= –10V

= 25°C

2

0

–2

–4

POWER SUPPL Y CURRENTS (mA)

–6

DD

I

SS

06469-018

12

AVDD = +15V
AV

= –15V

SS

V

= +10V

REFP

10

V

= –10V

REFN

T

= 25°C

A

8

6

4

OUTPUT SWING (V)

2

0

0.01 100

0.1 1 10

LOAD RESISTANCE (k)

Figure 22. Output Swing vs. Load Resistance

1.0

0.8

0.6

0.4

0.2

0

GLITCH AMPLITUDE (V)

–0.2

0x800  0x7FF ( ±15V SUPPL Y)
0x7FF  0x800 ( ±15V SUPPL Y)
0x800  0x7FF ( ±5V SUPPL Y)
0x7FF  0x800 ( ±5V SUPPL Y)

06469-021

–8

–40 120100806040200

–20

TEMPERATURE ( °C)

Figure 20. Power Supply Currents vs. Temperature

20

AVDD = +15V
AV

= –15V

SS

15

V

= +10V

REFP

V

= –10V

REFN

T

= 25°C

10

A

DATA = 0x000

5

(mA)

0

OUT

I

–5

–10

–15

–20

–15 151050–5–10

V

(V)

OUT

06469-019

6469-020

–0.4

0 1000900800700600500400300200100

TIME (ns)

Figure 23. Major Code Transition Glitch

06469-032

Figure 21. Output Current vs. Output Voltage

Rev. B | Page 11 of 20

AD5726

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL vs. code plot is shown in Figure 7.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot is shown
in Figure 8.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5726 is
monotonic over its full operating temperature range.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
V

− 1 LSB. Full-scale error is expressed in LSBs. A plot of

REFP

full-scale error vs. temperature is shown in Figure 13.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) is loaded to the DAC register.
Ideally, the output voltage should be V
error vs. temperature is shown in Figure 14.

Zero-Scale Error Temperature Coefficient

Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. Zero­scale error temperature coefficient is expressed in ppm FSR/°C.

. A plot of zero-scale

REFN

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.

Slew Rate

The slew rate of a device is a limitation in the rate of change
of the output voltage. The output slewing speed of a voltage­output DAC converter is usually limited by the slew rate of the
amplifier used at its output. Slew rate is measured from 10% to
90% of the output signal and is given in V/μs.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-sec and measured with a full-scale code
change on the data bus.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.

Analog Crosstalk

Analog crosstalk is the dc change in the output level of one
DAC in response to a change in the output of another DAC.
It is measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in decibels.

Major Code Transition Glitch Impulse

Major code transition glitch impulse is the impulse injected
into the analog output when the input code in the DAC register
changes state, but the output voltage remains constant. It is
normally specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major code transition (0x7FF to 0x800 and 0x800 to 0x7FF).

Figure 23.

See

Rev. B | Page 12 of 20

AD5726

A

V

V

THEORY OF OPERATION

The AD5726 is a quad, 12-bit, serial input, unipolar/bipolar
voltage output DAC. It operates from single-supply voltages of
+5 V to +15 V or dual-supply voltages of ±5 V to ±15 V. The
four outputs are buffered and capable of driving a 2 kΩ load.
Data is written to the AD5726 in a 16-bit word format via a
3-wire serial interface.

DAC ARCHITECTURE

Each of the four DACs is a voltage switched, high impedance
(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven by a
pair of switches that connect the resistor to either V

REFP

or V

REFN

OUTPUT AMPLIFIERS

The AD5726 features buffered analog voltage outputs capable of
sourcing and sinking up to 5 mA when operating from ±15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The output amplifiers are short-circuit
protected. The designer should verify that the output load meets
the capabilities of the device, in terms of both output current and
load capacitance. The AD5726 is stable with capacitive loads up
to 2 nF typically. However, any capacitance load increases the
settling time and should be minimized if speed is a concern.

The output stage includes a P-channel MOSFET to pull the
output voltage down to the negative supply. This is very impor­tant in single-supply systems where V

usually has the same

REFN

potential as the negative supply. With no load, the zero-scale
output voltage in these applications is less than 500 μV typically,
or less than 1 LSB when V

= 2.5 V. However, when sinking

REFP

current, this voltage increases because of the finite impedance
of the output stage. The effective value of the pull-down resistor
in the output stage is typically 320 Ω. With a 100 kΩ resistor
connected to 5 V, the resulting zero-scale output voltage is
16 mV. Thus, the best single-supply operation is obtained with
the output load connected to ground, so the output stage does
not have to sink current.

Like all amplifiers, the AD5726 output buffers generate voltage
noise, 5 nV/√Hz typically. This is easily reduced by adding a
simple RC low-pass filter on each output.

REFERENCE INPUTS

The two reference inputs of the AD5726 allow a great deal of
flexibility in circuit design. The user must take care, however,
to observe the minimum voltage input levels on V
to maintain the accuracy shown in the data sheet. These input
voltages can be set anywhere across a wide range within the
supplies, but must be a minimum of 2.5 V apart in any case
(see Figure 24). A wide output voltage range can be obtained
with ±5 V references that can be provided by the AD588 as
shown in Figure 26. Many applications utilize the DACs to

REFP

and V

REFN

.

synthesize symmetric bipolar waveforms, which require an
accurate, low drift bipolar reference. The AD588 provides both
voltages and needs no external components. Additionally, the
part is trimmed in production for 12-bit accuracy over the full
temperature range without user calibration.

V

DD

+2.5V MIN

REFP

0xFFF

+2.5V MIN

0x000

REFN

0V MIN

AV

SS

Figure 24. Output Voltage Range Programming

–10V MIN

1 LSB

06469-022

When driving the reference input, it is important to note that
V

both sinks and sources current, and that the input currents

REFP

of both are code dependent. Many voltage reference products
have limited current sinking capabilities and must be buffered
with an amplifier to drive V
racy. The input, V

, however, has no such requirement.

REFN

For a single 5 V supply, V

to maintain overall system accu-

REFP

is limited to 2.5 V at the most, and

REFP

must always be at least 2.5 V less than the positive supply to ensure
linearity of the device. For these applications, the AD780 is an
excellent low drift 2.5 V reference. It works well with the AD5726
in a single 5 V system, as shown in Figure 28.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.

V

Input Requirements

REFP

The AD5726 uses a DAC switch driver circuit that compensates
for different supplies, reference voltages, and digital code inputs.
This ensures that all DAC ladder switches are always biased
equally, ensuring excellent linearity under all conditions. Thus,
as indicated in the specifications, the V

input of the AD5726

REFP

requires both sourcing and sinking current capability from the
reference voltage source. Many positive voltage references are
intended as current sources only and offer little sinking capability.
The user should consider references such as the AD584, AD586,

AD587, AD588, AD780, and REF43 for such an application.

Rev. B | Page 13 of 20

AD5726

SERIAL INTERFACE

The AD5726 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of a serial
clock input, SCLK. The input register consists of two address
bits, two don’t care bits, and 12 data bits as shown in Table 10.
The timing diagram for this operation is shown in Figure 2.

CS

When
MSB first into the internal shift register on the rising edge of
SCLK. Once all 16 bits of the serial data-word have been input,
the load control
the internal data bus. The two address bits are decoded and used to
route the 12-bit data-word to the appropriate DAC data register.

Operation of CS and SCLK

The CS and SCLK pins are internally fed to the same logical OR
gate and, therefore, require careful attention during a load cycle
to avoid clocking in false data bits. As shown in the timing diagram
in , SCLK must be halted high, or Figure 2
high, during the last high portion of SCLK following the rising
edge that clocked in the last data bit. Otherwise, an additional
rising edge is generated by
CS
shift register. The same must also be considered for the beginning
of the data load sequence.

Coding

The AD5726 uses binary coding. The output voltage can be
calculated from the following equation:

where D is the digital code in decimal.

is low, the data presented to the input, SDIN, is shifted

LDAC

is strobed, and the word is latched onto

CS

must be brought

CS

rising while SCLK is low, causing

to act as the clock and allowing a false data bit into the input

OUT

()

+=

VV

REFN

4096

×−

DVV

REFNREFP

Load DAC (

When asserted, the
digital input that transfers the contents of the input register to
the internal data bus, updating the addressed DAC output. New
data must not be programmed to the AD5726 while the
pin is low.

and CLRSEL

CLR

CLR

The

control allows the user to perform an asynchronous
clear function. Asserting
forcing the DAC outputs to either zero scale (0x000) or midscale

(0x800), depending on the state of CLRSEL as shown in .

CLR

The
When

function is asynchronous and independent of CS.

CLR

value until
registers with either the data held in the input register prior to
the clear or with new data loaded through the serial interface.

Table 8.

CLR

0 0 Zero scale (0x000)
0 1 Midscale (0x800)
1 0 No change
1 1 No change

CLR

Table 9. DAC Address Word Decode Table

A1 A0 DAC Addressed

0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D

)

LDAC

LDAC

pin is an asynchronous, active low,

LDAC

CLR

loads all four DAC registers,

Table 8

returns high, the DAC outputs remain at the clear

LDAC

is strobed, reloading the individual DAC

/CLRSEL Truth Table

CLRSEL DAC Registers

Table 10. Input Register Format

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15

A1 A0 X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Rev. B | Page 14 of 20

AD5726

V

V

APPLICATIONS INFORMATION

POWER-UP SEQUENCE

To prevent CMOS latch-up conditions, powering AVDD, AVSS,
and GND prior to any reference voltages is recommended. The
ideal power-up sequence is GND, AV

, AVDD, V

SS

REFP

, V

REFN

, and
the digital inputs. Noncompliance with the power-up sequence
over an extended period can elevate the reference currents and
eventually damage the device. On the other hand, if the non­compliant power-up sequence condition is as short as a few
milliseconds, the device can resume normal operation without
damage once AV

/AVSS are powered up.

DD

REFERENCE CONFIGURATION

Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either a positive (as
shown in Figure 25) or a negative voltage output. The bipolar
configuration can be either symmetrical (as shown in Figure 26)
or nonsymmetrical.

INPUT

ADR01

BALANCE

GAIN
100k

+15

100k

+

OUTPUT

TRIM

OP1177

10k

+10V OPERATION

0.2µF

V

V

REFN

Figure 25. Unipolar +10 V Operation

+15V

39k

46

12

AD688 FOR ±10V
AD588 FOR ±5V

5

138

3

6.2

1

0.2µF

14

6.2

15

0.2µF

7

1µF

±5 OR ±10V OPERATION

Figure 26. Symmetrical Bipolar Operation

REFP

+15V

AV

DD

AD5726

AV

SS

–15V

+15V

AV

DD

V

REFP

AD5726

V

REFN

AV

SS

–15V

0.1µF10µF

0.1µF10µF

06469-023

06469-024

Figure 26 (symmetrical bipolar operation) shows the AD5726
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of the reference operation.

Adjustments may not be necessary for many applications
because the AD688 is a very high accuracy reference. However,
if additional adjustments are required, adjust the AD5726 full­scale first. Begin by loading the digital full-scale code (0xFFF).
Then, modify the gain adjust potentiometer to attain a DAC
output voltage of 9.9976 V. Next, alter the balance adjust to set
the midscale output voltage to 0.000 V.

The 0.2 μF bypass capacitors shown at their reference inputs in
Figure 26 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 μF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier keeps the amplifier
from oscillating with the capacitive load. This has been found
to be large enough to stabilize this circuit. Larger resistor values
are acceptable if the drop across the resistor does not exceed a V
Assuming a minimum V

of 0.6 V and a maximum current of

BE

BE

2.75 mA, the resistor should be under 200 Ω for the loading of a
single AD5726.

Using two separate references is not recommended. Having two
references may cause different drifts with time and temperature,
whereas with a single reference, most drifts track.

Unipolar positive full-scale operation can usually be set by a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
+10 V full-scale output, the circuit can be configured as shown
in Figure 25. In this configuration, the full-scale value is first set
by adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

0.1µF10µF

+15

+15V

AV

DD

V

REFP

AD5726

V

REFN

AV

SS

0V TO –10V O PERATION

–15V

Figure 27. Unipolar −10 V Operation

V

TEMP

0.2µF

IN

ADR01

U1

GND

V

OUT

TRIM

+15V

U2

V+

OP1177

V–

–15V

06469-025

Figure 27 shows the AD5726 configured for −10 V to 0 V opera­tion. An ADR01 and OP1177 are configured to produce a −10 V
output that is connected directly to V

for the reference voltage.

REFP

.

Rev. B | Page 15 of 20

AD5726

V

*

Single 5 V Supply Operation

For operation with a 5 V supply, the reference voltage should
be set between 1.0 V and 2.5 V for optimum linearity. Figure 28
shows an AD780 used to supply a 2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a +5 V supply with ±5 V tolerance.

5

10µF 0.01µF

INPUT

AD780

GND

OUTPUT

TRIM

0V TO 2.5V OPERATI ON
SINGLE 5V SUPPLY

10k

V

REFP

0.2µF

V

REFN

AV

DD

AD5726

AV

SS

0.1µF10µF

06469-026

Figure 28. 5 V Single-Supply Operation

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration
to the power supply and ground return layout helps to ensure
the rated performance. The AD5726 has a single ground pin
that is internally connected to the digital section as the logic
reference level. The user’s first instinct may be to connect this
pin to the digital ground; however, in large systems, the digital
ground is often noisy because of the switching currents of other
digital circuitry. Any noise introduced at the ground pin could
couple into the analog output. Thus, to avoid error-causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground.

The ground path (circuit board trace) should be as wide as possible
to reduce any effects of parasitic inductance and ohmic drops. A
ground plane is recommended if possible. The noise immunity
of the on-board digital circuitry, typically in the hundreds of milli­volts, is well able to reject the common-mode noise typically seen
between system analog and digital grounds. Finally, connect the
analog and digital ground to each other at a single point in the
system to provide a common reference. This connection is prefer­ably done at the power supply.

Good grounding practice is essential to maintain analog perform­ance in the surrounding analog support circuitry as well. With
two reference inputs and four analog outputs capable of moderate
bandwidth and output current, there is a significant potential
for ground loops. Again, a ground plane is recommended as
the most effective solution to minimize errors due to noise and
ground offsets.

The AD5726 should have ample supply bypassing located as
close to the package as possible. Recommended capacitor values
are 10 μF in parallel with 0.1 μF. The 0.1 μF capacitor should
have low effective series resistance (ESR) and effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies
to handle transient currents due to internal logic switching.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from any
hazardous common-mode voltages that may occur. Isocouplers
provide voltage isolation in excess of 2.5 kV. The serial loading
structure of the AD5726 makes it ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 29 shows a 4-channel isolated interface connected to
the AD5726 using an ADuM1400.

MICROCONTROLLER

V

SERIAL CLOCK O UT

SERIAL DATA O UT

SYNC OUT

CONTROL O UT

ADDITIONAL PINS OMI TTED FO R CLARITY.

IA

V

IB

V

IC

V

ID

ADuM1400*

ENCODE DECODE

ENCODE DECODE

ENCODE DECODE

ENCODE DECODE

V

OA

TO SCLK

V

OB

TO SDIN

V

OC

TO CS

V

OD

TO LDAC

06469-027

Figure 29. Isolated Interface

Rev. B | Page 16 of 20

AD5726

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5726 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
interface (minimum) consisting of a clock signal, a data signal,
and a synchronization signal. The AD5726 requires a 16-bit
data-word with data valid on the falling edge of SCLK.

For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be

LDAC

done under the control of

MC68HC11 Interface

Figure 30 shows an example of a serial interface between the
AD5726 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1); clock polarity bit (CPOL = 0), and
the clock phase bit (CPHA = 1). The SPI is configured by writing
to the SPI control register (SPCR); see the 68HC11 User Manual.
SCK of the MC68HC11 drives the SCLK of the AD5726, the
MOSI output drives the serial data line (SDIN) of the AD5726.

CS

is driven from one of the port lines, in this case, PC7.

The
When data is being transmitted to the AD5726, the

(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle; thus,
to load the required 16-bit word, PC7 is not brought high until
the second 8-bit word has been transferred to the input shift
register of the DAC.

*ADDITIONAL PINS OMIT TED FO R CLARITY.

Figure 30. MC68HC11 to AD5726 Interface

8xC51 Interface

The AD5726 requires a clock synchronized to the serial data.
For this reason, the 8xC51 must be operated in Mode 0. In this
mode, serial data is transferred through RxD, and a shift clock
is output on TxD.

P3.3 and P3.4 are bit-programmable pins on the serial port and

LDAC

CS

are used to drive

and
the LSB of its SBUF register as the first bit in the data stream. The
user must ensure that the data in the SBUF register is arranged
correctly because the DAC expects MSB first. When data is to
be transmitted to the DAC, P3.3 is taken low. Data on RxD is
clocked out of the microcontroller on the rising edge of TxD
and is valid on the falling edge. As a result, no glue logic is
required between this DAC and the microcontroller interface.

.

CS

line

AD5726*MC68HC11*

SDINMOSI

SCLKSCK

CSPC7

6469-028

, respectively. The 8Cx51 provides

The 8xC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC

CS

expects a 16-bit word,

(P3.3) must be left low after the first
eight bits are transferred. After the second byte has been trans­ferred, the P3.3 line is taken high. The DAC can be updated

LDAC

using

via P3.4 of the 8xC51.

AD5726*8xC51*

SDINRxD

SCLKTxD

CSP3.3

LDACP3.4

*ADDITIONAL PINS OMIT TED FO R CLARITY.

Figure 31. 8xC51 to AD5726 Interface

6469-029

PIC16C6x/PIC16C7x Interface

The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit set to 0.
This is accomplished by writing to the synchronous serial port
control register (SSPCON). See the PIC16/17 Microcontroller
User Manual . In this example, I/O Port RA1 is used to pulse

CS

and enable the serial port of the AD5726. This microcontroller
transfers only eight bits of data during each serial transfer opera­tion; therefore, two consecutive write operations are needed.

shows the connection diagram. Figure 32

PIC16C6x/

PIC16C7x*

*ADDITIONAL PINS OMIT TED FO R CLARITY.

Figure 32. PIC16C6x/PIC16C7x to AD5726 Interface

AD5726*

SDINSDO/RC5

SCLKSCLK/RC3

CSRA1

6469-030

Blackfin® DSP Interface

Figure 33 shows how the AD5726 can be interfaced to the
Analog Devices Blackfin DSP. The Blackfin processor has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5726. It also has programmable I/O pins that can

LDAC

be used to set the state of a digital input such as the

ADSP-BF531

*ADDITIONAL PINS OMIT TED FO R CLARITY.

Figure 33. Blackfin DSP to AD5726 Interface

AD5726*

CSSPISELx

SCLKSCK

SDINMOSI

LDACPF10

pin.

06469-031

Rev. B | Page 17 of 20

AD5726

OUTLINE DIMENSIONS

7.50

7.20

6.90

10

0.38

0.22

11

5.60

5.30

8.20

5.00

7.80

7.40

1.85

1.75

1.65

SEATING
PLANE

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

060106-A

2.00 MAX

0.05 MIN

COPLANARITY

0.10

20

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AE

Figure 34. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

6.50

6.20

5.90

16

1

9

5.60

5.30

8.20

5.00

7.80

8

7.40

2.00 MAX

0.05 MIN

COPLANARITY

0.10

1.85

1.75

1.65

0.38

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AC

0.22

SEATING
PLANE

8°
4°
0°

Figure 35. 16-Lead Shrink Small Outline Package [SSOP]

(RS-16)

Dimensions shown in millimeters

Rev. B | Page 18 of 20

0.25

0.09

0.95

0.75

0.55

060106-A

AD5726

C

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

8°
0°

0.33 (0.0130)

0.20 (0.0079)

5

0

.

7

0

.

2

5

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

(

0

.

0

2

9

0

0

9

(

0

.

1.27 (0.0500)

0.40 (0.0157)

5

)

45°

8

)

032707-B

Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5726YRSZ-1REEL
AD5726YRSZ-1500RL7
AD5726YRSZ-500RL7
AD5726YRSZ-REEL
AD5726YRWZ-REEL
AD5726YRWZ-REEL7

1

Z = RoHS Compliant Part.

1

1

−40°C to +125°C 16-Lead SSOP RS-16

1

−40°C to +125°C 20-Lead SSOP RS-20

1

−40°C to +125°C 20-Lead SSOP RS-20

1

−40°C to +125°C 16-Lead SSOP RS-16

−40°C to +125°C 16-Lead SOIC_W RW-16

1

−40°C to +125°C 16-Lead SOIC_W RW-16

Rev. B | Page 19 of 20

AD5726

NOTES

©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06469-0-6/08(B)

Rev. B | Page 20 of 20