Analog Devices AD53509JSQ Datasheet

High-Performance Driver/Comparator

a

FEATURES
250 MHz Operation
Driver/Comparator and Active Load Included
On-Chip Schottky Diode Bridge
52-Lead LQFP Package with Built-In Heat Sink

APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment

PRODUCT DESCRIPTION

The AD53509 is a single chip that performs the pin electronics
functions of driver, comparator and active load in ATE VLSI
and memory testers. In addition, a Schottky diode bridge for the
active load and a VCOM buffer are included internally.

The driver is a proprietary design that features three active
states: Data High Mode, Data Low Mode and Term Mode as
well as an Inhibit State. This facilitates the implementation of
high speed active termination. The output voltage range is –2 V
to +7 V to accommodate a wide variety of test devices. The
output leakage is typically less than 250 nA over the entire sig­nal range.

The dual comparator, with an input range equal to the driver
output range, features built-in latches and ECL-compatible
outputs. The outputs are capable of driving 50 Ω signal lines
terminated to –2 V. Signal tracking capability is upwards of
5 V/ns.

The active load can be set for up to 40 mA load current with
less than a 10 µA linearity error through the entire set range.
I

, IOL and the buffered VCOM are independently adjustable.

OH

On-board Schottky diodes provide high speed switching and low
capacitance.

Also included on the chip is an on-board temperature sensor
whose purpose is to give an indication of the surface tempera­ture of the DCL. This information can be used to measure θ
and θJA or flag an alarm if proper cooling is lost. Output from
the sensor is a current sink that is proportional to absolute tem­perature. The gain is trimmed to a nominal value of 1.0 µA/K.
As an example, the output current can be sensed by using a
10 kΩ resistor connected from 10 V to the THERM (IOUT) pin.
A voltage drop across the resistor will be developed that equals:
10K × 1 µA/K = 10 mV/K = 2.98 V at room temperature.

JC

Active Load on a Single Chip

AD53509

FUNCTIONAL BLOCK DIAGRAM

V

VEEVEEVEEV

CC

CC

51 52 39 40 41 32

34

EE

AD53509

DRIVER

COMPARATOR

ACTIVE LOAD

+1

2,5,89,33,44,46,48

VCCO

NC = NO CONNECT

46

1.0A/K

HQGND2 HQGND

14, 26

CHDCPL

VHDCPL

V

OUT

VLDCPL

VCOMS

OUT_L

THERM

VH

VTERM

DATA

DATA

IOD

IOD

RLD

RLD

HCOMP

LEH

LEH

QH

QH

QL

QL

LEL

LEL

LCOMP

VCOMI

IOLC

IOLRTN

IOHRTN

INHL

INHL

IOHC

V

L

VCCVCCV

47

45

37

38

43

42

49

50

31

V/I

36

35

V/I

PWRGND

39nF

NC

39nF

CLDCPL

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD53509–SPECIFICATIONS

DRIVER SPECIFICATIONS

(All specifications are at TJ = 85C  5C, VS = 11 V  3%, –VS = –6 V = 3% unless otherwise noted. All temperature coefficients are
measured at TJ = 75C to 95C.)

Parameter Min Typ Max Unit Test Conditions

DIFFERENTIAL INPUT CHARACTERISTICS

(DATA to DATA, IOD to IOD, RLD to RLD)

Input Voltage –2 +3 V
Differential Input Range 2 V All Digital Inputs Within a 2 V Range
Bias Current –250 +250 µAV

REFERENCE INPUTS

Bias Currents –50 +50 µAV

OUTPUT CHARACTERISTICS

Logic High Range –2 +7 V DATA = H, VH = –2 V to +7 V, VL = –2 V, VT = 0 V
Logic Low Range –2 +6 V DATA = L, VL = –2 V to +6 V, VH = 7 V, VT = 0 V
Amplitude (V

and VL) 0.1 9 V VL = 0.0 V, VH = 0.1 V, VT = 0 V

H

Absolute Accuracy V

VH Offset –50 +50 mV DATA = H, VH = 0 V, VL = –2 V, VT = –1 V
VH Gain + Linearity Error 0.3 – 5 +0.3 + 5 % of VH + mV DATA = H, VH = –1 V to +7 V, VL = –2 V, VT = –2 V
VL Offset –50 +50 mV DATA = L, VL = 0 V, VH = 5 V, VT = 3 V
VL Gain + Linearity Error –0.3 – 5 +0.3 + 5 % of VL + mV DATA = L, VL = –2 V to +6 V, VH = 7 V, VT = 7 V
Offset TC 0.5 mV/°CV

Output Resistance

VH = –2 V 44 46 48 Ω VL = –2 V, VT = 0 V, I
VH = +7 V 44 46 48 Ω VL = –1 V, VT = 0 V, I
VL = –2 V 44 46 48 Ω VH = 6 V, VT = 0 V, I
VL = +6 V 44 46 48 Ω VH = 7 V, VT = 0 V, I

VH = +3 V 46 Ω VL = 0 V, VT = 0 V, I
Dynamic Current Limit >100 mA C
Static Current Limit –85 +85 mA Output to –2 V, VH = 7 V, VL = –1 V, VT = 0 V

V

ERM

T

Voltage Range –2 +7 V TERM MODE, VT = –2 V to +7 V, VL = 0 V, VH = 3 V

V

Offset –50 +50 mV TERM MODE, VT = 0 V, VL = 0 V, VH = 3 V

ERM

T

V

Gain + Linearity Error –0.3 +10 +0.3 +10 % of V

ERM

T

+ mV TERM MODE, VT = –2 V to +7 V, VL = 0 V, VH = 3 V

SET

Offset TC 0.5 mV/°CV
Output Resistance 44 46 49 Ω I

DYNAMIC PERFORMANCE, (VH AND VL)

Propagation Delay Time 1.5 ns Measured at 50%, VH = +400 mV, VL = –400 mV,

Propagation Delay TC 2 ps/°C Measured at 50%, VH = +400 mV, VL = –400 mV,

Delay Matching, Edge to Edge <100 ps Measured at 50%, VH = +400 mV, VL = –400 mV,

Rise and Fall Times

1 V Swing 0.42 ns Measured 20%–80%, VL = 0 V, VH = 1 V, VT = 0 V

3 V Swing 0.75 ns Measured 20%–80%, VL = 0 V, VH = 3 V, VT = 0 V

5 V Swing 1.65 ns Measured 10%–90%, VL = 0 V, VH = 5 V, VT = 0 V

9 V Swing 3.0 ns Measured 10%–90%, VL = –2 V, VH = 7 V, VT = 0 V
Rise and Fall Time Temperature Coefficient

1 V Swing ±1 ps/°C Measured 20%–80%, VL = 0 V, VH = 1 V

3 V Swing ±2 ps/°C Measured 20%–80%, VL = 0 V, VH = 3 V

5 V Swing ±4 ps/°C Measured 10%–90%, VL = 0 V, VH = 5 V
Overshoot and Preshoot <3 + 50 % of Step + mV VL, VH = –0.1 V, 0.1 V, VL, VH = 0.0 V, 1.0 V

Settling Time

to 15 mV <50 ns VL = 0 V, VH = 0.5 V, VT = –2 V

to 4 mV <10 µsV

= –2 V, +3 V

IN

, VH, VT = 5 V

L

= –2 V, VH = +7 V, VT = 0 V

L

= –2 V, VH = 0 V, VT = –1 V (VH Offset)

L

VL = 0 V, VH = 5 V, VT = 3 V (VL Offset)

= 0, +1, +30 mA

OUT

= 0, –1, –30 mA

OUT

= 0, 1, 30 mA

OUT

= 0, –1, –30 mA

OUT

= –30 mA (Trim Point)

= 39 nF, VH = 6 V, VL = –2 V, VT = 0 V

BYP

OUT

DATA = H and Output to 7 V, VH = 6 V,
VL = –2 V, VT = 0 V, DATA = L

= 0 V, VL = 0 V, VH = 3 V

T

= +30 mA, +1.0 mA, VT = –2.0 V, VH = 3 V, VL = 0 V

OUT

I

= –30 mA, –1.0 mA, VT = +7.0 V, VH = 3 V, VL = 0 V

OUT

I

= ±30 mA, ±1.0 mA, VT = 0 V, VH = 3 V, VL = 0 V

OUT

VT = 0 V

VT = 0 V

VT = 0 V

VL, VH = 0.0 V, 3.0 V, VL, VH = 0.0 V, 5.0 V
VL, VH = –2.0 V, 7.0 V

= 0 V, VH = 0.5 V, VT = –2 V

L

–2–

REV. A

AD53509

Parameter Min Typ Max Unit Test Conditions

Delay Change vs. Pulsewidth 50 ps V

= 0 V, VH = 2 V, Pulsewidth = 2.5 ns/7.5 ns, 30 ns/90 ns

L

Minimum Pulsewidth

3 V Swing 1.4 ns V
5 V Swing 2.0 ns V

= 0 V, VH = 3 V, 90% (2.7 V) Reached, Measure @ 50%

L

= 0 V, VH = 5 V, 90% (4.5 V) Reached, Measure @ 50%

L

Toggle Rate 250 MHz VL = 0 V, VH = 5 V, VDUT > 3.0 V p-p

DYNAMIC PERFORMANCE, INHIBIT

Delay Time, Active to Inhibit 3.3 ns Measured at 50%, VH = +2 V, VL = –2 V, VT = 0 V
Delay Time, Inhibit to Active 2.9 ns Measured at 50%, V

= +2 V, VL = –2 V, VT = 0 V

H

Delay Time Matching (Z) <2 ns Z = Delay Time Active to Inhibit Test (Above)—

Delay Time Inhibit to Active Test (Above)

(Of Worst Two Edges)
I/O Spike 150 mV, p-p VH = 0 V, VL = 0 V, VT = 0 V
Rise, Fall Time, Active to Inhibit 1.6 ns V

= +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)

H

Rise, Fall Time, Inhibit to Active 1.4 ns VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)

DYNAMIC PERFORMANCE , V

Delay Time, VH to V
Delay Time, V

to VH and V

TERM

TERM

Overshoot and Preshoot <3.0 + 75 % of Step + mV VH/VL, V

, VL to V

TERM

TERM

TERM

to V

2.5 ns Measured at 50%, VL = –1 V, VH = +1 V, V

L

2.5 ns Measured at 50%, VL = VH = +0.4 V, V
= (0 V, –1 V), (0 V, –2.0 V),

TERM

TERM

= 0 V

TERM

= –0.4 V

(0 V, 6.0 V)

V

Mode Rise Time 2.2 ns VL = –2 V, VH = +2 V, V

TERM

V

Mode Fall Time 2.2 ns VL = –2 V, VH = +2 V, V

TERM

= 0 V, 20%–80%

TERM

= 0 V, 20%–80%

TERM

PSRR, DRIVE or TERM Mode 35 dB VS = VS ± 3%

Specifications subject to change without notice.

COMPARATOR SPECIFICATIONS

(All specifications are at TJ = 85C  5C. [Outputs terminated in 150  to GND, +VS = 11 V  3% –VS = 6 V  3%, VCCO = 3.3 V unless
otherwise specified.] All temperatures coefficients are measured at TJ = 75C to 95C.)

Parameter Min Typ Max Unit Test Conditions

DC INPUT CHARACTERISTICS

Offset Voltage (VOS) –25 +25 mV CMV = 0 V
Offset Voltage (Drift) 50 µV/°C CMV = 0 V
HCOMP, LCOMP Bias Current –50 +50 µAV

= 0 V

IN

Voltage Range (VCM) –2 +7.0 V
Differential Voltage (V

) 9.0 V

DIFF

Gain and Linearity –0.05 +0.05 % FSR VIN = –2 V to +7 V (9 V FSR)

LATCH ENABLE INPUTS

Logic “1” Current (IIH) 250 µA LEA, LEA, LEB, LEB = +3 V
Logic “0” Current (IIL) –250 µA LEA, LEA, LEB, LEB = –2 V
Logic Input Range –2 +3 V

DIGITAL OUTPUTS

Logic “1” Voltage (VOH) VCCO – 0.98 V Q or Q, 16.7 mA Load
Logic “0” Voltage (VOL) VCCO – 1.5 V Q or Q, 10 mA Load
Slew Rate 1 V/ns
VCCO Range 0 8 V

SWITCHING PERFORMANCE

Propagation Delay

Input to Output 1.8 ns VIN = 2 V p-p,
Latch Enable to Output 2 ns HCOMP = 1 V, LCOMP = 1 V
Propagation Delay Temperature Coefficient 2 ps/°C

Propagation Delay Change with Respect to

Slew Rate: 0.5 V, 1.0 V, 3.0 V/ns <± 100 ps VIN = 0 V to 5 V
Slew Rate: 5.0 V/ns <±350 ps VIN = 0 V to 5 V
Amplitude: 1.0 V, 3.0 V, 5.0 V <± 200 ps VIN = 1.0 V/ns
Equivalent Input Rise Time 450 ps VIN = 0 V to 3 V, 3 V/ns

Pulsewidth Linearity <±200 ps VIN = 0 V to 3 V, 3 V/ns, PW = 3 ns–8 ns
Settling Time 25 ns Settling to ±8 mV, VIN = 1 V to 0 V
Latch Timing

Input Pulsewidth 1.68 ns

Setup Time 1.0 ns

Hold Time 1.1 ns

Hysteresis 6 mV Latch Inputs Programmed for Hysteresis

Specifications subject to change without notice.

–3–REV. A