2 stereo headphone amplifiers
Microsoft Vista Premium logo for notebook and desktop
95 dB audio outputs, 90 dB audio inputs
Internal 32-bit arithmetic for greater accuracy
Impedance and presence detection on all jack pins
Digital synthesis PCBeep
C/LFE channel swapping
2 general-purpose digital I/O (GPIO) pins
Advanced power management modes
EAPD control for internal speakers
48-lead, Pb-free LFCSP_VQ package
Supports 44.1 kHz, 48, kHz 88.2 kHz, and 96 kHz sample rates
16-, 20-, and 24-bit data widths; PCM and AC3 formats
Digital PCM gain control
DEDICATED AUXILIARY PINS
Stereo CD input w/GND sense
Mono out pin for internal speakers or telephony
Analog PCBeep input pin
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Changed analog and digital power supply specifications......6
Changed analog and digital specifications and revised footnotes
in Power-Down States ............................................... 6
Changed revision ID in Widget Parameters .................. 13
Rev. A | Page 2 of 16 | April 2008
GENERAL DESCRIPTION
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AD1882
The AD1882 audio codec and SoundMAX® software provides
superior HD audio quality that exceeds Vista Premium performance. The AD1882 has six DACs and four ADCs, two stereo
headphone ports, C/LFE swapping, digital and analog PCBeep,
and S/PDIF output, making the AD1882 the right choice for
desktop PCs where performance is the primary consideration.
The jack retasking feature on this product supports various configurations including platforms for 5.1 on 5 or 3 jacks, and front
panel jack retasking.
The AD1882 is available in a 48-lead RoHS compliant lead
frame chip scale package in both reels and trays. See Ordering
Guide on Page 16.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the AD1882
SoundMAX codec’s architecture and functionality. Additional
information on the AD1882 is available in the AD1882 Programmers Reference Manual. Please contact your local Analog
Devices, Inc., sales representative for more information. For
information on SoundMAX codecs and software, see Analog
Devices website at www.analog.com/soundMAX.
JACK CONFIGURATION
The guidelines shown in Table 1 through Table 3 should be
used when selecting ports for particular functions.
Table 2. Typical Desktop Configuration with 5.1 on 3 Jacks
PortFunction
Port AFront Panel Headphone
Port BFront Panel Microphone
Port CRear Panel Line-In/Surround
Port DRear Panel Line-Out/Headphone
Port ERear Panel Microphone / C/LFE
Table 3. Typical Notebook Configuration
PortFunction
Port AHeadphone
Port BMicrophone
Port C Internal Microphone
Port D Internal Stereo Speakers
Port E Docking Station Line-In/Microphone
Table 1. Typical Desktop Configuration with Discreet Jacks
PortFunction
Port AFront Panel Headphone
Port BFront Panel Microphone
Port CRear Panel Line-In
Port DRear Panel Line-Out/Headphone
Port E Rear Panel Microphone
Port FRear Panel Surround
Port GRear Panel C/LFE
Rev. A | Page 3 of 16 | April 2008
AD1882
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SPECIFICATIONS
TEST CONDITIONS
ParameterTest Condition
Tem pe ra tu re
Digital Supply
Analog Supply
MIC_BIAS_IN (via Low-Pass Filter)
Sample Rate f
Input Signal (Frequency Sine Wave)
Amplitude for THD + N
Analog Output Pass Band
DAC10 kΩ Output Load: Line Out Tests
ADC0 dB Gain
S
PERFORMANCE
ParameterMinTypMaxUnit
Line-Out Drive (10 kΩ Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
Headphone Drive (32 Ω Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to f
Signal-to-Noise Ratio
Input Ports (Pin to ADC, Mic Boost = 0 dB)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to f
Signal-to-Noise Ratio
A-Weighted)
S
A-Weighted)
S
25°C
3.3 V
3.3 V
5.0 V
48 kHz
1008 Hz
–3.0 dB Full Scale
20 Hz to 20 kHz
32 Ω Output Load: Headphone Tests
–85
95
95
–83
95
95
–81
90
90
dB
dB
dB
dB
dB
dB
dB
dB
dB
GENERAL SPECIFICATIONS
Table 4. AD1882 General Specifications
ParameterMinTypMaxUnit
DIGITAL DECIMATION AND INTERPOLATION FILTERS—f
Pass Band00.4 f
Pass-Band Ripple±0.005dB
Stop Band0.6 f
Stop-Band RejectiondB
Group Delay+20–1001/f
Group Delay Variation Over Pass Band0μs
ANALOG-TO-DIGITAL CONVERTERS
Resolution24Bits
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)±0.5dB
ADC Offset Error
ADC Crosstalk
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)–85dB
Line Inputs to Other–100–80dB
1
1
= 8 kHz to 192 kHz
S
2
1
S
S
±10%
±5mV
Hz
Hz
S
Rev. A | Page 4 of 16 | April 2008
AD1882
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Table 4. AD1882 General Specifications (Continued)
ParameterMinTypMaxUnit
DIGITAL TO ANALOG CONVERTERS
Resolution 24Bits
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)±0.5dB
Total Audible Out-of-Band Energy (Measured from 0.6 × f
DAC Crosstalk (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)
DAC VOLUMES
Step Size (DAC-0, DAC-1, DAC-2)1.5dB
Output Gain/Attenuation Range–58.50dB
Mute Attenuation of 0 dB Fundamental
1
ADC VOLUMES
Step Size (ADCSEL-0, ADCSEL-1)1.5dB
PGA Gain/Attenuation Range–58.5+22.5dB
Mute Attenuation of 0 dB Fundamental
1
ANALOG MIXER
Signal-to-Noise Ratio (SNR) Input to Output
CD to Port D Output
Port B, C, or E to Port D Output
Port A to Port D Output
Port D to Port A Output
Step Size: All Mixer Inputs1.5dB
Input Gain/Attenuation Range: All Mixer Inputs–34.5+12.0dB
ANALOG LINE LEVEL OUTPUTS
Full-Scale Output Voltage1.01.0V rms
Ports C, E, F, and G Mono Out 2.83V p-p
Table 4. AD1882 General Specifications (Continued)
ParameterMinTypMaxUnit
Digital GPIO Pins: GPIO_0, GPIO_1/EAPD
Input Signal High (V
Input Signal Low (V
Input Leakage Current (Signal High, (I
Input Leakage Current (Signal Low, (I
Output Signal High (V
Output Signal Low (V
)DV
IH
)0DV
IL
)I
OH
)I
OL
) 150nA
IH
)50μA
IL
= –500 μADV
OUT
= +1500 μA0DV
OUT
S/PDIF_OUT
Output Signal High (VOH)I
Output Signal Low (V
)I
OL
= –500 μADV
OUT
= +1500 μA0DV
OUT
Power Supply
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DV
) 3.3 V ± 10%
IO
Power Supply Range
Power Dissipation
Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1 80 dB
1
Guaranteed but not tested.
2
Measurements reflect main ADC.
3
RMS values assume sine wave input.
× 0.60DV
IO
× 0.72DV
IO
× 0.72DVIO V
IO
3.13 3.30
IO
× 0.24 V
IO
IO
× 0.10 V
IO
× 0.10 V
IO
3.46V
116
35
2.973.30
3.63V
162
49
2.973.30
3.63V
3.96
1.20
V
V
mW
mA
mW
mA
mW
mA
HD AUDIO LINK SPECIFICATIONS
HD Audio signals comply with the High Definition Audio specifications. Please refer to these specifications at
www.intel.com/standards/hdaudio.
POWER-DOWN STATES
Table 5. Power-Down States
ParameterID
Function Node In D0, All Nodes Active4935mA
Function Node in D3160.7mA
Codec in RESET
Individual block power savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (and Associated Amps) Saves
MIC_BIAS Powered Down Saves
1
Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 Ω and high-Z states remain unaffected by the MIC_BIAS power state.
1
TypIA
VDD
TypUn it
VDD
33mA
6
5
0
0
6
4.4
3
1.0
mA
mA
mA
mA
Rev. A | Page 6 of 16 | April 2008
AD1882
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Power SuppliesRating
Digital (DV
Digital I/O (DV
Analog (AV
Input Current (Except Supply Pins) ±10.0 mA
Analog Input Voltage (Signal Pins) –0.30 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins)–0.30 V to DV
Ambient Temperature (Operating) 0°C to +70°C
Storage Temperature–65°C to +150°C
)–0.30 V to +3.65 V
DD
)–0.30 V to +3.65 V
IO
)–0.30 V to +3.65 V
DD
+ 0.3 V
IO
ESD CAUTION
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
= T
AMB
T
CASE
PD = power dissipation in W
= thermal resistance (case-to-ambient)
θ
CA
θ
= thermal resistance (junction-to-ambient)
JA
θ
= thermal resistance (junction-to-case)
JC
All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7.
Packageθ
LFCSP_VQ471532°C/W
– (PD × θCA)
CASE
= case temperature in °C
JA
θ
JC
θ
CA
Unit
Rev. A | Page 7 of 16 | April 2008
AD1882
1
2
3
4
5
6
7
8
9
10
11
12
242313 141516 17 18 19 2021 22
34
33
36
35
25
26
27
28
29
30
31
32
44 4347484546373839404142
AD1882JCPZ
TOP VIEW
(NotToScale)
DV
CORE
GPIO_0
DV
I/O
DV
SS
SDATA_OUT
BIT_CLK
DV
SS
SDATA_IN
DV
DD
SYNC
RESET
PCBEEP
PORT-D_R
PORT-D_L
P
O
R
T
-
C
_
R
P
O
R
T
-
C
_
L
P
O
R
T
-
B
_
R
P
O
R
T
-
E
_
L
P
O
R
T
-
F
_
R
P
O
R
T
-
F
_
L
P
O
R
T
-
B
_
L
P
O
R
T
-
E
_
R
C
D
_
L
C
D
_
R
C
D
_
G
N
D
S
E
N
S
E
_
A
/
S
R
C
_
B
SENSE_B/SRC_A
P
O
R
T
-
A
_
L
M
O
N
O
_
O
U
T
G
P
I
O
_
1
/E
A
P
D
P
O
R
T
-
G
_
R
A
V
D
D
P
O
R
T
-
G
_
L
P
O
R
T
-
A
_
R
A
V
S
S
S
P
D
I
F
_
O
U
T
MIC_BIAS_IN
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS-E
AV
DD
AV
SS
VREF_FLT
RESERVED (NC)
RESERVED(NC)
R
E
S
E
R
V
E
D
(
N
C
)
R
E
S
E
R
V
E
D
(
N
C
)
R
E
S
E
R
V
E
D
(
N
C
)
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. AD1882 48-Lead Package and Pinout
Rev. A | Page 8 of 16 | April 2008
AD1882
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Table 6. AD1882 Pin Descriptions
MnemonicPin No.FunctionDescription
DIGITAL INTERFACE
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
DIGITAL I/O
GPIO_0
GPIO_1/EAPD
SPDIF_OUT
JACK SENSE AND EAPD
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
CD_L
CD_GND
VREF_FLT27OVoltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels
(typically used to support C/LFE or shared C/LFE function).
5
6
8
10
11
2
47
48
13
34
12
14
15
16
17
18
19
20
21
22
23
24
35
36
39
40
41
43
44
28
29
31
1OCAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
I
I
I/O
I
I
I/O
I/O
O
I/O
I/O
LI
LI, MIC, LO, SWAP
LI, MIC, LO, SWAP
I/O
I/O
LI
LI
LI
LI, MIC, HP, LO
LI, MIC, HP, LO
LI, MIC, LO
LI, MIC, LO
LI, HP, LO
LI, HP, LO
LI, MIC, HP, LO
LO
LI, MIC, HP, LO
LO, SWAP
LO, SWAP
O
O
O
Link Serial Data Output. AD1882 input stream. Clocked on both edges of the
BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1882 output stream Clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. AD1882 master hardware reset
General-Purpose Input/Output Pin. Digital signal used to control external circuitry.
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. Defaults to high-Z. When used as EAPD: high-Z = amp-on, DV
S/PDIF_OUT. Supports S/PDIF output.
JACK SENSE A-D Input/Sense B Drive.
JACK SENSE E-H Input/Sense A Drive.
Monaural Input from System for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to
AGND via 0.1 mF capacitor if not in use as CD_GND.
CD Audio Right Channel.
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Front Panel Headphone/Line-Out.
Rear Panel C/LFE Output.
Rear Panel C/LFE Output.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
parallel between Pin 1 and DV
connected in parallel between Pin 27 and AV
(Pin 4).
SS
(Pins 26, 42).
SS
= amp off.
SS
Rev. A | Page 9 of 16 | April 2008
AD1882
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Table 6. AD1882 Pin Descriptions (Continued)
MnemonicPin No.FunctionDescription
POWER AND GROUND
(3.3V) 3IConnect to the I/O Voltage Used for the HD Audio Controller Signals.
DV
I/O
DV
SS
(3.3 V)9IDigital Supply Voltage 3.3 V. This is regulated down to DV
DV
DD
(3.3 V)25, 38ICAUTION: DO NOT APPLY 5.0 V TO THESE PINS!
AV
DD
MIC_BIAS_IN33ISource Power for Microphone Bias Boost Circuitry.
AV
SS
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels
(typically used to support C/LFE or shared C/LFE function).
4, 7IDigital Supply Return (Ground).
on Pin 1 to supply the
internal digital core internal to the AD1882.
Analog supply voltage 3.3 V ONLY.
Note: AV
audio performance.
26, 42IAnalog Supply Return (Ground). AVSS should be connected to DVSS using a
conductive trace under, or close to, the AD1882.
supplies should be well regulated and filtered as supply noise degrades
DD
CORE
Rev. A | Page 10 of 16 | April 2008
AD1882
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HD AUDIO WIDGETS
In the following table, node IDs that are not shown are reserved
for future use.
Table 7. HD Audio Widgets
Node ID NameType IDTypeDescription
00ROOTxRootDevice identification
01FUNCTIONxFunctionDesignates this device as an audio codec
02S/PDIF DAC0Audio OutputS/PDIF digital stream output interface
03DAC_00Audio OutputHeadphone/surround side (7.1) channel digital/audio converters
04DAC_10Audio OutputStereo front channel digital/audio converters
05DAC_20Audio OutputStereo C/LFE channel digital/audio converters
08ADC_01Audio InputStereo record channel 1 audio/digital converters
09ADC_11Audio InputStereo record channel 2 audio/digital converters
0BS/PDIF Mix Selector3Audio SelectorSelects which ADC drives the S/PDIF mixer
0CADC Selector 03Audio SelectorSelects and amplifies/attenuates the input to ADC_0
0DADC Selector 13Audio SelectorSelects and amplifies/attenuates the input to ADC_1
10Digital Beep7Beep GeneratorInternal digital PCBeep signal
11Port A (Headphone)4Pin ComplexFront panel headphone/microphone jack
12Port D (Front L/R)4Pin ComplexRear panel front/headphone jack
13Mono Out4Pin ComplexMonorail output pin (internal speakers or telephony system)
14Port B (Front Mic)4Pin ComplexFront panel microphone/headphone jack
15Port C (Line In)4Pin ComplexRear panel line-in jack
16Port F (Surr Back)4Pin ComplexRear panel surround-rear (5.1) jack
17Port E (Rear Mic)4Pin ComplexRear panel mic jack
18CD In4Pin ComplexAnalog CD input
19Mixer Power-Down5Power WidgetPowers down the analog mixer and associated amps
1AAnalog PCBeep4Pin ComplexExternal analog PCBeep signal input
1BS/PDIF Out4Pin ComplexS/PDIF output pin
1DS/PDIF Mixer2Audio MixerMixes the selected ADC with the digital stream to drive S/PDIF out
1EMono Out Mixer2Audio MixerSelects which source drives the mono out signal
20Analog Mixer2Audio MixerMixes individually gainable analog inputs
21Mixer Output Atten3Audio SelectorAttenuates the mixer output to drive the Port mixers
22Port A Mixer2Audio MixerMixes the Port A selected DAC and mixer output amps to drive Port A
23VREF Power-DownFVendor DefinedPowers down the internal and external VREF circuitry
24Port G (C/LFE)4Pin ComplexRear panel C/LFE jack
26Port E Mixer2Audio MixerMixes DAC_1 and mixer output amps to drive Port E
27Port G Mixer2Audio MixerMixes DAC_1 and mixer output amps to drive Port G
29Port D Mixer2Audio MixerMixes DAC_0 and mixer output amps to drive Port D
2APort F Mixer2Audio MixerMixes DAC_2 and mixer output amps to drive Port F
2CPort C Mixer2Audio MixerMixes the Port C selected DAC and mixer output amps to drive Port C
2DStereo Mix Down2Audio MixerMixes the stereo L/R channels to drive mono output
2FBIAS Power-DownFVendor DefinedPowers down the internal MIC_BIAS_FILT and all MIC_BIAS pins
37Port A Out Selector3Audio SelectorSelects the Port A DAC (0, 1)
39Port B Boost3Audio SelectorMicrophone boost amp for Port B
3APort C Boost3Audio SelectorMicrophone boost amp for Port C
3CPort E Boost3Audio SelectorMicrophone boost amp for Port E
Rev. A | Page 11 of 16 | April 2008
AD1882
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HD AUDIO PARAMETERS
The SSID value is set on codec power-up only. SSID is not reset
by link or soft reset in order to preserve modifications by BIOS
control.
In Table 12, default configuration values are set on codec
power-up only. Default configuration values are not reset by
link or soft reset to preserve modifications by BIOS control.
Table 12. Default Configuration Bytes
31:3029:2827:2423:2019:1615:1287:43:0
Location
Connectivity
Port A (Headphone) 0221401F JackExternal FrontHP Out1/8” JackGreen01F
Port D (Front L/R)01014010 JackExternal RearLine Out1/8” JackGreen010
Mono Out901701F0 FixedInternal N/ASpeakerOther Analog Unknown 1F0
Port B (Front Mic)02A190F0 JackExternal FrontMic In1/8” JackPink0F0
Port C (Line In)01813021 JackExternal RearLine In1/8” JackBlue021
Port F (Surr Back)01011012 JackExternal RearLine Out1/8” JackBlack012
Port E (Rear Mic)01A19020 JackExternal RearMic In1/8” JackPink020
CD IN9933012E FixedInternal Special 3 CDATAPIUnknown 12E
Analog PCBeep90F701F0 FixedInternal N/AOtherOther Analog Unknown 1F0
S/PDIF Out014511F0 JackExternal RearSPDIF OutOpticalBlack1F0
Port G (C/LFE)01016011 JackExternal RearLine Out1/8” JackOrange011
Def. Device Conn TypeColor
Misc.
JD Over
Ride
Def Assn SequenceNameValueChasisPosition
Rev. A | Page 15 of 16 | April 2008
AD1882
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
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OUTLINE DIMENSIONS
Dimensions are shown in millimeters.
Figure 3. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm x 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD1882JCPZ
AD1882JCPZ-RL
1
Z = RoHS Compliant Part.
1
1
0°C to 70°C 48-Lead LFCSP_VQCP-48-1
0°C to 70°C 48-Lead LFCSP_VQ, 13” Tape and ReelCP-48-1