Analog Devices AD1847JST, AD1847JP Datasheet
Serial-Port 16-Bit
a
FEATURES
Single-Chip Integrated SD Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
PRODUCT OVERVIEW
The AD1847 SoundPort® Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multimedia applications requiring operation from a single +5 V supply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
ANALOG
I/O
LINE 1
INPUT
LINE 2
INPUT
AUX 1
INPUT
LINE
OUTPUT
AUX 2
INPUT
L
R
L
R
L
R
L
R
L
R
ANALOG
SUPPLY
DIGITAL
SUPPLY
M
U
X
GAIN/ATTEN/MUTE
L
∑
R
GAIN/ATTEN
/MUTE
GAIN/ATTEN
/MUTE
L
GAIN
R
GAIN
ATTEN/
MUTE
ATTEN/
∑
MUTE
∑∆ A/D
CONVERTER
∑∆ A/D
CONVERTER
∑∆ D/A
CONVERTER
∑∆ D/A
CONVERTER
REFERENCE
SoundPort Stereo Codec
AD1847
I
S
A
B
U
S
Figure 1. Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of ∑∆ analog-to-digital converters (ADCs) and a stereo pair of ∑∆ digital-to-analog converters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs’ output can be digitally
mixed with the DACs’ input.
The pair of 16-bit outputs from the ADCs is available over a serial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit µ-law or A-law
companded digital data.
CLOCK
OUT
CRYSTALS
2 2
OSCILLATORS
ATTEN
ATTEN
∑
ATTEN
AD1847
ASIC AD1847
DSP
(Continued on page 7)
DIGITAL
I/O
RESET
POWER
2
DOWN
BUS
MASTER
TIME SLOT
INPUT
TIME SLOT
OUTPUT
SERIAL DATA
OUTPUT
SERIAL DATA
INPUT
EXTERNAL
CONTROL
SERIAL BIT
CLOCK
FRAME
SYNC
µ/A
LAW
S
µ/A
µ/A
µ/A
E
R
I
A
L
P
O
R
T
LAW
LAW
∑
LAW
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2.25V
® Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD1847–SPECIFICA TIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature 25 °C DAC Output Conditions
Digital Supply (V
Analog Supply (V
Word Rate (F
Input Signal 1007 Hz No Output Load
Analog Output Passband 20 Hz to 20 kHz Mute Off
FFT Size 4096 ADC Input Conditions
V
IH
V
IL
V
OH
V
OL
ANALOG INPUT
Full-Scale Input Voltage (RMS Values Assume Sine Wave Input)
Line1, Line2, AUX1, AUX2 1 V rms
Input Impedance
Line1, Line2, AUX1, AUX2† 10 kΩ
Input Capacitance† 15 pF
) 5.0 V 0 dB Attenuation
DD
) 5.0 V Full-Scale Digital Inputs
CC
) 48 kHz 16-Bit Linear Mode
S
2.4 V 0 dB Gain
0.8 V –3.0 dB Relative to Full Scale
2.4 V Line Input
0.4 V 16-Bit Linear Mode
Min Typ Max Units
2.54 2.8 3.10 V p-p
PROGRAMMABLE GAIN AMPLIFIER—ADC
Min Typ Max Units
Step Size (All Steps Tested, –30 dB Input) 1.10 1.5 1.90 dB
PGA Gain Range Span† 21.0 24.0 dB
AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS
Min Typ Max Units
Step Size (+12 dB to –28.5 dB, Referenced to DAC Full Scale) 1.3 1.5 1.7 dB
(–30 dB to –34.5 dB, Referenced to DAC Full Scale) 1.1 1.5 1.9 dB
Input Gain/Attenuation Range Span† 45.5 47.5 dB
AUX Input Impedance† 10 kΩ
DIGITAL DECIMATION AND INTERPOLATION FILTERS†
Min Max Units
Passband 0 0.4 3 F
S
Hz
Passband Ripple –0.1 +0.1 dB
Transition Band 0.4 3 F
Stopband 0.6 3 F
S
S
0.6 3 F
S
Hz
∞ Hz
Stopband Rejection 74 dB
Group Delay 30/F
S
Group Delay Variation Over Passband 0 µs
–2–
REV. B
AD1847
ANALOG-TO-DIGITAL CONVERTERS
Min Typ Max Units
Resolution 16 Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) 70 dB
THD+N (Referenced to Full Scale) 0.040 %
–68 dB
Signal-to-Intermodulation Distortion† 83 dB
ADC Crosstalk†
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) –80 dB
Line1 to Line2 (Input Line1, Ground and Select Line2, Read Both Channels) –80 dB
Line to AUX1 –80 dB
Line to AUX2 –80 dB
Line to DAC –80 dB
Gain Error (Full-Scale Span Relative to V
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.2 dB
DC Offset ±55 LSB
DIGITAL-TO-ANALOG CONVERTERS
Resolution 16 Bits
Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) 76 dB
THD+N (Referenced to Full Scale) 0.025 %
Signal-to-Intermodulation Distortion† 86 dB
Gain Error (Full-Scale Span Relative to V
Interchannel Gain Mismatch (Difference of Gain Errors) ±0.2 dB
DAC Crosstalk† (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) –80 dB
Total Out-of-Band Energy† (Measured from 0.6 3 F
Audible Out-of-Band Energy (Measured from 0.6 3 FS to 22 kHz, Tested at FS = 5.5 kHz) –55 dB
DAC ATTENUATOR
Step Size (0 dB to –22.5 dB) (Tested at Steps 0 dB, –19.5) 1.3 1.5 1.7 dB
Step Size (–24 dB to –94 dB) 1.0 1.5 2.0 dB
Output Attenuation Range Span† –93 95 dB
DIGITAL MIX ATTENUATOR
Step Size (0 dB to –22.5 dB) (Tested at Steps 0 dB, –19.5) 1.3 1.5 1.7 dB
Step Size (–24 dB to –94 dB) 1.0 1.5 2.0 dB
Output Attenuation Range Span† –93.5 95.5 dB
ANALOG OUTPUT
Full-Scale Line Output Voltage 0.707 V rms
V
= 2.35* 1.80 2 2.20 V p-p
REFI
Line Output Impedance† 600 Ω
External Load Impedance 10 kΩ
Output Capacitance† 15 pF
External Load Capacitance 100 pF
V
(Clock Running) 2.00 2.50 V
REF
V
Current Drive 100 µA
REF
V
REFI
Mute Attenuation of 0 dB –80 dB
Fundamental† (LOUT)
Mute Click† 8mV
(|Muted Output Minus Unmuted
Midscale DAC Output|)
*Full-scale line output voltage scales with V
†Guaranteed, Not Tested.
REF
(e.g., V
REV. B
) ±10 %
REFI
Min Typ Max Units
–72 dB
) ±10 %
REFI
to 100 kHz) –50 dB
S
Min Typ Max Units
Min Typ Max Units
Min Typ Max Units
2.35 V
(typ) – 2.0 V 3 (V
OUT
REF
/2.35)).
–3–
AD1847
SYSTEM SPECIFICATIONS
Min Typ Max Units
System Frequency Response† ±0.3 dB
(Line In to Line Out, 20 Hz to 20 kHz)
Differential Nonlinearity† ±1/2 Bit
Phase Linearity Deviation† 1 Degrees
STATIC DIGITAL SPECIFICATIONS
Min Max Units
High Level Input Voltage (VIH)
Digital Inputs 2.0 V
XTAL1/2I 2.4 V
Low Level Input Voltage (V
High Level Output Voltage (V
Low Level Output Voltage (V
Input Leakage Current (GO/NOGO Tested) –10 +10 µA
Output Leakage Current (GO/NOGO Tested) –10 +10 µA
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
) 0.8 V
IL
) IOH = 1 mA 2.4 V
OH
) IOL = 4 mA 0.4 V
OL
DD
Min Typ Max Units
V
Serial Frame Sync Period (t
Clock to Frame Sync [SDFS] Propagation Delay (t
Data Input Setup Time (t
Data Input Hold Time (t
Clock to Output Data Valid (t
Clock to Output Three-State [High-Z] (t
Clock to Time Slot Output [TSO] Propagation Delay (t
RESET and PWRDOWN Lo Pulse Width (t
POWER SUPPLY
) 1/0.5 F
1
)15 ns
S
)15 ns
H
) 25 ns
DV
)20ns
HZ
RPWL
)20ns
PD1
)20ns
PD2
) 100 ns
S
µs
Min Max Units
Power Supply Range – Digital & Analog 4.75 5.25 V
Power Supply Current – Operating (10 kΩ Line Out Load) 140 mA
Analog Supply Current – Operating (10 kΩ Line Out Load) 70 mA
Digital Supply Current – Operating (10 kΩ Line Out Load) 70 mA
Analog Power Supply Current – Power Down 400 µA
Digital Power Supply Current – Power Down 400 µA
Power Dissipation – Operating (Current 3 Nominal Supply) 750 mW
Power Dissipation – Power Down (Current 3 Nominal Supply) 4 mW
Power Supply Rejection (@ 1 kHz)†
(At Both Analog and Digital Supply Pins, ADCs) 45 dB
(At Both Analog and Digital Supply Pins, DACs) 55 dB
CLOCK SPECIFICATIONS†
Min Max Units
Input Clock Frequency 27 MHz
Recommended Clock Duty Cycle ±10 %
Initialization/Sample Rate Change Time
16.9344 MHz Crystal Selected at Power-Up 171 ms
24.576 MHz Crystal Selected at Power-Up 171 ms
16.9344 MHz Crystal Selected Subsequently 6 ms
24.576 MHz Crystal Selected Subsequently 6 ms
†Guaranteed, not tested.
Specifications subject to change without notice.
–4–
REV. B
AD1847
WARNING!
ESD SENSITIVE DEVICE
44 SDFS
43 SDO
42 SDI
41 GNDD
40 V
DD
39 SCLK
38 CLKOUT
37 XTAL2O
36 XTAL2I
35 XTAL1O
34 XTAL1I
33
32
31
30
29
28
27
26
25
24
23
PIN 1 IDENTIFIER
R_LINE1
V
REF
V
REFI
GNDA
V
CC
PWRDOWN
RESET
GNDD
V
DD
TSI
TSO
1
2
3
4
5
6
7
8
9
11
10
V
DD
GNDD
XCTL1
XCTL0
GNDD
V
DD
BM
L_AUX2
R_AUX2
L_OUT
N/C
R_LINE2 12
RFILT 13
GNDA 14
LFILT 15
L_LINE2 16
L_LINE1 17
GNDA 18
L_AUX1 20
R_AUX1 21
R_OUT 22
V
CC
19
Top View
(Not to Scale)
AD1847JST
N/C = NO CONNECT
ABSOLUTE MAXIMUM RATINGS*
Min Max Units
Power Supplies
Digital (V
Analog (V
) –0.3 6.0 V
DD
) –0.3 6.0 V
CC
Input Current
(Except Supply Pins) ±10.0 mA
Model Range Description Option*
AD1847JP 0 °C to +70°C 44-Lead PLCC P-44A
AD1847JST 0°C to +70°C 44-Lead TQFP ST-44
*P = PLCC; ST = TQFP.
ORDERING GUIDE
Temperature Package Package
Analog Input Voltage (Signal Pins) –0.3 (VA+) + 0.3 V
Digital Input Voltage (Signal Pins) –0.3 (VD+) + 0.3 V
Ambient Temperature (Operating) 0 +70 °C
Storage Temperature –65 +150 °C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1847 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PINOUTS
44-Lead PLCC 44-Lead TQFP
DD
SCLK
23
L_LINE1
XTAL2O
CLKOUT
4412645
43
25 28
CC
V
GNDA
XTAL2I
26
L_AUX1
XTAL1O
27
R_AUX1
XTAL1I
404142
R_OUT
39
38
37
36
35
34
33
32
31
30
29
V
DD
GNDD
XCTL1
XCTL0
GNDD
V
DD
BM
L_AUX2
R_AUX2
L_OUT
N/C
SDI
GNDD
3
AD1847JP
Top View
(Not to Scale)
21 24
22182019
LFILT
GNDA
V
L_LINE2
SDFS
SDO
7
TSO
8
TSI
V
9
DD
GNDD
10
11
RESET
V
CC
GNDA
V
REFI
V
REF
R_LINE1
12
13
14
15
16
17
N/C = NO CONNECT
R_LINE2
RFILT
PWRDOWN
REV. B
–5–
AD1847
PIN DESCRIPTIONS
Parallel Interface
Pin Name PLCC TQFP I/O Description
SCLK 1 39 I/O Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output to the
serial bus when the Bus Master (BM) pin is driven HI and accepts the clock as an input
when the BM pin is driven LO. The serial clock output is fixed at 12.288 MHz when
XTAL1 is selected, and 11.2896 MHz when XTAL2 is selected. SCLK runs continuously. An AD1847 should always be configured as the serial bus master unless it is a slave
in a daisy-chained multiple codec system.
SDFS 6 44 I/O Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame synchroni-
zation signal as an output to the serial bus when the Bus Master (BM) pin is driven HI
and accepts the frame synchronization signal as an input when the BM pin is driven LO.
The SDFS frequency powers up at one half of the AD1847 sample rate (i.e., FRS bit = 0)
with two samples per frame and can be programmed to match the sample rate (i.e., FRS
bit = 1) with one sample per frame. An AD1847 should always be configured as the serial
bus master unless it is a slave in a daisy-chained multiple codec system.
SDI 4 42 I Serial Data Input. SDI is used by peripheral devices such as the host CPU or a DSP to
supply control and playback data information to the AD1847. All control and playback
transfers are 16 bits long, MSB first.
SDO 5 43 O Serial Data Output. SDO is used to supply status/index readback and capture data infor-
mation to peripheral devices such as the host CPU or a DSP. All status/index readback
and capture data transfers are 16 bits long, MSB first. Three-state output driver.
RESET 11 5 I Reset. The RESET signal is active LO. The assertion of this signal will initialize the
on-chip registers to their default values. See the “Control Register Definitions” section for
a description of the contents of the control registers after
PWRDOWN 12 6 I Powerdown. The PWRDOWN signal is active LO. The assertion of this signal will reset
the on-chip control registers (identically to the
AD1847 in a low power consumption mode. V
BM 33 27 I Bus Master. The assertion (HI) of this signal indicates that the AD1847 is the serial bus
master. The AD1847 will then supply the serial clock (SCLK) and the frame sync (SDFS)
signals for the serial bus. One and only one AD1847 should always be configured as the
serial bus master. If BM is connected to logic LO, the AD1847 is configured as a bus
slave, and will accept the SCLK and SDFS signals as inputs. An AD1847 should only be
configured as a serial bus slave when an AD1847 serial bus master already exists, in
daisy-chained multiple codec systems.
TSO 7 1 O Time Slot Output. This signal is asserted HI by the AD1847 coincidentally with the LSB
of the last time slot used by the AD1847. Used in daisy-chained multiple codec systems.
TSI 8 2 I Time Slot Input. The assertion of this signal indicates that the AD1847 should immedi-
ately use the next three time slots (TSSEL = 1) or the next six time slots (TSSEL = 0)
and then activate the TSO pin to enable the next device down the TDM chain. TSI
should be driven LO when the AD1847 is the bus master or in single codec systems. Used
in daisy-chained multiple codec systems.
CLKOUT 44 38 O Clock Output. This signal is the buffered version of the crystal clock output and the fre-
quency is dependent on which crystal is selected. This pin can be three-stated by driving
the BM pin LO or by programming the CLKTS bit in the Pin Control Register. See the
“Control Registers” section for more details. The CLKOUT frequency is 12.288 MHz
when XTAL1 is selected and 16.9344 MHz when XTAL2 is selected.
RESET signal) and will also place the
REF
RESET is deasserted.
and all analog circuitry are disabled.
Analog Signals
Pin Name PLCC TQFP I/O Description
L_LINE1 23 17 I Left Line Input #1. Line level input for the #1 left channel.
R_LINE1 17 11 I Right Line Input #1. Line level input for the #1 right channel.
L_LINE2 22 16 I Left Line Input #2. Line level input for the #2 left channel.
R_LINE2 18 12 I Right Line Input #2. Line level input for the #2 right channel.
L_AUX1 26 20 I Left Auxiliary Input #1. Line level input for the AUX1 left channel.
R_AUX1 27 21 I Right Auxiliary Input #1. Line level input for the AUX1 right channel.
L_AUX2 32 26 I Left Auxiliary Input #2. Line level input for the AUX2 left channel.
R_AUX2 31 25 I Right Auxiliary Input #2. Line level input for the AUX2 right channel.
L_OUT 30 24 O Left Line Output. Line level output for the left channel.
R_OUT 28 22 O Right Line Output. Line level output for the right channel.
–6–
REV. B
AD1847
Miscellaneous
Pin Name PLCC TQFP I/O Description
XTAL1I 40 34 I 24.576 MHz Crystal #1 Input.
XTAL1O 41 35 O 24.576 MHz Crystal #1 Output.
XTAL2I 42 36 I 16.9344 MHz Crystal #2 Input.
XTAL2O 43 37 O 16.9344 MHz Crystal #2 Output.
XCTL1:O 37 & 36 31 & 30 O External Control. These TTL signals reflect the current status of register bits inside the
AD1847. They can be used for signaling or to control external logic.
V
REF
V
REFI
L_FILT 21 15 I Left Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
R_FILT 19 13 I Right Channel Filter Capacitor. This pin requires a 1.0 µF capacitor to analog ground
NC 29 23 No Connect. Do not connect.
Power Supplies
Pin Name PLCC TQFP I/O Description
16 10 O Voltage Reference. Nominal 2.25 volt reference available externally as a voltage datum
for dc-coupling and level-shifting. V
should not have any signal dependent load.
REF
15 9 I Voltage Reference Internal. Voltage reference filter point for external bypassing only.
for proper operation.
for proper operation.
V
CC
13 & 25 7 & 19 I Analog Supply Voltage (+5 V).
GNDA 14, 20, 24 8, 14, 18 I Analog Ground.
V
DD
2, 9, 34, 39 40, 3, 28, 33 I Digital Supply Voltage (+5 V).
GNDD 3, 10, 35, 38 41, 4, 29, 32 I Digital Ground.
(Continued from page 1)
The ∑∆ DACs are preceded by a digital interpolation filter. An
attenuator provides independent user volume control over each
DAC channel. Nyquist images are removed from the DACs’
analog stereo output by on-chip switched-capacitor and
continuous-time filters. Two stereo pairs of auxiliary line-level
inputs can also be mixed in the analog domain with the DAC
output.
The AD1847 serial data interface uses a Time Division Multiplex (TDM) scheme that is compatible with DSP serial ports
configured in Multi-Channel Mode with 32 16-bit time slots
(i.e., SPORT0 on the ADSP-2101, ADSP-2115, etc.).
Analog Mixing
AUX1 and AUX2 analog stereo signals can be mixed in the analog domain with the DAC output. Each channel of each auxiliary analog input can be independently gained/attenuated from
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. The
post-mixed DAC output is available on L_OUT and R_OUT
externally and as an input to the ADCs.
Even if the AD1847 is not playing back data from its DACs, the
analog mix function can still be active.
Analog-to-Digital Datapath
The ∑∆ ADCs incorporate a proprietary fourth-order modulator. A single pole of passive filtering is all that is required for
antialiasing the analog input because of the ADC’s high 64
AUDIO FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1847 and is
intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog Inputs
The AD1847 SoundPort Stereo Codec accepts stereo line-level
inputs. All inputs should be capacitively coupled (ac-coupled) to
the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC
output analog stereo signals are multiplexed to the internal programmable gain amplifier (PGA) stage.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
times oversampling ratio. The ADCs include digital decimation
filters that low-pass filter the input to 0.4 3 F
word rate or “sampling frequency.”) ADC input overrange conditions will cause status bits to be set that can be read.
Digital-to-Analog Datapath
The ∑∆ DACs contain a programmable attenuator and a lowpass digital interpolation filter. The anti-imaging interpolation
filter oversamples and digitally filters the higher frequency images. The attenuator allows independent control of each DAC
channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.
The DACs’ ∑∆ noise shapers also oversample and convert the
signal to a single-bit stream. The DAC outputs are then filtered
in the analog domain by a combination of switched-capacitor
and continuous-time filters. These filters remove the very high
frequency components of the DAC bitstream output. No external components are required.
both channel outputs.
. (“FS’’ is the
S
REV. B
–7–
AD1847
EXPANSION
DAC INPUT
MSB LSB
15 0
MSB
15 0
MSB
15 0
COMPRESSED
INPUT DATA
LSB
3/2 2/1
LSB
3/2 2/1
0 0 0 / 0 0
87
TRUNCATION
COMPRESSION
MSB LSB
15 0
MSB
LSB
15 0
MSB
LSB
15 0
3/2 2/1
ADC OUTPUT
0 0 0 0 0 0 0 0
87
Changes in DAC output attenuation take effect only on zero
crossings of the digital signal, thereby eliminating “zipper” noise
on playback. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of an input signal that changes sign. The time-out period
is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds
at an 8 kHz sampling rate. (Time-out [ms] ≈ 384/F
[kHz]).
S
Digital Mixing
Stereo digital output from the ADCs can be mixed digitally with
the input to the DACs. Digital output from the ADCs going out
of the serial data port is unaffected by the digital mix. Along the
digital mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both channels of the monitor data are attenuated by the same amount.
(Note that internally the AD1847 always works with 16-bit
PCM linear data, digital mixing included; format conversions
take place at the input and output.)
Sixty-four steps of –1.5 dB attenuation are supported to
–94.5 dB. The digital mix datapath can also be completely
muted, preventing any mixing of the digital input with the digital output. Note that the level of the mixed signal is also a function of the input PGA settings, since they affect the ADCs’
output.
The attenuated digital mix data is digitally summed with the
DAC input data prior to the DACs’ datapath attenuators. The
digital sum of digital mix data and DAC input data is clipped at
plus or minus full scale and does not wrap around. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs’ datapath
attenuators.
Analog Outputs
A stereo line-level output is available at external pins. Other
output types such as headphone and speaker must be implemented in external circuitry. The stereo line-level outputs
should be capacitively coupled (ac-coupled) to the external circuitry. Each channel of this output can be independently
muted. When muted, the outputs will settle to a dc value near
V
, the midscale reference voltage.
REF
Digital Data Types
The AD1847 supports four global data types: 16-bit twoscomplement linear PCM, 8-bit unsigned linear PCM,
companded µ-law, and 8-bit companded A-law, as specified by
control register bits. Eight-bit data is always left-justified in 16bit fields; in other words, the MSBs of all data types are always
aligned; in yet other words, full-scale representations in all four
formats correspond to equivalent full-scale signals. The eight
least significant bit positions of 8-bit data in 16-bit fields are ignored on digital input and zoned on digital output (i.e., truncated).
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded µ-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was
specified in the Codec’s internal registers. Note that when µ-law
compressed data is expanded to a linear format, it requires 14
bits. A-law data expanded requires 13 bits.
Figure 2. A-Law or µ-Law Expansion
When 8-bit companding is specified, the ADCs’ linear output is
compressed to the format specified.
Figure 3. A-Law or µ-Law Compression
Note that all format conversions take place at input or output.
Internally, the AD1847 always uses 16-bit linear PCM representations to maintain maximum precision.
Power Supplies and Voltage Reference
The AD1847 operates from +5 V power supplies. Independent
analog and digital supplies are recommended for optimal performance though excellent results can be obtained in single-supply
systems. A voltage reference is included on the Codec and its
2.25 V buffered output is available on an external pin (V
REF
).
The reference output can be used for biasing op amps used in
dc coupling. The internal reference must be externally bypassed
to analog ground at the V
pin, and must not be used to bias
REFI
external circuitry.
Clocks and Sample Rates
The AD1847 operates from two external crystals, XTAL1 and
XTAL2. The two crystal inputs are provided to generate a wide
range of sample rates. The oscillators for these crystals are on
the AD1847, as is a multiplexer for selecting between them.
They can be overdriven with external clocks by the user, if so
desired. At a minimum, XTAL1 must be provided since it is selected as the reset default. If XTAL2 is not used, the XTAL2
input pin should be connected to ground. The recommended
crystal frequencies are 16.9344 MHz and 24.576 MHz. From
them, the following sample rates can be selected: 5.5125, 6.615,
8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8,
44.1, 48 kHz.
–8–
REV. B
AD1847
CONTROL REGISTERS
Control Register Mapping
The AD1847 has six 16-bit and thirteen 8-bit on-chip useraccessible control registers. Control information is sent to the
AD1847 in the 16-bit Control Word. Status information is sent
from the AD1847 in the 16-bit Status Word. Playback Data and
Capture Data each have two 16-bit registers for the right and
left channels. Additional 8-bit Index Registers are accessed via
indirect addressing in the AD1847 Control Word. [Index Registers are reached with indirect addressing.] The contents of an
indirect addressed Index Register may be readback by the host
CPU or DSP (during the Status Word/Index Readback time
slot) by setting the Read Request (RREQ) bit in the Control
Word. Note that each 16-bit register is assigned its own time
slot, so that the AD1847 always consumes six 16-bit time slots.
Figure 4 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL = 0.
TSSEL = 0 is used when the SDI and SDO pins are tied together (i.e., “1-wire” system). This configuration is efficient in
terms of component interconnect (one bidirectional wire for serial data input and output), but inefficient in terms of time slot
usage (six slots consumed on single bidirectional Time Division
Multiplexed [TDM] serial bus). When TSSEL = 0, serial data
input to the AD1847 occurs sequentially with serial data output
from the AD1847 (i.e., Control Word, Left Playback and Right
Playback data is received on the SDI pin, then the Status Word/
lndex Readback, Left Capture and Right Capture data is transmitted on the SDO pin).
Slot Register Name (16-Bit)
0 Control Word Input
1 Left Playback Data Input
2 Right Playback Data Input
3 Status Word/Index Readback Output
4 Left Capture Data Output
5 Right Capture Data Output
Figure 4. Control Register Mapping with TSSEL = 0
Figure 5 shows the mapping of the Control Word, Status Word/
Index Readback and Data registers to time slots when TSSEL =
1. Note that the six 16-bit registers “share” three time slots.
TSSEL = 1 is used when the SDI and SDO pins are independent inputs and output (i.e., “2-wire” system). This configuration is inefficient in terms of component interconnect (two
unidirectional wires for serial data input and output), but efficient in terms of time slot usage (three slots consumed on each
of two unidirectional TDM serial buses). When TSSEL = 1, serial data input to the AD1847 occurs concurrently with serial
data output from the AD1847 (i.e., Control Word reception on
the SDI pin occurs simultaneously with Status Word/lndex
Readback transmission on the SDO pin).
Slot Register Name (16-Bit)
0 Control Word Input
1 Left Playback Data Input
2 Right Playback Data Input
0 Status Word/Index Readback Output
1 Left Capture Data Output
2 Right Capture Data Output
Figure 5. Control Register Mapping with TSSEL = 1
An Index Register readback request to an invalid index address
(11, 14 and 15) will return the contents of the Status Word. Attempts to write to an invalid index address (11, 14 and 15) will
have no effect on the AD1847. As mentioned above, the RREQ
bit of the Control Word is used to request Status Word output
or Index Register readback output during either time slot 3
(TSSEL = 0) or time slot 0 (TSSEL = 1). RREQ is set for Index Register readback output, and reset for Status Word output.
When Index Register readback is requested, the Index Readback
bit format is the same as the Control Word bit format. All status
bits are updated by the AD1847 before a new Control Word is
received (i.e., at frame boundaries). Thus, if TSSEL = 0 and
the Control Word written at slot 0 causes some status bits to
change, the change will show up in the Status Word transmitted
at slot 3 of the same sample.
REV. B
–9–
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