Analog Devices AD1833 a Datasheet

Multichannel,

24-Bit, 192 kHz, - DAC

AD1833

FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital

Interface

Supports 96 kHz Sample Rates on 6 Channels and

192 kHz on 2 Channels

Supports 16-/20-/24-Bit Word Lengths
Multibit - Modulators with

Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor

Data Directed Scrambling DACs—Least Sensitive to

Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range: 110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control per Channel with 1024-Step

Linear Scale
Software Controllable Clickless Mute
Digital De-emphasis Processing
Supports 256  f

, 512  fS, and 768  fS Master

S

Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified,

Left-Justified, I

2

S Compatible, and DSP Serial Port Modes
Supports Packed Data Mode and TDM Mode
48-Lead LQFP Plastic Package

APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Set-Top Boxes
Digital Audio Effects Processors

GENERAL DESCRIPTION

The AD1833 is a complete, high performance, single-chip, multi­channel, digital audio playback system. It features six audio
playback channels, each comprising a high performance digital
interpolation filter, a multibit S-D modulator featuring Analog
Devices’ patented technology, and a continuous-time voltage-out
analog DAC section. Other features include an on-chip clickless
attenuator and mute capability for each channel, programmed
through an SPI compatible serial control port.

FUNCTIONAL BLOCK DIAGRAM

CDATA

CLATCH

CCLK

MCLK

RESET

L/RCLK

BCLK

SDIN1

SDIN2

SDIN3

SOUT

DV

DD1

SPI

PORT

DATA
PORT

DGND

DV

DD2

FILTER

ENGINE

AD1833

ZERO FLAGS

INTERPOLATOR

INTERPOLATOR

INTERPOLATOR

INTERPOLATOR

INTERPOLATOR

INTERPOLATOR

FILTR FILTD

AV

AGND

DD

DAC

DAC

DAC

DAC

DAC

DAC

OUTLP1
OUTLN1

OUTLP2
OUTLN2

OUTLP3
OUTLN3

OUTRP3
OUTRN3

OUTRP2
OUTRN2

OUTRP1
OUTRN1

The AD1833 is fully compatible with all known DVD formats,
accommodating word lengths of up to 24 bits at sample rates of
48 kHz and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the Redbook stan­dard 50 ms/15 ms digital de-emphasis filters at sample rates of
32 kHz, 44.1 kHz, and 48 kHz.

The AD1833 has a very flexible serial data input port that
allows glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. It can be con­figured in right-justified, left-justified, I

2

S, or DSP serial port
compatible modes. The AD1833 accepts serial audio data in MSB
first, twos complement format. The AD1833 can be operated
from a single 5 V power supply; it also features a separate supply
pin for its digital interface that allows it to be interfaced to devices
using 3.3 V power supplies.

The AD1833 is fabricated on a single monolithic integrated
circuit and is housed in a 48-lead LQFP package for operation
from –40∞C to +85∞C.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD1833–SPECIFICATIONS

TEST CONDITIONS, UNLESS OTHERWISE NOTED *

Supply Voltages (AVDD, DV
Ambient Temperature 25∞C
Input Clock 12.288 MHz, (8 Mode)
Input Signal Nominally 1 kHz, 0 dBFS

Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 20 kHz
Word Width 24 Bits
Load Capacitance 100 pF
Load Impedance 10 kW

*Performance is identical for all channels (except for the Interchannel Gain

Mismatch and Interchannel Phase Deviation specifications).

Parameter Min Typ Max Unit Test Conditions

ANALOG PERFORMANCE
DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)

with A-Weighted Filter
AD1833A 106.5 110.0 dB
AD1833A 110.5 dB f
AD1833C 107.0 dB

Total Harmonic Distortion + Noise –95 –89 dB Two channels active

SNR 110 dB
Interchannel Isolation 108 dB
DC Accuracy

Gain Error ± 3%
Interchannel Gain Mismatch 0.2 %

Gain Drift 80 ppm/∞C
Interchannel Crosstalk (EIAJ Method) –120 dB
Interchannel Phase Deviation ± 0.1 Degrees
Volume Control Step Size (1023 Linear Steps) 0.098 %
Volume Control Range (Max Attenuation) +63.5 (0.098) dB (%)
Mute Attenuation –63.5 (0.098) dB (%)
De-emphasis Gain Error ± 0.1 dB
Full-Scale Output Voltage at Each Pin (Single-Ended) 1 (2.8) V rms (V p-p)
Output Resistance Measured Differentially 150 W
Common-Mode Output Volts 2.2 V

DAC INTERPOLATION FILTER—8⫻ Mode (48 kHz)

Pass Band 21.768 kHz
Pass-Band Ripple ± 0.01 dB
Stop Band 24 kHz
Stop-Band Attenuation 70 dB
Group Delay 510 ms

DAC INTERPOLATION FILTER—4⫻ Mode (96 kHz)

Pass Band 37.7 kHz
Pass-Band Ripple ± 0.03 dB
Stop Band 55.034 kHz
Stop-Band Attenuation 70 dB
Group Delay 160 ms

DAC INTERPOLATION FILTER—2⫻ Mode (192 kHz)

Pass Band 89.954 kHz
Pass-Band Ripple ± 1dB
Stop Band 104.85 kHz
Stop-Band Attenuation 70 dB
Group Delay 140 ms

)5 V

DDX

(Full-Scale)

= 96 kHz

S

–94 dB Six channels active
–95 dB 96 kHz, two channels active
–94 dB 96 kHz, six channels active

–2–

REV. A

AD1833

Parameter Min Typ Max Unit Test Conditions

DIGITAL I/O

Input Voltage HI 3.0 V
Input Voltage LO 0.8 V
Output Voltage HI DV
Output Voltage LO 0.4 V

POWER SUPPLIES

Supply Voltage (AV
Supply Voltage (DV
Supply Current I
Supply Current I

ANALOG

DIGITAL

and DV

DD

) 3.3 DV

DD2

) 4.5 5 5.5 V

DD1

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins –60 dB
20 kHz 300 mV p-p Signal at Analog Supply Pins –50 dB

Specifications subject to change without notice.

– 0.4 V

DD2

38.5 42 mA
42 48 mA Active
2mAPower-Down

DD1

V

DIGITAL TIMING

(Guaranteed over –40C to +85C, AVDD = DVDD = 5 V  10%)

Parameter Min Max Unit Comments

MASTER CLOCK AND RESET

t
t
t

ML

MH

PDR

MCLK LO (All Modes)* 15 ns 24 MHz clock, clock doubler bypassed
MCLK HI (All Modes)* 15 ns 24 MHz clock, clock doubler bypassed
PD/RST LO 20 ns

SPI PORT

t

CCH

t

CCL

t

CCP

t

CDS

t

CDH

t

CLS

t

CLH

CCLK HI Pulsewidth 20 ns
CCLK LO Pulsewidth 20 ns
CCLK Period 80 ns
CDATA Setup Time 10 ns To CCLK rising
CDATA Hold Time 10 ns From CCLK rising
CLATCH Setup 10 ns To CCLK rising
CLATCH Hold 10 ns From CCLK rising

DAC SERIAL PORT

t

DBH

t

DBL

t

DLS

t

DLH

t

DDS

t

DDH

BCLK HI 15 ns
BCLK LO 15 ns
L/RCLK Setup 10 ns To BCLK rising
L/RCLK Hold 10 ns From BCLK rising
SDATA Setup 10 ns To BCLK rising
SDATA Hold 15 ns From BCLK rising

TDM MODE MASTER

t

TMBD

t

TMFSD

t

TMDDS

t

TMDDH

BCLKTDM Delay 20 ns From MCLK rising
FSTDM Delay 10 ns From BCLKTDM rising
SDIN1 Setup 15 ns To BCLKTDM falling
SDIN1 Hold 15 ns From BCLKTDM falling

AUXILIARY INTERFACE

t

AXLRD

t

AXDD

t

AXBD

*MCLK symmetry must be better than 60:40 or 40:60.

Specifications subject to change without notice.

L/RCLK Delay 10 ns From BCLK falling
Data Delay 10 ns From BCLK falling
AUXBCLK Delay 20 ns From MCLK rising

REV. A

–3–

AD1833

MCLK

PD/RST

t

MH

t

ML

t

PDR

Figure 1. MCLK and

RESET

Timing

CLATCH

CCLK

CIN

BCLK

L/RCLK

SDATA

LEFT-JUSTIFIED

MODE

SDATA

2

I

S MODE

SDATA

RIGH T-JUSTIFIED

MODE

t

CLS

t

D15 D14

t

DBH

CCP

t

t

t

DDS

DBL

DLS

MSB

t

t

CCHtCCL

D9

t

t

CDH

CDS

D8

CLH

D0

Figure 2. SPI Port Timing

t

DLH

MSB-1

t

DDH

t

DDS

MSB

t

DDH

t

DDS

MSB

t

DDH

t

DDS

LSB

t

DDH

Figure 3. Serial Port Timing

MCLK

BCLKTDM

FSTDM

SDIN1

t

TMBD

t

TMFSD

t

TMDDS

MSB

t

TMDDH

Figure 4. TDM Master Mode Timing

–4–

REV. A

MCLK

AUX BCLK

AUX L/ RCLK

AUX DATA

t

AXBD

t

AXLRD

t

AXDD

Figure 5. Auxiliary Interface Timing

AD1833

MSB

ABSOLUTE MAXIMUM RATINGS*

(TA = 25∞C, unless otherwise noted.)

AVDD, DV

to AGND, DGND . . . . . . . . –0.3 V to +6.5 V

DDX

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DV

Analog I/O Voltage to AGND . . . . . . –0.3 V to AV

+ 0.3 V

DD2

+ 0.3 V

DD

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

LQFP, q
Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

Thermal Impedance . . . . . . . . . . . . . . . . . 91∞C/W

JA

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150∞C

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD1833AST –40∞C to +85∞CLow Profile Quad Flat Package ST-48
AD1833AST-REEL –40∞C to +85∞CLow Profile Quad Flat Package ST-48
AD1833CST –40∞C to +85∞CLow Profile Quad Flat Package ST-48
AD1833CST-REEL –40∞C to +85∞CLow Profile Quad Flat Package ST-48
EVAL-AD1833EB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although the AD1833

features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to

high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid

performance degradation or loss of functionality.

REV. A

–5–

AD1833

PIN CONFIGURATION

OUTLN2

OUTLP2

OUTLN3

OUTLP3

AVDDFILTD

FILTR

AGND

OUTRP3

OUTRN3

OUTRP2

SDIN2

SDIN3

OUTRN2

SOUT

36

35

34

33

32

31

30

29

28

27

26

25

ZERO2L

OUTRP1

OUTRN1

AV

DD

AV

DD

AGND

AGND

AGND

DGND

DV

DD2

RESET

ZERO1L

ZERO1R

48 4 7 46 4 5 44 39 38 3743 42 41 40

1

OUTLP1

OUTLN1

AV

AV

AGND

AGND

AGND

DGND

DV

DD1

ZEROA

ZERO3R

ZERO3L

DD

DD

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

ZERO2R

CDATA

CLATCH

AD1833

TOP VIEW

(Not to Scale)

CCLK

BCLK

MCLK

L/RCLK

SDIN1

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic IN/OUT Description

1 OUTLP1 O DAC 1 Left Channel Positive Output.
2 OUTLN1 O DAC 1 Left Channel Negative Output.
3, 4, 33, 34, 44 AV

DD

Analog Supply.
5, 6, 7, 30, 31, 32, 41 AGND Analog Ground.
8, 29 DGND Digital Ground.
9DV

DD1

Digital Supply to Core Logic.
10 ZEROA O Flag to Indicate Zero Input on All Channels.
11 ZERO3R O Flag to Indicate Zero Input on Channel 3 Right.
12 ZERO3L O Flag to Indicate Zero Input on Channel 3 Left.
13 ZERO2R O Flag to Indicate Zero Input on Channel 2 Right.
14 CLATCH I Latch Input for Control Data (SPI Port).
15 CDATA I Serial Control Data Input (SPI Port).
16 CCLK I Clock Input for Control Data (SPI Port).
17 L/RCLK I/O Left/Right Clock for DAC Data Input; FSTDM Output in TDM Master Mode.
18 BCLK I/O Bit Clock for DAC Data Input; BCLKTDM Output in TDM Master Mode.
19 MCLK I Master Clock Input.
20 SDIN1I Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes).
21 SDIN2 I/O Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in

TDM Mode).
22 SDIN3 I/O Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode).
23 SOUT O Auxiliary I

2

S Output (Available in TDM Mode).
24 ZERO2L O Flag to Indicate Zero Input on Channel 2 Left.
25 ZERO1R O Flag to Indicate Zero Input on Channel 1 Right.
26 ZERO1L O Flag to Indicate Zero Input on Channel 1 Left.
27 RESET IPower-Down and Reset Control.
28 DV

DD2

Power Supply to Output Interface Logic.
35 OUTRN1 O DAC 1 Right Channel Negative Output.
36 OUTRP1 O DAC 1 Right Channel Positive Output.
37 OUTRN2 O DAC 2 Right Channel Negative Output.
38 OUTRP2 O DAC 2 Right Channel Positive Output.
39 OUTRN3 O DAC 3 Right Channel Negative Output.

–6–

REV. A