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of their respective companies.
The AMD Geode™ SC1200 and SC1201 processors are
members of the AMD Geode processor family of fully integrated x86 system chips. The SC1200/SC1201 processor
includes:
• The Geode GX1 processor module combines advanced
CPU performance with MMX™ support, fully accelerated 2D graphics, a 64-bit synchronous DRAM
(SDRAM) interface, a PCI bus controller, and a display
controller.
• The Core Logic module includes: PC/AT functionality, a
USB interface, an IDE interface, a PCI bus interface, an
LPC bus interface, Advanced Configuration Power Interface (ACPI) version 1.0 compliant power management,
and an audio codec interface.
• The SuperI/O module has: three serial ports (UART1,
UART2, and UART3 with fast infrared), a parallel port,
two ACCESS.bus (ACB) interfaces, and a real-time
clock (RTC).
1
• A low-power CRT and TFT Video Processor module with
a hardware video accelerator for scaling, filtering, and
color space conversion, a Video Input Port (VIP), and an
NTSC/PAL TV encoder. The SC1201 (only) processor
has Macrovision copy protection support (see "Macrovision Product Notice" on page 441).
GX1
Memory Controller
Display
CPU
Core
IDE I/F
USB
PCI/Sub-ISA
Bus I/F
GPIO
Audio Codec I/F
LPC I/F
2D Graphics
Accelerator
PCI Bus
Controller
Controller
Fast-PCI Bus
Bridge
PCI Bus
X-Bus
Config.
Block
Fast X-Bus
Core Logic
PIT
PIC
DMAC
Pwr Mgmnt
Configuration
ISA Bus I/F
These features, combined with the device’s low power consumption, enable a small form factor design making it ideal
as the core for a set-top box or an advanced multimediatype device.
Figure 1-1 shows the relationships between the modules.
Video Processor
CRT I/F
Video
Scaling
Video Input Port (VIP)
Host Interface
SuperI/O
ISA Bus
RTC
I/F
Video
Mixer
Clock & Reset Logic
TFT I/F
TV I/F
Parallel
Por t
ACB1
I/F
ACB2
I/F
UART1
UART2
UART3
& IR
VOP
Figure 1-1. Block Diagram
AMD Geode™ SC1200/SC1201 Processor Data Book 13
1.2Features
32579B
Overview
General Features
■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc-
tion set support
■ Memory controller with 64-bit SDRAM interface
■ 2D graphics accelerator
■ CRT controller with hardware video accelerator
■ CCIR-656 video input port with direct video for full
screen display
■ PC/AT functionality
■ PCI bus controller
■ IDE interface, two channels
■ USB, three ports, OHCI (OpenHost Controller Interface)
version 1.0 compliant
■ Audio, AC97/AMC97 version 2.0 compliant
■ Virtual System Architecture™ technology (VSA) support
■ Power management, ACPI (Advanced Configuration
Power Interface) version 1.0 compliant
■ Package:
— BGU481 (481-Terminal Ball Grid Array Cavity Up)
GX1 Processor Module
■ CPU Core:
— 32-Bit x86, 266 MHz, with MMX compatible instruc-
tion set support
— 16 KB unified L1 cache
— Integrated FPU (Floating Point Unit)
— Re-entrant SMM (System Management Mode)
enhanced for VSA
■ 2D Graphics Accelerator:
— Accelerates BitBLTs, line draw and text
— Supports all 256 raster operations
— Supports transparent BLTs
— Runs at core clock frequency
■ Memory Controller:
— 64-Bit SDRAM interface
— 66 to 100 MHz frequency range
— Direct interface with CPU/cache, display controller
and 2D graphic accelerator
— Supports clock suspend and power-down/
self-refresh
— Up to two banks of SDRAM (8 devices total) or one
SODIMM
■ Display Controller:
— Hardware graphics frame buffer compress/
decompress
— Hardware cursor, 32x32 pixels
Video Processor Module
■ Video Accelerator:
— Flexible video scaling support of up to 8x (horizon-
tally and vertically)
— Bilinear interpolation filters (with two taps, and eight
phases) to smooth output video
■ Video/Graphics Mixer:
— 8-Bit value alpha blending
— Three blending windows with constant alpha value
— Color key
■ Video Input Port (VIP):
— Video capture or display
— CCIR-656 and VESA Video Interface Port v1.1
compliant
— Lock display timing to video input timing (GenLock)
— Able to transfer video data into main memory
— Direct video transfer for full screen display
— Separate memory location for VBI
■ Video Output Port (VOP):
— VESA Video Interface Port Rev. 1.1 Task B format
■ CRT Interface:
— Uses three 8-bit DACs
— Support up to 135 MHz
— 1280x1024 non-interlaced CRT @ 8 bpp, up to 75 Hz
— 1024x768 non-interlaced CRT @ 16 bpp, up to 85 Hz
■ TFT Interface:
— Direct connection to TFT panels
— 800x600 non-interlaced TFT @ 16 bpp graphics, up
to 85 Hz
— 1024x768 non-interlaced TFT @ 16 bpp graphics, up
to 75 Hz
— TFT on IDE: FPCLK max is 40 MHz
— TFT on Parallel Port: FPCLK max is 80 MHz
■ TV Interface:
— Uses four 10-bit DACs
— 720x480 NTSC @ 60 Hz or 720x576 PAL @ 50 Hz
— NTSC-M, PAL-M/B/D/G/H/I
— Luminance filtering with 2x oversampling and sinx/x
correction
— Chrominance filtering with 4x oversampling
— Flicker filter with a three-line buffer for graphics
display on TV
— Composite, S-Video and YCrCb component video
outputs
— Analog video output interface supports SCART stan-
dard (both RGBCvbs and YCCvbs)
— Support for VBI (Vertical Blanking Interval) transfer
— ACPI v1.0 compliant
— Sx state control of three power planes
— Cx/Sx state control of clocks and PLLs
— Thermal event input
— Wakeup event support:
– Three general-purpose events
– AC97 codec event
– UART2 RI# signal
– Infrared (IR) event
■ General Purpose I/Os (GPIOs):
— 27 multiplexed GPIO signals
■ Low Pin Count (LPC) Bus Interface:
— Specification v1.0 compatible
■ PCI Bus Interface:
— PCI v2.1 compliant with wakeup capability
— 32-Bit data path, up to 33 MHz
— Glueless interface for an external PCI device
— Fixed priority
— 3.3V signal support only
■ Sub-ISA Bus Interface:
— Up to 16 MB addressing
— Supports a chip select for ROM or Flash EPROM
boot device
— Supports either:
– M-Systems DiskOnChip DOC2000 Flash file
system
– NAND EEPROM
— Supports up to two chip selects for external I/O
devices
— 8-Bit (optional 16-bit) data bus width
— Shares balls with PCI signals
— Is not a subtractive agent
■ IDE Interface:
— Two IDE channels for up to four external IDE devices
— Supports ATA-33 synchronous DMA mode transfers,
up to 33 MB/s
■ Universal Serial Bus (USB):
— USB OpenHCI 1.0 compliant
— Three ports
SuperI/O Module
■ Real-Time Clock (RTC):
— DS1287, MC146818 and PC87911 compatible
— Multi-century calendar
As illustrated in Figure 1-1 on page 13, the SC1200/
SC1201 processor contains the following modules in one
integrated device:
• GX1 Module:
— Combines advanced CPU performance with MMX
support, fully accelerated 2D graphics, a 64-bit
synchronous DRAM (SDRAM) interface and a PCI
bus controller. Integrates GX1 silicon revision 8.1.1.
• Video Processor Module:
— A low-power CRT and TFT support module with a
hardware video accelerator for scaling, filtering and
color space conversion, and a video input port (VIP).
Includes an NTSC/PAL TV encoder.
• Core Logic Module:
— Includes PC/AT functionality, an IDE interface, a
Universal Serial Bus (USB) interface, ACPI 1.0
compliant power management, and an audio codec
interface.
• SuperI/O Module:
— Includes two Serial Ports, an Infrared (IR) Port, a
Parallel Port, two ACCESS.bus interfaces, and a
Real-Time Clock (RTC).
2.1GX1 Module
The GX1 processor (silicon revision 8.1.1) is the central
module of the SC1200/SC1201 processor. For detailed
information regarding the GX1 module, refer to the AMD
Geode™ GX1 Processor Data Book and the AMD
Geode™ GX1 Processor Silicon Revision 8.1.1 Specification Update documents.
The SC1200/SC1201 processor’s device ID is contained in
the GX1 module. Software can detect the revision by reading the DIR0 and DIR1 Configuration registers (see Configuration registers in the AMD Geode™ GX1 Processor Data
Book). The AMD Geode™ SC1200/SC1201 Processor
Specification Update document contains the specific val-
ues.
2.1.1Memory Controller
The GX1 module is connected to external SDRAM devices.
For more information see Section 3.4.2 "Memory Interface
Signals" on page 50, and the “Memory Controller” chapter
in the AMD Geode™ GX1 Processor Data Book.
There are some differences in the SC1200/SC1201 processor’s memory controller and the stand-alone GX1 processor’s memory controller:
1)There is drive strength/slew control in the SC1200/
SC1201 that is not in the GX1. The bits that control
this function are in the MC_MEM_CNTRL1 and
MC_MEM_CNTRL2 registers. In the GX1 processor,
these bits are marked as reserved.
2)The SC1200/SC1201 supports two banks of memory.
The GX1 supports four banks of memory. In addition,
the SC1200/SC1201 supports a maximum of eight
devices and the GX1 supports up to 32 devices. With
this difference, the MC_BANK_CFG register is different.
Table 2-1 on page 18 summarizes the 32-bit registers contained in the SC1200/SC1201 processor’s memory controller. Table 2-2 on page 18 gives detailed register/bit formats.
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,
this field must be written as 00.
52CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.
0: Disable.
1: Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
4RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes.
3XBUSARB (X-Bus Round Robin). When round robin is enabled, processor, graphics pipeline, and low priority display con-
troller requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority
level. High priority display controller requests always have the highest arbitration priority.
0: Disable.
1: Enable round robin.
2SMM_MAP (SMM Region Mapping). Maps the SMM memory region at GX_BASE+400000 to physical address A0000 to
BFFFF in SDRAM.
0: Disable.
1: Enable.
1RSVD (Reserved). Write as 0.
0SDRAMPRG (Program SDRAM). When this bit is set, the memory controller will program the SDRAM MRS register using
LTMODE in MC_SYNC_TIM1.
This bit must transition from zero (written to zero) to one (written to one) in order to program the SDRAM devices.
30:28LTMODE (CAS Latency). CAS latency is the delay, in SDRAM clock cycles, between the registration of a read command
27:24RC (RFSH to RFSH/ACT Command Period, tRC). Minimum number of SDRAM clock between RFSH and RFSH/ACT
23:20RAS (ACT to PRE Command Period, tRAS). Minimum number of SDRAM clocks between ACT and PRE commands:
18:16RP (PRE to ACT Command Period, tRP). Minimum number of SDRAM clocks between PRE and ACT commands:
14:12RCD (Delay Time ACT to READ/WRT Command, tRCD). Minimum number of SDRAM clock between ACT and READ/
and the availability of the first piece of output data. This parameter significantly affects system performance. Optimal setting
should be used. If an SODIMM is used, BIOS can interrogate EEPROM across the ACCESS.bus interface to determine this
value:
10:8RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command
to two different component banks within the same module bank. The memory controller does not perform back-to-back Activate commands to two different component banks without a READ or WRITE command between them. Hence, this field
should be written as 001.
7RSVD (Reserved). Write as 0.
6:4DPL (Data-in to PRE Command Period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is
3:0RSVD (Reserved). Leave unchanged. Always returns a 101h.
Note:Refer to the SDRAM manufacturer’s specification for more information on component banks.
0: TEST[3:0] are driven low (normal operation).
1: TEST[3:0] pins are used to output test information
16TECTL (Test Enable Shared Control Pins).
0: RASB#, CASB#, CKEB, WEB# (normal operation).
1: RASB#, CASB#, CKEB, WEB# are used to output test information
11RSVD (Reserved). Write as 0.
KB boundaries. This field corresponds to address bits [29:19].
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.
register. This field does not auto increment.
1D (Dirty Bit). This bit is read/write accessible.
0V (Valid Bit). This bit is read/write accessible.
AMD Geode™ SC1200/SC1201 Processor Data Book21
32579B
Architecture Overview
2.1.2Fast-PCI Bus
The GX1 module communicates with the Core Logic module via a Fast-PCI bus that can work at up to 66 MHz. The
Fast-PCI bus is internal for the SC1200/SC1201 processor
and is connected to the General Configuration Block (see
Section 4.0 on page 71 for details on the General Configuration Block).
This bus supports seven bus masters. The requests
(REQs) are fixed in priority. The seven bus masters in order
of priority are:
1)VIP
2)IDE Channel 0
3)IDE Channel 1
4)Audio
5)USB
6)External REQ0#
7)External REQ1#
2.1.3Display
The GX1 module generates display timing, and controls
internal signals CRT_VSYNC and CRT_HSYNC of the
Video Processor module.
The GX1 module interfaces with the Video Processor via a
video data bus and a graphics data bus.
• Video data. The GX1 module uses the core clock,
divided by 2 or 4 (typically 100 to 133 MHz). It drives the
video data using this clock. Internal signals VID_VAL
and VID_RDY are used as data-flow handshake signals
between the GX1 module and the Video Processor.
• Graphics data. The GX1 module uses the internal
DCLK signal, supplied by the PLL of the Video
Processor, to drive the 18-bit graphics-data bus of the
Video Processor. Each six bits of this bus define a
different color. Each of these 6-bit color definitions is
expanded (by adding two zero LSB lines) to form an
8-bit bus, at the Video Processor.
For more information about the GX1 module’s interface to
the Video Processor, see the “Display Controller” chapter
in the AMD Geode™ GX1 Processor Data Book.
2.2.1GX1 Module Interface
The Video Processor is connected to the GX1 module in
the following way:
• The Video Processor’s DOTCLK output signal is used as
the GX1 module’s DCLK input signal.
• The GX1 module’s PCLK output signal is used as the
GFXCLK input signal of the Video Processor.
2.2.2Video Input Port
The Video Input Port (VIP) within the Video Processor contains a standard interface that is typically connected to a
media processor or TV encoder. The clock is supplied by
the externally connected device; typically at 27 MHz.
Video input can be sent to the GX1 module’s video frame
buffer (Capture Video mode) or can be used directly (Direct
Video mode).
2.2.3Core Logic Module Interface
The Video Processor interfaces to the Core Logic module
for accessing PCI function configuration registers.
2.2.4CRT DAC
The Video Processor drives three CRT DACs with up to
135M pixels per second.
The interface for these DACs can be monitored via external
balls of the SC1200/SC1201 processor. For more information, see Section 3.4.4 "CRT/TFT Interface Signals" on
page 52.
2.3Core Logic Module
The Core Logic module is described in detail in Section 6.0
on page 141.
The Core Logic module is connected to the Fast-PCI bus. It
uses signal AD28 as the IDSEL for all PCI configuration
functions except for USB which uses AD29.
2.3.1Other Core Logic Module Interfaces
The following interfaces of the Core Logic module are
implemented via external signals of the SC1200/SC1201
processor. Each interface is listed below with a reference to
the descriptions of the relevant signals.
2.2Video Processor Module
The Video Processor provides high resolution and graphics
for a CRT, TV, or TFT/DSTN interface. The following subsections provide a summary of how the Video Processor
interfaces with the other modules of the SC1200/SC1201
processor. For detailed information about the Video Processor, see Section 7.0 on page 311.
22AMD Geode™ SC1200/SC1201 Processor Data Book
• IDE: See Section 3.4.10 "IDE Interface Signals" on page
61.
• AC97: See Section 3.4.15 "AC97 Audio Interface
Signals" on page 65.
• PCI: See Section 3.4.7 "PCI Bus Interface Signals" on
page 55.
Architecture Overview
32579B
• USB: See Section 6.2.4 "Universal Serial Bus" on page
147. The USB function uses signal AD29 as the IDSEL
for PCI configuration.
• LPC: See Section 3.4.9 "Low Pin Count (LPC) Bus Interface Signals" on page 60.
• Sub-ISA: See Section 3.4.8 "Sub-ISA Interface Signals"
on page 59, Section 6.2.5 "Sub-ISA Bus Interface" on
page 147, and Section 4.2 "Pin Multiplexing, Interrupt
Selection, and Base Address Registers" on page 72
• GPIO: See Section 3.4.17 "GPIO Interface Signals" on
page 67.
More detailed information about each of these interfaces is
provided in Section 6.2 "Module Architecture" on page 142.
• Super/IO Block Interfaces: See Section 4.2 "Pin Multiplexing, Interrupt Selection, and Base Address Registers" on page 72, Section 3.4.6 "ACCESS.bus Interface
Signals" on page 55, Section 3.4.14 "Fast Infrared (IR)
Port Interface Signals" on page 64, and Section 3.4.13
"Parallel Port Interface Signals" on page 63.
The Core Logic module interface to the GX1 module consists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• PSERIAL is a one-way serial bus from the GX1 to the
Core Logic module used to communicate powermanagement states and VSYNC information for VGA
emulation.
• IRQ13 is an input from the processor indicating that a
floating point error was detected and that INTR should
be asserted.
• INTR is the level output from the integrated 8259A PICs
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
• SMI# is a level-sensitive interrupt to the GX1 that can be
configured to assert on a number of different system
events. After an SMI# assertion, SMM is entered and
program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
• SUSP# and SUSPA# are handshake signals for implementing CPU Clock Stop and clock throttling.
• CPU_RST resets the CPU and is asserted for approximately 100 µs after the negation of POR#.
• PCI bus interface signals.
2.4SuperI/O Module
The SuperI/O (SIO) module is a PC98 and ACPI compliant
SIO that offers a single-cell solution to the most commonly
used ISA peripherals.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
2.5Clock, Timers, and Reset Logic
In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the SC1200/
SC1201 processor, the following blocks of logic have also
been integrated:
• Clock Generators as described in Section 4.5 "Clock
Generators and PLLs" on page 83.
• Configuration Registers as described in Section 4.2 "Pin
Multiplexing, Interrupt Selection, and Base Address
Registers" on page 72.
• A WATCHDOG timer as described in Section 4.3
"WATCHDOG" on page 79.
• A High-Resolution timer as described in Section 4.4
"High-Resolution Timer" on page 81.
2.5.1Reset Logic
This section provides a description of the reset flow of the
SC1200/SC1201 processor.
2.5.1.1Power-On Reset
Power-on reset (POR) is triggered by assertion of the
POR# signal. Upon power-on reset, the following things
happen:
• Strap balls are sampled.
• PLL4, PLL5, and PLL6 are reset, disabling their output.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 4.5 "Clock
Generators and PLLs" on page 83.
• Certain WATCHDOG and High-Resolution Timer
register bits are cleared.
2.5.1.2System Reset
System reset causes signal PCIRST# to be issued, thus
triggering a reset of all PCI and LPC agents. A system
reset is triggered by any of the following events:
• Power-on, as indicated by POR# signal assertion.
• A WATCHDOG reset event (see Section 4.3.2
"WATCHDOG Registers" on page 80).
• Software initiated system reset.
AMD Geode™ SC1200/SC1201 Processor Data Book23
32579B
Architecture Overview
24AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions32579B
3.0Signal Definitions
3
This section defines the signals and describes the external
interface of the SC1200/SC1201 processor. Figure 2-1
shows the signals organized by their functional groups.
Where signals are multiplexed, the default signal name is
listed first and is separated by a plus sign (+). A slash (/) in
a signal name means that the function is always enabled
and available (i.e., cycle multiplexed).
The remaining subsections of this chapter describe:
• Section 3.1 "Ball Assignments": Provides a ball assignment diagram and tables listing the signals sorted
according to ball number and alphabetically by signal
name.
• Section 3.2 "Strap Options": Several balls are read at
power-up that set up the state of the SC1200/SC1201
processor. This section provides details regarding those
balls.
• Section 3.4 "Signal Descriptions": Detailed descriptions
of each signal according to functional group.
Signal Definitions
3.1Ball Assignments
The SC1200/SC1201 processor is highly configurable as
illustrated in Figure 3-1 on page 25. Strap options and register programming are used to set various modes of operation and specific signals on specific balls. This section
describes which signals are available on which balls and
provides configuration information:
• Figure 3-2 on page 28: Illustrates the BGU481 ball
assignments.
• Table 3-2 on page 29: Lists signals according to ball
number. Power Rail, Signal Type, Buffer Type and,
where relevant, Pull-Up or Pull-Down resistors are indicated for each ball in this table. For multiplexed balls, the
necessary configuration for each signal is listed as well.
• Table 3-3 on page 40: Quick reference signal list sorted
alphabetically - listing all signal names and ball
numbers.
The tables in this chapter use several common abbreviations. Table 3-1 lists the mnemonics and their meanings
Notes:
1)For each GPIO signal, there is an optional pull-up
resistor on the relevant ball. After system reset, the
pull-up is present.
This pull-up resistor can be disabled via registers in the
Core Logic module. The configuration is without regard to
the selected ball function (except for GPIO12, GPIO13,
and GPIO16). Alternate functions for GPIO12, GPIO13,
and GPIO16 control pull-up resistors.
For more information, see Section 6.4.1 "Bridge,
GPIO, and LPC Registers - Function 0" on page 190.
2)Configuration settings listed in this table are with
regard to the Pin Multiplexing Register (PMR). See
Section 4.2 "Pin Multiplexing, Interrupt Selection, and
Base Address Registers" on page 72 for a detailed
description of this register.
32579B
Table 3-1. Signal Definitions Legend
MnemonicDefinition
AAnalog
AV
SS
AV
CC
GCBGeneral Configuration Block registers.
IInput ball
I/OBidirectional ball
MCR[x]Miscellaneous Configuration Register
OOutput ball
ODOpen-drain
PDPull-down (KΩ)
PMR[x]Pin Multiplexing Register Bit x: A regis-
PUPull-up (KΩ)
TSTRI-STATE
V
CORE
V
IO
V
SS
#The # symbol in a signal name indicates
/A / in a signal name indicates both func-
+A + in signal name indicates the function
Ground ball: Analog
Power ball: Analog
Refer to Section 4.0 "General Configuration Block" on page 71.
Location of the General Configuration
Block cannot be determined by software.
See AMD Geode™ SC1200/SC1201
Processor Specification Update document.
Bit x: A register, located in the GCB.
Refer to Section 4.1 "Configuration
Block Addresses" on page 71 for further
details.
ter, located in the GCB, used to configure balls with multiple functions. Refer to
Section 4.1 "Configuration Block
Addresses" on page 71 for further
details.
Power ball: 1.2V
Power ball: 3.3V
Ground ball
that the active or asserted state occurs
when the signal is at a low voltage level.
Otherwise, the signal is asserted when
at a high voltage level.
tions are always enabled (i.e., cycle multiplexed).
is available on the ball, but that either
strapping options or register programming is required to select the desired
function.
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND Ball
= PWR Ball
S
= Strap Option Ball
= Multiplexed Ball
SS
IOVSS
SS
SDO SYNC ACCK
SSVIO
DQM7
IOVSS
MD28
A
SS
B
IO
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
IO
AL
SS
Figure 3-2. BGU481 Ball Assignment Diagram
28AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
1
Ball
No.Signal Name
A1V
A2V
SS
IO
I/O
(PU/PD)
Buffer
GND---------
PWR---------
A3AD30I/OIN
D6I/OIN
A4PCICLK0OO
FPCI_MONI
(PD
100
IN
)
A5REQ1#I
(PU
)
22.5
A6PCIRST#OO
A7PCICLKIIN
A8IOW#OO
DOCW#OO
GPIO15I/O
A9GPIO20I/O
(PU
(PU
22.5
22.5
)
IN
)
DOCCS#O
)
(PU
22.5
TFTD0O
(PU
22.5
)
A10GPIO17I/O
)
(PU
22.5
IOCS0#O
(PU
22.5
)
TFTDCKO
)
(PU
22.5
A11HSYNCOO
A12AV
A13V
CCCRT
SS
PWR---------
GND---------
A14GREENOWIREAV
A15BLUEOWIREAV
A16V
A17V
SS
PLL2
GND---------
PWR---------
Typ e
O
O
STRP
IN
IN
O
, O
T
O
O
IN
O
O
O
PCI
PCI
PCI
PCI
PCI
PCI
,
,
PCI
T
3/5
3/5
,
TS
3/5
3/5VIO
3/5
1/4
,
TS
3/5
3/5
1/4
1/4
Power
Rail Configuration
VIOCycle Multiplexed
VIO---
Strap (See Table 34 on page 44.)
VIO---
VIO---
VIO---
VIOPMR[21] = 0 and
PMR[2] = 0
PMR[21] = 0 and
PMR[2] = 1
PMR[21] = 1 and
PMR[2] = 1
(PMR[23]3 = 0 and
PMR[7] = 0) or
3
(PMR[23]
PMR[15] = 1 and
PMR[7] = 0)
= 1 and
(PMR[23]3 = 0 and
PMR[7] = 1) or
3
(PMR[23]
PMR[15] = 1 and
= 1 and
PMR[7] = 1)
PMR[23]3 = 1 and
PMR[15] = 0
V
IO
(PMR[23]3 = 0 and
PMR[5] = 0) or
3
(PMR[23]
PMR[15] = 1 and
= 1 and
PMR[5] = 0)
(PMR[23]3 = 0 and
PMR[5] = 1) or
3
(PMR[23]
PMR[15] = 1 and
PMR[5] = 1)
PMR[23]3 = 1 and
PMR[15] = 0
= 1 and
VIO---
---
C-
CCRT
---
C-
CCRT
32579B
Ball
No.Signal Name
2
PD7I/OINT,
A186,
I/O
(PU/PD)
TFTD13OO
F_AD7OO
A19V
A20
SS
6, 2
PD6I/OINT,
GND---------
TFTD1OO
VOPD0OO
F_AD6OO
6, 2
PD1I/OINT,
A21
TFTD7OO
VOPD6OO
F_AD1OO
6, 2
STB#/WRITE#OO
A22
TFTD17O
F_FRAME#OO
A23CVBSOWIRE AV
YO
TVGO
A24SVYOWIRE AV
TVRO
CbO
CVBSO
A25TVRSETIWIRE AV
6
DPOS_PORT3I/OIN
A26
6
DNEG_PORT3I/OIN
A27
Buffer
Typ e
O
14/14
1/4
14/14
O
14/14
1/4
1/4
14/14
O
14/14
1/4
1/4
14/14
14/14
1/4
O
14/14
USB
O
USB
USB
O
USB
1
,
,
Power
Rail Configuration
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
---
CCTV
AV
---
C-
CUSB
AV
---
C-
CUSB
AMD Geode™ SC1200/SC1201 Processor Data Book 29
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Ball
No.Signal Name
6
DPOS_PORT1I/OIN
A28
6
DNEG_PORT1I/OIN
A29
A30V
A31V
B1V
B2V
IO
SS
SS
IO
I/O
(PU/PD)
Buffer
PWR---------
GND---------
GND---------
PWR---------
B3AD29I/OIN
D5I/OIN
B4AD28I/OIN
D4I/OIN
B5REQ0#I
(PU
22.5
)
B6AD23I/OIN
A23OO
B7V
SS
GND---------
B8RD#OO
CLKSEL0I
(PD
100
IN
)
B9WR#OO
B10V
SS
GND---------
B11VSYNCOO
B12REDOWIREAV
B13V
B14AV
IO
SSCRT
PWR---------
GND---------
B15SETRESIWIREAV
B16V
B17
IO
6, 2
BUSY/WAIT#IIN
PWR---------
TFTD3OO
VOPD2OO
F_C/BE1#OO
Power
Typ e
,
USB
O
USB
,
USB
O
USB
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
INPCIV
,
PCI
O
PCI
PCI
3/5
STRP
3/5
1/4
T
1/4
1/4
1/4
AV
CUSB
AV
CUSB
CCRT
CCRT
Rail Configuration
---
C-
---
C-
VIOCycle Multiplexed
VIOCycle Multiplexed
---
IO
VIOCycle Multiplexed
VIO---
Strap (See Table 34 on page 44.)
V
IO
VIO---
---
C-
---
C-
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
Ball
No.Signal Name
6, 2
ACK#IIN
B18
TFTDEOO
VOPCKOO
FPCICLKOO
B19V
B20
IO
6,2
SLIN#/ASTRB#OO
TFTD16OO
F_IRDY#OO
6,2
INIT#OO
B21
TFTD5OO
VOPD4OO
SMI_OOO
B22V
SS
I/O
(PU/PD)
PWR---------
GND---------
Buffer
Typ e
1/4
1/4
1/4
14/14
1/4
14/14
14/14
1/4
1/4
14/14
1
T
B23TVIOMOWIREAV
B24AV
B25V
SSTV
SS
GND---------
GND---------
B26TVCOMPIWIREAV
6
DPOS_PORT2I/OIN
B27
6
DNEG_PORT2I/OIN
B28
B29GPIO10I/O
DSR2#I
(PU
(PU
IDE_IORDY1I
(PU
SDTEST1 O
B30V
B31V
SS
IO
(PU
GND---------
PWR---------
22.5
22.5
22.5
22.5
,
USB
O
USB
,
USB
O
USB
IN
,
TS
)
O
8/8
IN
TS
)
IN
TS1
)
O
2/5
)
Signal Definitions
Power
Rail Configuration
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
---
CCTV
---
CCTV
AV
---
C-
CUSB
AV
---
C-
CUSB
VIOPMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
30AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
C1AD26I/OIN
D2I/OIN
C2AD24I/OIN
D0I/OIN
C3V
IO
C4AD25I/OIN
D1I/OIN
C5GNT0#OO
DID0I
C6GNT1#OO
DID1I
C7V
IO
C8ROMCS#OO
BOOT16I
C9GPIO19I/O
INTC#I
IOCHRDYI
C10V
IO
C11IRTXOO
SOUT3OO
C12V
C13AV
C14AV
C15AV
C16AV
C17
SSCRT
CCCRT
SSCRT
SSCRT
SSPLL2
6,2
SLCTIIN
TFTD15OO
F_C/BE3#OO
C18PD4I/OIN
TFTD10OO
F_AD4OO
I/O
(PU/PD)
Buffer
PWR---------
IN
)
(PD
100
IN
)
(PD
100
PWR---------
IN
)
(PD
100
)
(PU
22.5
)
(PU
22.5
)
(PU
22.5
PWR---------
GND---------
PWR---------
GND---------
GND---------
GND---------
O
1
Typ e
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
,
PCI
O
PCI
PCI
STRP
PCI
STRP
3/5
STRPVIO
IN
,
TS
O
3/5
IN
TS
IN
TS1
8/8
8/8
T
1/4
1/4
,
T
14/14
1/4
14/14
Power
Rail Configuration
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
VIO---
Strap (See Table 34 on page 44.)
VIO---
Strap (See Table 34 on page 44.)
VIO---
Strap (See Table 34 on page 44.)
VIOPMR[9] = 0 and
PMR[4] = 0
PMR[9] = 0 and
PMR[4] = 1
PMR[9] = 1 and
PMR[4] = 1
VIOPMR[6] = 0
PMR[6] = 1
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
32579B
)
)
)
)
)
Buffer
Typ e
O
14/14
1/4
14/14
O
14/14
1/4
14/14
O
14/14
1/4
1/4
14/14
IN
PCI
IN
TS
O
1/4
IN
TS
O
1/4
O
2/5
1
,
Ball
No.Signal Name
6,2
PD5I/OINT,
C19
I/O
(PU/PD)
TFTD11OO
F_AD5OO
6,2
PD3I/OINT,
C20
TFTD9OO
F_AD3OO
6,2
PD0I/OINT,
C21
TFTD6OO
VOPD5OO
F_AD0OO
C22V
IO
PWR---------
C23SVCOWIREAV
CrO
CbO
TVBO
TVRO
C24TVREFI/OWIRE AV
C25V
IO
C26INTB#I
C27AV
SSUSB
C28GPIO9I/O
DCD2#I
IDE_IOW1#O
PWR---------
(PU
22.5
GND---------
(PU
22.5
(PU
22.5
(PU
22.5
SDTEST2 O
(PU
22.5
C29V
IO
PWR---------
Power
Rail Configuration
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
---
CCTV
VIO---
VIOPMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
AMD Geode™ SC1200/SC1201 Processor Data Book 31
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
C30GPIO7I/O
RTS2#O
IDE_DACK1#O
SDTEST0 O
C31GPIO8I/O
CTS2#I
IDE_DREQ1I
SDTEST4 O
D1AD21I/OIN
A21OO
D2AD22I/OIN
A22OO
D3AD20I/OIN
A20OO
D4AD27I/OIN
D3I/OIN
D5AD31I/OIN
D7I/OIN
D6PCICLK1OO
LPC_ROMI
D7V
SS
D8FRAME#I/O
D9IOR#OO
DOCR#OO
GPIO14I/O
D10GPIO1I/O
IOCS1#O
TFTD12O
I/O
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
100
)
)
)
)
)
)
)
)
)
Buffer
IN
IN
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PD
GND---------
IN
)
(PU
22.5
)
(PU
22.5
IN
)
(PU
22.5
(PU
)
22.5
(PU
)
22.5
Typ e
IN
TS
O
1/4
O
1/4
O
1/4
O
2/5
IN
TS
O
8/8
IN
TS1
O
2/5
PCI
O
PCI
PCI
PCI
O
PCI
PCI
PCI
O
PCI
PCI
PCI
O
PCI
PCI
O
PCI
PCI
O
PCI
PCI
O
PCI
PCI
STRP
PCI
O
PCI
3/5
3/5
IN
TS
O
3/5
, O
T
O
3/5
O
1/4
1
Power
Rail Configuration
,
VIOPMR[17] = 0 and
,
VIOPMR[17] = 0 and
TS
,
VIOCycle Multiplexed
,
VIOCycle Multiplexed
,
VIOCycle Multiplexed
,
VIOCycle Multiplexed
,
,
VIOCycle Multiplexed
,
VIO---
,
VIO---
VIOPMR[21] = 0 and
,
3/5VIO
V
IO
V
IO
PMR[8] = 0
PMR[17] = 1 and
PMR[8] = 0
PMR[17] = 0 and
PMR[8] = 1
PMR[17] = 1 and
PMR[8] = 1
PMR[8] = 0
PMR[17] = 1 and
PMR[8] = 0
PMR[17] = 0 and
PMR[8] = 1
PMR[17] = 1 and
PMR[8] = 1
Strap (See Table 34 on page 44.)
PMR[2] = 0
PMR[21] = 0 and
PMR[2] = 1
PMR[21] = 1 and
PMR[2] = 1
(PMR[23]3 = 0 and
PMR[13] = 0) or
3
(PMR[23]
PMR[15] = 1 and
= 1 and
PMR[13] = 0)
(PMR[23]3 = 0 and
PMR[13] = 1) or
3
(PMR[23]
PMR[15] = 1 and
PMR[13] = 1)
= 1 and
PMR[23]3 = 1 and
PMR[15] = 0
1
Ball
No.Signal Name
I/O
(PU/PD)
Buffer
D11TRDE#OO
GPIO0I/O
)
(PU
22.5
D12V
D13V
D14V
D15AV
CCCRT
SS
IO
CCCRT
PWR---------
GND---------
PWR---------
PWR---------
Typ e
3/5
IN
O
3/5
Power
,
TS
D16VREFI/OWIREAV
CCRT
6, 2
PEI
D17
TFTD14OO
F_C/BE2#OO
D18V
D19V
D20
IO
SS
6, 2
PD2I/OINT,
TFTD8OO
VOPD7OO
F_AD2OO
6, 2
ERR#IINT, O
D21
TFTD4OO
VOPD3OO
F_C/BE0#OO
(PU
PD
PWR---------
GND---------
22.5
22.5
IN
T
)
1/4
1/4
O
14/14
1/4
1/4
14/14
1/4VIO
1/4
1/4
1/4
Signal Definitions
Rail Configuration
VIOPMR[12] = 0
VIOPMR[12] = 1
---
C-
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under software control.)
PMR[23]3 = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
IO
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3 = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
32AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Ball
No.Signal Name
6, 2
AFD#/DSTRB#OO
D22
I/O
(PU/PD)
Buffer
TFTD2OO
VOPD1OO
INTR_OOO
D23AV
CCTV
PWR---------
D24CVBSOWIRE AV
CrO
TVBO
D25V
SS
D26INTA#I
D27AV
CCUSB
D28GPIO6I/O
DTR2#/BOUT2O
IDE_IOR1#O
SDTEST5 O
GND---------
)
(PU
22.5
PWR---------
(PU
)
22.5
(PU
)
22.5
)
(PU
22.5
)
(PU
22.5
D29SOUT2OO
CLKSEL2I
(PD
100
IN
)
D30TDPI/ODiode------
D31TDNI/OWIREV
E1AD16I/OIN
A16OO
E2AD19I/OIN
A19OO
E3AD18I/OIN
A18OO
E4DEVSEL#I/O
)
(PU
22.5
BHE#OO
E28SIN2IIN
SDTEST3 OO
E29TRST#I
(PU
22.5
)
E30TDOOO
E31TCKI
(PU
22.5
)
Typ e
14/14VIO
1/4
1/4
14/14
IN
PCI
,
IN
TS
O
1/4
O
1/4
O
1/4
O
2/5
8/8
STRP
,
PCI
O
PCI
PCI
,
PCI
O
PCI
PCI
,
PCI
O
PCI
PCI
IN
,
PCI
O
PCI
PCI
TS
2/5
IN
PCI
PCI
IN
PCI
Power
Rail Configuration
CCTV
VIO---
VIOPMR[18] = 0 and
VIO---
IO
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOPMR[28] = 0
VIO---
VIO---
VIO---
PMR[23]3 = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 1 and
PMR[15] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]3= 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]3 = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 356.
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
Strap (See Table 34 on page 44.)
---
PMR[28] = 1
32579B
Ball
No.Signal Name
F1TRDY#I/O
D13I/O
F2IRDY#I/O
D14I/O
F3C/BE2#I/O
D10I/O
F4AD17I/OIN
A17OO
F28TMSI
F29TDII
F30GTESTI
F31VPCKINIIN
G1STOP#I/O
D15I/O
G2V
G3V
G4V
G28V
G29V
G30V
SS
IO
SS
SS
IO
SS
G31VPD7IIN
H1SERR#I/O
H2PERR#I/O
H3LOCK#I/O
H4C/BE3#I/O
D11I/O
H28VPD6IIN
H29VPD5IIN
H30VPD4IIN
H31VPD3IIN
J1AD13I/OIN
A13OO
I/O
Buffer
22.5
22.5
22.5
22.5
Typ e
IN
)
O
IN
)
O
IN
)
O
IN
)
O
(PU/PD)
(PU
(PU
(PU
(PU
IN
)
(PU
22.5
O
IN
)
(PU
22.5
O
O
IN
)
(PU
22.5
22.5
22.5
22.5
22.5
IN
)
)
IN
)
O
IN
)
O
(PU
(PD
(PU
(PU
GND---------
PWR---------
GND---------
GND---------
PWR---------
GND---------
22.5
22.5
22.5
22.5
IN
)
OD
IN
)
O
IN
)
O
IN
)
O
(PU
(PU
(PU
(PU
IN
)
(PU
22.5
O
O
1
Power
Rail Configuration
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
PCI
PCI
PCI
IN
T
T
,
PCI
PCI
,
PCI
PCI
T
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
,
PCI
PCI
T
T
T
T
,
PCI
PCI
PCI
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
VIO---
VIO---
VIO---
VIO---
VIOCycle Multiplexed
VIO---
VIO---
VIO---
VIO---
VIOCycle Multiplexed
VIO---
VIO---
VIO---
VIO---
VIOCycle Multiplexed
AMD Geode™ SC1200/SC1201 Processor Data Book 33
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
J2C/BE1#I/O
D9I/O
J3AD15I/OIN
A15OO
J4PARI/O
D12I/O
J28VPD2IIN
J29VPD1IIN
J30VPD0IIN
J31GPIO39I/O
SERIRQ I/OIN
K1AD11I/OIN
A11OO
K2V
K3V
IO
SS
K4AD14I/OIN
A14OO
K28GPIO38/IRRX2I/O
LPCPD#OO
K29V
K30V
IO
SS
K31GPIO37I/O
LFRAME#OO
L1C/BE0#I/O
D8I/O
L2AD9I/OIN
A9OO
I/O
Buffer
22.5
22.5
Typ e
IN
)
O
IN
)
O
(PU/PD)
(PU
(PU
O
(PU
(PU
(PU
22.5
22.5
22.5
O
IN
)
O
IN
)
O
IN
)
O
O
PWR---------
GND---------
O
22.5
IN
)
O
(PU
PWR---------
GND---------
(PU
(PU
22.5
22.5
O
IN
)
O
IN
)
IN
)
(PU
22.5
O
O
1
Power
Rail Configuration
,
VIOCycle Multiplexed
PCI
PCI
,
PCI
PCI
,
VIOCycle Multiplexed
PCI
PCI
PCI
,
VIOCycle Multiplexed
PCI
PCI
,
PCI
PCI
VIO---
T
VIO---
T
VIO---
T
,
V
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
IO
,
,
VIOCycle Multiplexed
,
VIOCycle Multiplexed
,
V
IO
,
V
IO
,
VIOCycle Multiplexed
,
,
VIOCycle Multiplexed
PMR[14]4 = 0 and
4
PMR[22]
PMR[14]4 = 1 and
PMR[22]
PMR[14]4 = 0 and
PMR[22]
IRRX2 input is connected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a simple connection.
Hence, when
GPIO38 is the
selected function,
IRRX2 is also
= 0
4
= 1
4
= 0. The
selected.
PMR[14]4 = 1 and
4
4
4
= 1
= 0
= 1
PMR[22]
PMR[14]4 = 0 and
PMR[22]
PMR[14]4 = 1 and
PMR[22]
Ball
No.Signal Name
I/O
(PU/PD)
Buffer
L3AD10I/OIN
A10OO
L4AD12I/OIN
A12OO
L28GPIO36I/O
(PU
22.5
)
LDRQ#IIN
L29GPIO35I/O
LAD3I/O
L30GPIO34I/O
LAD2I/O
(PU
(PU
(PU
(PU
22.5
22.5
22.5
22.5
)
)
)
)
L31GPIO33I/O
(PU
)
22.5
LAD1I/O
M1V
SS
)
(PU
22.5
GND---------
M2AD7I/OIN
A7OO
M3V
IO
PWR---------
M4AD8I/OIN
A8OO
M28GPIO32I/O
)
(PU
22.5
LAD0 I/O
(PU
22.5
)
M29GPIO13I/O
(PU
)
22.5
AB2DI/O
)
(PU
22.5
M30V
M31V
IO
SS
PWR---------
GND---------
N1AD3I/OIN
A3OO
N2AD6I/OIN
A6OO
N3AD5I/OIN
A5OO
N4V
N13V
N14V
SS
CORE
CORE
GND---------
PWR---------
PWR---------
Typ e
PCI
O
PCI
PCI
PCI
O
PCI
PCI
IN
PCI
O
PCI
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
PCI
O
PCI
PCI
PCI
O
PCI
PCI
IN
PCI
O
PCI
IN
PCI
O
PCI
IN
AB
O
8/8
IN
AB
OD
PCI
O
PCI
PCI
PCI
O
PCI
PCI
PCI
O
PCI
PCI
Signal Definitions
1
Power
Rail Configuration
,
VIOCycle Multiplexed
,
VIOCycle Multiplexed
,
V
IO
PMR[14]4 = 0 and
PMR[22]
PMR[14]4 = 1 and
PMR[22]
,
V
IO
PMR[14]4 = 0 and
PMR[22]
,
,
,
,
,
,
,
,
,
,
,
8
,
,
,
PMR[14]4 = 1 and
PMR[22]
V
IO
PMR[14]4 = 0 and
PMR[22]
PMR[14]4 = 1 and
PMR[22]
V
IO
PMR[14]4 = 0 and
PMR[22]
PMR[14]4 = 1 and
PMR[22]
VIOCycle Multiplexed
VIOCycle Multiplexed
V
IO
PMR[14]4 = 0 and
PMR[22]
PMR[14]4 = 1 and
PMR[22]
VIOPMR[19] = 0
VIOPMR[19] = 1
VIOCycle Multiplexed
VIOCycle Multiplexed
VIOCycle Multiplexed
4
= 0
4
= 1
4
= 0
4
= 1
4
= 0
4
= 1
4
= 0
4
= 1
4
= 0
4
= 1
34AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
N15V
N16V
N17V
N18V
N19V
N28V
SS
SS
SS
CORE
CORE
SS
N29GPIO12I/O
AB2CI/O
N30AB1DI/O
GPIO1I/O
IOCS1#OO
N31AB1CI/O
GPIO20I/O
DOCCS#OO3/5
P1AD4I/OIN
A4OO
P2IDE_CS1#OO
TFTDEOO
P3AD1I/OIN
A1OO
P4V
P13V
P14V
P15V
P16V
P17V
P18V
P19V
P28V
CORE
CORE
CORE
SS
SS
SS
CORE
CORE
CORE
P29SDATA_OUTOO
TFT_PRSNTI
P30SYNCOO
CLKSEL3I
P31AC97_CLKOO
R1V
R2V
SS
SS
I/O
(PU/PD)
GND---------
GND---------
GND---------
PWR---------
PWR---------
GND---------
(PU
)
22.5
)
(PU
22.5
)
(PU
22.5
IN
)
(PU
22.5
(PU
)
22.5
IN
(PU
)
22.5
PWR---------
PWR---------
PWR---------
GND---------
GND---------
GND---------
PWR---------
PWR---------
PWR---------
)
(PD
100
)
(PD
100
GND---------
GND---------
1
Buffer
Typ e
,
IN
AB
O
8/8
IN
,
AB
OD
8
IN
,
AB
OD
8
, O
T
3/5
3/5
IN
,
AB
OD
8
, O
T
3/5
,
PCI
O
PCI
PCI
1/4
1/4
,
PCI
O
PCI
PCI
AC97
IN
STRPVIO
AC97
IN
STRP
2/5
Power
Rail Configuration
VIOPMR[19] = 0
PMR[19] = 1
V
IO
PMR[23]3 = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
PMR[23]3 = 1 and
PMR[15] = 0 and
PMR[13] = 0
PMR[23]3 = 1 and
PMR[15] = 0 and
PMR[13] = 1
V
IO
PMR[23]3 = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
PMR[23]3 = 1 and
PMR[15] = 0 and
PMR[7] = 0
3
PMR[23]
PMR[15] = 0 and
PMR[7] = 1
= 1 and
VIOCycle Multiplexed
VIOPMR[24] = 0
PMR[24] = 1
VIOCycle Multiplexed
VIO---
Strap (See Table 34 on page 44.)
VIO---
Strap (See Table 34 on page 44.)
VIOPMR[25] = 1
32579B
Ball
No.Signal Name
R3V
R4V
R13V
R14V
R15V
R16V
R17V
R18V
R19V
R28V
R29V
R30V
R31V
T1V
T2V
T3V
T4V
T13V
T14V
T15V
T16V
T17V
T18V
T19V
T28V
T29V
T30V
T31V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
CORE
CORE
CORE
CORE
SS
SS
SS
SS
SS
SS
SS
CORE
CORE
CORE
CORE
U1AD0I/OIN
A0OO
U2IDE_ADDR2OO
TFTD4OO
U3AD2I/OIN
A2OO
U4V
U13V
U14V
U15V
U16V
U17V
U18V
U19V
U28V
CORE
SS
SS
SS
SS
SS
SS
SS
CORE
U29AC97_RST#OO
F_STOP#OO
I/O
(PU/PD)
Buffer
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
PWR---------
PWR---------
PWR---------
PWR---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
PWR---------
PWR---------
PWR---------
PWR---------
PWR---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
GND---------
PWR---------
Typ e
PCI
O
PCI
PCI
1/4
1/4
PCI
O
PCI
PCI
2/5
2/5
1
Power
Rail Configuration
,
VIOCycle Multiplexed
VIOPMR[24] = 0
PMR[24] = 1
,
VIOCycle Multiplexed
VIOFPCI_MON = 0
FPCI_MON = 1
AMD Geode™ SC1200/SC1201 Processor Data Book 35
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
U30BIT_CLKIIN
F_TRDY#OO
U31SDATA_INIIN
F_GNT0#OO
V1IDE_DATA15I/OIN
TFTD7OO
V2IDE_DATA14I/OIN
TFTD17OO
V3IDE_DATA13I/OIN
TFTD15OO
V4V
V13V
V14V
V15V
V16V
V17V
V18V
V19V
V28V
SS
CORE
CORE
SS
SS
SS
CORE
CORE
SS
V29SDCLK3OO
V30GXCLKOO
FP_VDD_ONOO
TEST3OO
V31GPIO16I/O
PC_BEEPOO
F_DEVSEL#OO
W1V
W2V
IO
SS
W3IDE_DATA12I/OIN
TFTD13OO
W4IDE_DATA11I/OIN
GPIO41I/OIN
W13V
W14V
W15V
W16V
W17V
W18V
CORE
CORE
SS
SS
SS
CORE
I/O
Buffer
(PU/PD)
Typ e
TS
TS
TS
GND---------
PWR---------
PWR---------
GND---------
GND---------
GND---------
PWR---------
PWR---------
GND---------
IN
T
)
(PU
22.5
PWR---------
GND---------
TS
TS
O
PWR---------
PWR---------
GND---------
GND---------
GND---------
PWR---------
1
Power
Rail Configuration
VIOFPCI_MON = 0
T
1/4
VIOFPCI_MON = 0
T
2/5
,
VIOPMR[24] = 0
TS1
1/4
1/4
,
VIOPMR[24] = 0
TS1
1/4
1/4
,
VIOPMR[24] = 0
TS1
1/4
1/4
VIO---
2/5
VIO(PMR[29] = 0 and
2/5
1/4
2/5
, O
2/5VIO
2/5
2/5
,
VIOPMR[24] = 0
TS1
1/4
1/4
,
VIOPMR[24] = 0
TS1
1/4
,
TS1
1/4
FPCI_MON = 1
FPCI_MON = 1
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
3
PMR[23]
(PMR[23]
PMR[15] = 1)
= 0) or
3
= 1 and
PMR[23]3 = 1 and
PMR[15] = 0
PMR[29] = 1 and
3
PMR[23]
PMR[0] = 0 and
FPCI_MON = 0
PMR[0] = 1 = 0 and
FPCI_MON = 0
= 0
FPCI_MON = 1
PMR[24] = 1
PMR[24] = 1
Ball
No.Signal Name
W19V
W28
CORE
6
MD57I/OINT, TS
I/O
(PU/PD)
Buffer
PWR---------
W29SDCLK1OO
W30V
W31V
Y1
SS
IO
5
IDE_DATA10I/OIN
GND---------
PWR---------
DDC_SCLOOD
5
IDE_DATA9I/OIN
Y2
DDC_SDAI/OIN
Y3IDE_DATA8I/OIN
GPIO40I/OIN
Y4IDE_IOR0#OO
TFTD10OO
6
MD58I/OINT, TS
Y28
6
MD59I/OINT, TS
Y29
6
MD60I/OINT, TS
Y30
6
MD56I/OINT, TS
Y31
AA1IDE_RST#OO
TFTDCKOO
AA2IDE_DATA7I/OIN
INTD#IIN
AA3IDE_DATA6I/OIN
IRQ9IIN
AA4IDE_DATA5I/OIN
CLK27MOO
AA28SDCLK2OO
6
MD61I/OINT, TS
AA29
6
MD62I/OINT, TS
AA30
6
MD63I/OINT, TS
AA31
AB1IDE_DATA4I/OIN
FP_VDD_ONOO
AB2V
AB3V
SS
IO
GND---------
PWR---------
AB4IDE_DATA3I/OIN
TFTD12OO
6
MD24I/OINT, TS
AB28
AB29V
AB30V
IO
SS
PWR---------
GND---------
AB31DQM7OO
Typ e
2/5
TS1
TS
TS1
TS
, OD
T
TS1
TS
TS1
O
1/4
1/4
1/4
1/4
1/4
TS1
TS
TS1
TS
TS1
TS1
TS
1/4
2/5
TS1
TS
1/4
TS1
TS
1/4
2/5
1
Power
Rail Configuration
2/5VIO
VIO---
,
VIOPMR[24] = 0
1/4
4
,
VIOPMR[24] = 0
1/4
4
,
VIOPMR[24] = 0
1/4
,
VIOPMR[24] = 0
2/5VIO
2/5VIO
2/5VIO
2/5VIO
VIOPMR[24] = 0
,
VIOPMR[24] = 0
1/4
TS
,
VIOPMR[24] = 0
1/4
,
VIOPMR[24] = 0
1/4
VIO---
2/5VIO
2/5VIO
2/5VIO
,
VIOPMR[24] = 0
1/4
,
VIOPMR[24] = 0
1/4
2/5VIO
VIO---
Signal Definitions
---
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
---
---
---
---
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
---
---
---
PMR[24] = 1
PMR[24] = 1
---
36AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
Ball
No.Signal Name
AC1IDE_DATA1I/OIN
TFTD16OO
AC2IDE_DATA2I/OIN
TFTD14OO
AC3IDE_DATA0I/OIN
TFTD6OO
AC4IDE_DREQ0IIN
TFTD8OO
6
MD25I/OINT, TS
AC28
6
MD26I/OINT, TS
AC29
6
MD27I/OINT, TS
AC30
AC31DQM3OO
AD1IDE_IORDY0IIN
TFTD11OO
AD2IDE_IOW0#OO
TFTD9OO
AD3IDE_ADDR0OO
TFTD3OO
AD4IDE_DACK0#OO
TFTD0OO
6
MD52I/OINT, TS
AD28
6
MD29I/OINT, TS
AD29
6
MD30I/OINT, TS
AD30
6
MD31I/OINT, TS
AD31
AE1IDE_ADDR1OO
TFTD2OO
AE2V
AE3V
AE4V
AE28V
AE29V
AE30V
AE31
SS
IO
SS
SS
IO
SS
6
MD28I/OINT, TS
AF1IRQ14IIN
TFTD1OO
AF2IDE_CS0#OO
TFTD5OO
AF3SOUT1OO
CLKSEL1I
AF4OVER_CUR#IIN
6
MD50I/OINT, TS
AF28
6
MD49I/OINT, TS
AF29
6
MD54I/OINT, TS
AF30
6
MD53I/OINT, TS
AF31
I/O
(PU/PD)
Buffer
GND---------
PWR---------
GND---------
GND---------
PWR---------
GND---------
(PD
)
100
Typ e
TS
TS
TS
IN
1
Power
Rail Configuration
,
VIOPMR[24] = 0
TS1
1/4
1/4
,
VIOPMR[24] = 0
TS1
1/4
1/4
,
VIOPMR[24] = 0
TS1
1/4
1/4
VIOPMR[24] = 0
TS1
1/4
2/5VIO
2/5VIO
2/5VIO
VIO---
2/5
VIOPMR[24] = 0
TS1
1/4
VIOPMR[24] = 0
1/4
1/4
VIOPMR[24] = 0
1/4
1/4
VIOPMR[24] = 0
1/4
1/4
2/5VIO
2/5VIO
2/5VIO
2/5VIO
VIOPMR[24] = 0
1/4
1/4
2/5VIO
VIOPMR[24] = 0
TS1
1/4
VIOPMR[24] = 0
1/4
1/4
VIO---
8/8
STRP
VIO---
TS
2/5VIO
2/5VIO
2/5VIO
2/5VIO
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
---
---
---
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
PMR[24] = 1
---
---
---
---
PMR[24] = 1
---
PMR[24] = 1
PMR[24] = 1
Strap (See Table 34 on page 44.)
---
---
---
---
32579B
1
Ball
No.Signal Name
AG1GPIO18I/O
DTR1#/BOUT1O
I/O
(PU/PD)
(PU
22.5
(PU
22.5
Buffer
)
)
AG2SIN1IIN
AG3X27IIWIREV
TEST1OO
AG4
PLL6BI/OIN
6
MD21I/OINT, TS
AG28
AG29DQM6OO
AG30DQM2OO
6
MD55I/OINT, TS
AG31
AH1POWER_ENOO
AH2X27OOWIREV
TEST0OO
AH3
PLL2BI/OIN
AH4V
IO
AH5PWRBTN#I
AH6GPWIO0I/O
AH7V
SS
PWR---------
(PU
)
100
)
(PU
100
TS
GND---------
AH8CLK32OO
AH9POR#IIN
6
MD3I/OINT, TS
AH10
6
MD5I/OINT, TS
AH11
AH12WEA#OO
AH13V
AH14V
SS
IO
GND---------
PWR---------
AH15MA1OO
6
MD34I/OINT, TS
AH16
6
MD37I/OINT, TS
AH17
AH18V
AH19V
AH20
IO
SS
6
MD41I/OINT, TS
PWR---------
GND---------
AH21MA9OO
AH22MA8OO
AH23DQM1OO
6
MD13I/OINT, TS
AH24
AH25V
SS
GND---------
AH26MA11OO
AH27CS1#OO
6
MD18I/OINT, TS
AH28
6
MD48I/OINT, TS
AH29
6
MD20I/OINT, TS
AH30
6
MD51I/OINT, TS
AH31
Typ e
IN
,
TS
O
8/8
O
8/8
TS
2/5
,
TS
TS
2/5
2/5VIO
2/5
2/5
2/5VIO
1/4
2/5
, TS
T
2/5
IN
BTNVSB
IN
,
TS
2/14
2/5
TS
2/5VIO
2/5VIO
2/5
2/5
2/5VIO
2/5VIO
2/5VIO
2/5
2/5
2/5
2/5VIO
2/5
2/5
2/5VIO
2/5VIO
2/5VIO
2/5VIO
Power
Rail Configuration
VIOPMR[16] = 0
PMR[16] =1
VIO---
---
IO
VIOPMR[29] = 1
PMR[29] = 0
---
VIO---
VIO---
---
VIO---
---
IO
VIOPMR[29] = 1
PMR[29] = 0
---
VSB---
VSB---
VIO---
---
---
VIO---
VIO---
---
---
---
VIO---
VIO---
VIO---
---
VIO---
VIO---
---
---
---
---
AMD Geode™ SC1200/SC1201 Processor Data Book 37
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Ball
No.Signal Name
TEST2OO
AJ1
I/O
(PU/PD)
Buffer
PLL5BI/OIN
AJ2X32IIWIREV
AJ3X32OOWIREV
AJ4V
AJ5
PLL3
6, 2
ONCTL#OOD
AJ6GPWIO2I/O
AJ7V
IO
AJ8GPIO11I/O
RI2#I
IRQ15I
6
MD0I/OINT, TS
AJ9
AJ10V
AJ11
IO
6
MD6I/OINT, TS
PWR---------
)
(PU
100
TS
PWR---------
IN
)
(PU
22.5
)
(PU
22.5
)
(PU
22.5
PWR---------
AJ12CASA#OO
AJ13BA0OO
AJ14MA10OO
6
MD32I/OINT, TS
AJ15
6
MD33I/OINT, TS
AJ16
6
MD36I/OINT, TS
AJ17
6
MD47I/OINT, TS
AJ18
6
MD45I/OINT, TS
AJ19
6
MD42I/OINT, TS
AJ20
AJ21SDCLK0OO
AJ22V
IO
PWR---------
AJ23MA6OO
AJ24MA3OO
AJ25V
AJ26
IO
6
MD11I/OINT, TS
PWR---------
AJ27SDCLK_INIIN
6
MD19I/OINT, TS
AJ28
AJ29V
AJ30
AJ31
AK1V
AK2V
AK3AV
IO
6
MD22I/OINT, TS
6
MD17I/OINT, TS
IO
SS
SSPLL3
PWR---------
PWR---------
GND---------
GND---------
AK4THRM#IIN
AK5GPWIO1I/O
6, 2
PWRCNT1OOD
AK6
AK7V
SS
)
(PU
100
TS
GND---------
AK8IRRX1IIN
SIN3IIN
Typ e
, TS
T
IN
TS
8
IN
IN
TS1
IN
2/5
2/5
14
,
TS
2/14
, O
8/
TS
2/5VIO
2/5VIO
2/5
2/5
2/5
2/5VIO
2/5VIO
2/5VIO
2/5VIO
2/5VIO
2/5VIO
2/5
2/5
2/5
2/5VIO
T
2/5VIO
2/5VIO
2/5VIO
TS
,
TS
2/14
14
TS
TS
Power
Rail Configuration
VIOPMR[29] = 1
PMR[29] = 0
---
BAT
---
BAT
VSB---
VSB---
VIOPMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
---
---
VIO---
VIO---
VIO---
---
---
---
---
---
---
VIO---
VIO---
VIO---
---
VIO---
---
---
---
VSB---
VSB---
VSB---
VSBPMR[6] = 0
VIOPMR[6] =1
Ball
No.Signal Name
6
MD1I/OINT, TS
AK9
AK10V
AK11
SS
6
MD7I/OINT, TS
I/O
(PU/PD)
Buffer
Typ e
GND---------
AK12RASA#OO
AK13V
IO
PWR---------
AK14BA1OO
AK15MA2OO
AK16V
AK17
AK18
AK19V
AK20
IO
6
MD35I/OINT, TS
6
MD46I/OINT, TS
IO
6
MD43I/OINT, TS
PWR------
PWR---------
AK21DQM5OO
AK22V
SS
GND---------
AK23MA5OO
6
MD15I/OINT, TS
AK24
AK25V
AK26
AK27
SS
6
MD14I/OINT, TS
6
MD12I/OINT, TS
GND---------
AK28SDCLK_OUTOO
6
MD16I/OINT, TS
AK29
AK30V
AK31V
AL1V
AL2V
AL3V
SS
IO
SS
IO
BAT
GND---------
PWR---------
GND---------
PWR---------
PWR---------
AL4LED#OOD
AL5V
AL6V
AL7
SB
SBL
6, 2
PWRCNT2O
PWR---------
PWR---------
OD
AL8SDATA_IN2IIN
6
MD2I/OINT, TS
AL9
6
MD4I/OINT, TS
AL10
AL11DQM0OO
AL12CS0#OO
AL13V
SS
GND---------
AL14MA0OO
AL15DQM4OO
AL16V
AL17
AL18
AL19V
AL20
AL21
SS
6
MD38I/OINT, TS
6
MD39I/OINT, TS
SS
6
MD44I/OINT, TS
6
MD40I/OINT, TS
GND---------
GND---------
AL22CKEAOO
AL23MA7OO
Signal Definitions
1
Power
Rail Configuration
2/5VIO
2/5VIO
VIO---
2/5
VIO---
2/5
VIO---
2/5
2/5VIO
2/5VIO
2/5VIO
VIO---
2/5
VIO---
2/5
2/5VIO
2/5VIO
2/5VIO
VIO---
2/5
2/5VIO
VSB---
14
14
VSB---
VSBF3BAR0+Memory
TS
2/5VIO
2/5VIO
VIO---
2/5
VIO---
2/5
VIO---
2/5
VIO---
2/5
2/5VIO
2/5VIO
2/5VIO
2/5VIO
VIO---
2/5
VIO---
2/5
---
---
---
---
---
---
---
---
---
Offset 08h[21] = 1
---
---
---
---
---
---
38AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Ball
No.Signal Name
I/O
(PU/PD)
Buffer
AL24MA4OO
6
MD8I/OINT, TS
AL25
6
MD10I/OINT, TS
AL26
6
MD9I/OINT, TS
AL27
AL28MA12OO
6
MD23I/OINT, TS
AL29
AL30V
AL31V
1.For Buffer Type definitions, refer to Table 9-10 "Buffer Types" on page
Several balls are read at power-up that set up the state of
the SC1200/SC1201 processor. These balls are typically
multiplexed with other functions that are outputs after the
power-up sequence is complete. The SC1200/SC1201 processor must read the state of the balls at power-up and the
internal PU or PD resistors do not guarantee the correct
state will be read. Therefore, it is required that an external
Table 3-4. Strap Options
Nominal
Internal
Strap Option Muxed WithBall No.
CLKSEL0RD#B8PD
CLKSEL1SOUT1AF3PD
CLKSEL2SOUT2D29PD
CLKSEL3SYNCP30PD
BOOT16ROMCS#C8PD
TFT_PRSNT SDATA_OUTP29PD
LPC_ROMPCICLK1D6PD
FPCI_MONPCICLK0A4PD
DID0GNT0#C5PD
DID1GNT1#C6PD
Note:Accuracy of internal PU/PD resistors: 80K to 250K.
Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC1200/SC1201Processor Specification Update document.
PU or PD
External PU/PD Strap Settings
See Table 4-7 on page 85 for
100
CLKSEL strap options.
100
100
100
Enable boot
100
from 8-bit ROM
TFT not muxed
100
onto Parallel
Por t
Disable boot
100
from ROM on
LPC bus
Disable Fast-
100
PCI, INTR_O,
and SMI_O
monitoring signals.
Defines the system-level chip ID.GCB+I/O Offset 34h[31,29] (aka MCR regis-
100
100
Signal Definitions
PU or PD resistor with a value of 1.5 KΩ be placed on the
balls listed in Table 3-4. The value of the resistor is important to ensure that the proper state is read during the
power-up sequence. If the ball is not read correctly at
power-up, the SC1200/SC1201 processor may default to a
state that causes it to function improperly, possibly resulting in application failure.
Register ReferencesStrap = 0 (PD)Strap = 1 (PU)
GCB+I/O Offset 1Eh[9:8] (aka CCFC register
bits [9:8]) (RO): Value programmed at reset
by
CLKSEL[1:0].
GCB+I/O Offset 10h[3:0] (aka MCCM register bits [3:0]) (RO): Value programmed at
reset by
CLKSEL[3:0].
GCB+I/O Offset 1Eh[3:0] (aka CCFC register
bits [3:0]) (R/W, but write not recommended):
Value programmed at reset by CLKSEL[3:0].
Note: Values for GCB+I/O Offset 10h[3:0]
and 1Eh[3:0] are not the same.
Enable boot
from 16-bit
ROM
TFT muxed
onto Parallel
Por t
Enable boot
from ROM on
LPC bus
Enable FastPCI, INTR_O,
and SMI_O
monitoring signals. (Useful
during debug.)
GCB+I/O Offset 34h[3] (aka MCR register bit
3) (RO): Reads back strap setting.
GCB+I/O Offset 34h[14] (R/W): Used to allow
the ROMCS# width to be changed under program control.
GCB+I/O Offset 30h[23] (aka PMR register
bit 23) (R/W): Reads back strap setting.
F0BAR1+I/O Offset 10h[15] (R/W): Reads
back strap setting and allows LPC ROM to be
changed under program control.
GCB+I/O Offset 34h[30] (aka MCR register
bit 30) (RO): Reads back strap setting.
Note:For normal operation, strap this sig-
nal low using a 1.5 KΩ resistor.
ter bits 31 and 29) (RO): Reads back strap
setting.
Note:These signals should be connected
to a 1.5 KΩ PD resistor to ensure a
low level at power-up.
44AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
3.3Multiplexing Configuration
The tables that follow list multiplexing options and their
configurations. Certain multiplexing options may be chosen
per signal; others are available only for a group of signals.
Where ever a GPIO pin is multiplexed with another function, there is an optional pull-up resistor on this pin; after
Table 3-5. Two-Signal/Group Multiplexing
DefaultAlternate
32579B
system reset, the pull-up is present. This pull-up resistor
can be disabled by writing Core Logic registers. The configuration is without regard to the selected ball function. The
above applies to all pins multiplexed with GPIO, except
GPIO12, GPIO13, and GPIO16.
During system reset, an internal pull-down resistor of 100
KΩ exists on these balls. An external pull-up or pull-down
resistor of 1.5 KΩ must be used.
are used to set the maximum allowed multiplier value for
the core clock.
During system reset, an internal pull-down resistor of 100
KΩ exists on these balls. An external pull-up or pull-down
resistor of 1.5 KΩ must be used.
the optional 16-bit wide Sub-ISA bus.
During system reset, an internal pull-down resistor of 100
KΩ exists on these balls. An external pull-up or pull-down
resistor of 1.5 KΩ must be used.
bus and sets bit F0BAR1+I/O Offset 10h[15], LPC ROM
Addressing Enable. It enables the SC1200/SC1201 processor to boot from a ROM connected to the LPC bus.
During system reset, an internal pull-down resistor of 100
KΩ exists on these balls. An external pull-up or pull-down
resistor of 1.5 KΩ must be used.
signals at power-up. Enables using TFT instead of Parallel Port, ACB1, and GPIO17.
During system reset, an internal pull-down resistor of 100
KΩ exists on these balls. An external pull-up or pull-down
resistor of 1.5 KΩ must be used.
tion of Fast-PCI monitoring signals. For normal operation,
strap this signal low using a 1.5 KΩ resistor. The value of
this strap can be read at MCR[30].
the system-level chip ID.
The value of DID1 can be read in the MCR[29]. The
value of DID0 can be read in the MCR[31].
DID1 and DID0 should be connected to a 1.5 KΩ pulldown resistor to ensure a low level at power-up.
erated from the power supply to indicate that the system
should be reset.
SOUT1
SYNC
ROMCS#
PCICLK1
SDATA_OUT
PCICLK0
GNT1#
---
AMD Geode™ SC1200/SC1201 Processor Data Book49
32579B
Signal Definitions
3.4.1System Interface (Continued)
Signal NameBall No.TypeDescriptionMux
X32IAJ2I/OCrystal Connections. Connected directly to a 32.768
X32OAJ3---
KHz crystal. This clock input is required even if the internal RTC is not being used. Some of the internal clocks
---
are derived from this clock. If an external clock is used, it
should be connected to X32I, using a voltage level of 0
volts to V
+10% maximum. X32O should remain
CORE
unconnected.
X27IAG3I/OCrystal Connections. Connected directly to a
X27OAH2---
27.000 MHz crystal. This clock input is used for video circuits. Some of the internal clocks are derived from this
---
clock. If the internal TV encoder is used, a 25 ppm crystal
is recommended. If an external clock is used, it should be
connected to X27I, using a voltage level of 0 volts to V
IO
and X27O should be remain unconnected.
CLK27MAA4O27 MHz Output Clock. Output of crystal oscillator.IDE_DATA5
PCIRST#A6OPCI and System Reset. PCIRST# is the reset signal for
--the PCI bus and system. It is asserted for approximately
100 µs after POR# is negated.
3.4.2Memory Interface Signals
Signal NameBall No.TypeDescriptionMux
MD[63:0]See
Table 3-3
on page
40
MA[12:0]See
Table 3-3
on page
40
BA1AK14OBank Address Bits. These bits are used to select the
BA0AJ13---
CS1#AH27OChip Selects. These bits are used to select the module
CS0#AL12---
RASA#AK12ORow Address Strobe. RAS#, CAS#, WE# and CKE are
CASA#AJ12OColumn Address Strobe. RAS#, CAS#, WE# and CKE
WEA#AH12OWrite Enable. RAS#, CAS#, WE# and CKE are encoded
I/OMemory Data Bus. The data bus lines driven to/from
system memory.
OMemory Address Bus. The multiplexed row/column
address lines driven to the system memory. Supports
256-Mbit SDRAM.
component bank within the SDRAM.
bank within system memory. Each chip select corresponds to a specific module bank. If CS# is high, the
bank(s) do not respond to RAS#, CAS#, and WE# until
the bank is selected again.
encoded to support the different SDRAM commands.
RASA# is used with CS[1:0]#.
are encoded to support the different SDRAM commands.
CASA# is used with CS[1:0]#.
to support the different SDRAM commands. WEA# is
used with CS[1:0]#.
---
---
---
---
---
---
---
50AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.2Memory Interface Signals (Continued)
Signal NameBall No.TypeDescriptionMux
DQM7AB31OData Mask Control Bits. During memory read cycles,
DQM6AG29---
DQM5AK21---
DQM4AL15---
DQM3AC31---
DQM2AG30---
these outputs control whether SDRAM output buffers are
driven on the MD bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs control
whether or not MD data is written into SDRAM.
DQM[7:0] connect directly to the [DQM7:0] pins of each
DIMM connector.
---
DQM1AH23---
DQM0AL11---
CKEAAL22OClock Enable. These signals are used to enter Suspend/
--power-down mode. CKEA is used with CS[1:0]#.
If CKEA goes low when no read or write cycle is in
progress, the SDRAM enters power-down mode. To
ensure that SDRAM data remains valid, the self-refresh
command is executed. To exit this mode, and return to
normal operation, drive CKEA high.
These signals should have an external pull-down resistor
of 33 KΩ.
SDCLK3V29OSDRAM Clocks. SDRAM uses these clocks to sample
SDCLK2AA28---
SDCLK1W29---
SDCLK0AJ21---
all control, address, and data lines. To ensure that the
Suspend mode functions correctly, SDCLK3 and
SDCLK1 should be used with CS1#. SDCLK2 and
SDCLK0 should be used together with CS0#.
SDCLK_INAJ27ISDRAM Clock Input. The SC1200/SC1201 processor
---
--samples the memory read data on this clock. Works in
conjunction with the SDCLK_OUT signal.
SDCLK_OUTAK28OSDRAM Clock Output. This output is routed back to
--SDCLK_IN. The board designer should vary the length of
the board trace to control skew between SDCLK_IN and
SDCLK.
3.4.3Video Port Interface Signals
Signal NameBall No.TypeDescriptionMux
VPD7G31IVideo Port Data. The data is input from the CCIR-656
VPD6H28---
video decoder.
VPD5H29---
VPD4H30---
VPD3H31---
VPD2J28---
VPD1J29---
VPD0J30---
VPCKINF31IVideo Port Clock Input. The clock input from the video
decoder.
AMD Geode™ SC1200/SC1201 Processor Data Book51
---
---
32579B
Signal Definitions
3.4.3Video Port Interface Signals (Continued)
Signal NameBall No.TypeDescriptionMux
VOPD7D20OVideo Output Port Data. The data is output from the
Video Processor in VESA Video Interface Port Rev 1.1
VOPD6A21PD1+TFTD7+
Task B format.
PD2+TFTD8+
F_AD2
F_AD1
VOPD5C21PD0+TFTD6+
F_AD0
VOPD4B21INIT#+TFTD5+
SMI_O
VOPD3D21ERR#+TFTD4+
F_CBE0#
VOPD2B17BUSY/WAIT#+
TFTD3+F_C/BE1#
VOPD1D22AFD#/DSTRB#+
TFTD2+INTR_O
VOPD0A20PD6+TFTD1+
F_AD6
VOPCKB18OVideo Output Port Clock. The clock output from the
Video Processor.
ACK#+TFTDE+
FPCICLK
3.4.4CRT/TFT Interface Signals
Signal NameBall No.TypeDescriptionMux
DDC_SCLY1ODDC Serial Clock. This is the serial clock for the VESA
IDE_DATA10
Display Data Channel interface. It is used for monitor
communications. The DDC2B standard is supported by
this interface.
DDC_SDAY2I/ODDC Serial Data. This is the bidirectional serial data sig-
IDE_DATA9
nal for the VESA Display Data Channel interface. It is
used for monitor communications. The DDC2B standard
is supported by this interface.
HSYNCA11OHorizontal Sync---
VSYNCB11OVertical Sync---
VREFD16I/OVol t a ge R ef e r en c e. Reference voltage for CRT PLL and
--DAC. This signal reflects the internal voltage reference. If
internal voltage reference is used (recommended), leave
this ball disconnected. If an external voltage reference is
used, this input is tied to a 1.235V reference.
SETRESB15ISet Resistor. This signal sets the current level for the
--RED/GREEN/BLUE analog outputs. Typically, a 464 Ω,
1% resistor is connected between this ball and AV
SSCRT
.
On-Chip RAMDAC
REDB12OAnalog Red, Green and Blue---
GREENA14---
BLUEA15---
TFT (External DAC) Interface
52AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.4CRT/TFT Interface Signals (Continued)
Signal NameBall No.TypeDescriptionMux
TFTDCKAA1OTFT Clock. Clock to external CRT DACs or TFT.IDE_RST#
A10GPIO17+ IOCS0#
TFTDEP2OTFT Data Enable. Can be used as blank signal to exter-
B18ACK#+VOPCK+
nal CRT DACs.
FP_VDD_ONAB1OTFT Power Control. Used to enable power to the Flat
V30GXCLK+TEST3
TFTD[17:0]See
Table 3-3
on page
40
Panel display, with power sequence timing.
ODigital RGB Data to TFT.
TFTD[5:0] - Connect to BLUE TFT inputs.
TFTD[11:6] - Connect to GREEN TFT inputs.
TFTD[17:12] - Connect to RED TFT inputs.
IDE_CS1#
FPCICLK
IDE_DATA4
The TFT interface is
muxed with the IDE
interface or the Par-
allel Port/VOP inter-
face. See Table 3-5
on page 45 and
Table 3-7 on page
48 for details.
AMD Geode™ SC1200/SC1201 Processor Data Book53
32579B
Signal Definitions
3.4.5TV Interface Signals
Signal NameBall No.TypeDescriptionMux
CVBSA23,
A24,
OComposite Video. Includes synchronization, luminance
and chrominance components of video.
D24
SVYA24OSuper Video Luminance. S-Video luminance signal.
SVCC23OSuper Video Chrominance. S-Video chrominance sig-
nal.
TVRA24,
OTV Red. TV Red component signal for SCART.
C23
TVGA23OTV Green. TV Green component signal for SCART.
TVBC23,
OTV Blue. TV Blue component signal for SCART.
D24
YA23OIntensity. Color intensity vector.
CrC23,
OChrominance Red. Red axis phase angle.
D24
CbA24,
OChrominance Blue. Blue axis phase angle.
C23
TVREFC24I/OVolt a g e R e f er e nc e . Reference voltage for TV DAC. This
signal reflects the internal voltage reference. If an external voltage reference is used, this input is tied to a
1.235V reference.
TVCOMPB26ICurrent Compensation for TV DAC. A 0.1 µF to 1.2 µF
capacitor is used to connect this ball to AV
CCTV
.
TVRSETA25ITV Set Resistor. This signal sets the current-level for the
TV DAC. Typically, an 1140 Ω, 1% resistor is connected
between this ball and AV
. The full scale current out-
SSTV
put of TV DACs is 32 * TVREF / TVRSET. An 1140 Ω, 1%
resistor enables driving a double terminated 75 Ω transmission line.
TVIOMB23OTV Output Dump Current. Typically, a 9.3 Ω, 1% resistor
is connected between this ball and AV
SSTV
.
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 356 for config-
uration details.
---
---
---
---
54AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.6ACCESS.bus Interface Signals
Signal NameBall No.TypeDescriptionMux
AB1CN31I/OACCESS.bus 1 Serial Clock. This is the serial clock for
GPIO20+DOCCS#
the interface.
Note: If selected as AB1C function but not used, tie
AB1C high.
AB1DN30I/OACCESS.bus 1 Serial Data. This is the bidirectional
GPIO1+IOCS1#
serial data signal for the interface.
Note: If AB1D function is selected but not used, tie
AB1D high.
AB2CN29I/OACCESS.bus 2 Serial Clock. This is the serial clock for
GPIO12
the interface.
Note: If AB2C function is selected but not used, tie
AB2C high.
AB2DM29I/OACCESS.bus 2 Serial Data. This is the bidirectional
GPIO13
serial data signal for the interface.
Note: If AB2D function is selected but not used, tie
AB2D high.
3.4.7PCI Bus Interface Signals
Signal NameBalL No.TypeDescriptionMux
PCICLKA7IPCI Clock. PCICLK provides timing for all transactions
on the PCI bus. All other PCI signals are sampled on the
rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCICLK0A4OPCI Clock Outputs. PCICLK0 and PCICLK1 provide
PCICLK1D6OLPC_ROM (Strap)
clock drives for the system at 33 MHz. These clocks are
asynchronous to PCI signals. There is low skew between
FPCI_MON (Strap)
all outputs. One of these clock signals should be connected to the PCICLK input. All PCI clock users in the
system (including PCICLK) should receive the clock with
as low a skew as possible.
AD[31:24]See
AD[23:0]A[23:0]
Table 3-3
on page
40
I/OMultiplexed Address and Data. A bus transaction con-
sists of an address phase in the cycle in which FRAME#
is asserted followed by one or more data phases. During
the address phase, AD[31:0] contain a physical 32-bit
address. For I/O, this is a byte address. For configuration
and memory, it is a DWORD address. During data
phases, AD[7:0] contain the least significant byte (LSB)
and AD[31:24] contain the most significant byte (MSB).
C/BE3#H4I/OMultiplexed Command and Byte Enables. During the
C/BE2#F3D10
C/BE1#J2D9
C/BE0#L1D8
address phase of a transaction when FRAME# is active,
C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# are used as byte enables. The byte
enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies
to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).
---
D[7:0]
D11
AMD Geode™ SC1200/SC1201 Processor Data Book55
32579B
Signal Definitions
3.4.7PCI Bus Interface Signals (Continued)
Signal NameBalL No.TypeDescriptionMux
INTA#D26IPCI Interrupts. The SC1200/SC1201 processor pro-
INTB#C26---
INTC#C9GPIO19+IOCHRDY
INTD#AA2IDE_DATA7
vides inputs for the optional “level-sensitive” PCI interrupts (also known in industry terms as PIRQx#). These
interrupts can be mapped to IRQs of the internal 8259A
interrupt controllers using PCI Interrupt Steering Registers 1 and 2 (F0 Index 5Ch and 5Dh).
---
Note: If selected as INTC# or INTD# function(s) but not
used, tie INTC# and INTD# high.
PA RJ 4I / OParity. Parity generation is required by all PCI agents.
D12
The master drives PAR for address- and write-data
phases. The target drives PAR for read-data phases. Parity is even across AD[31:0] and C/BE[3:0]#.
For address phases, PAR is stable and valid one PCI
clock after the address phase. It has the same timing as
AD[31:0] but is delayed by one PCI clock.
For data phases, PAR is stable and valid one PCI clock
after either IRDY# is asserted on a write transaction or
after TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one PCI clock
after the completion of the data phase. (Also see
PERR#.)
FRAME#D8I/OFrame Cycle. Frame is driven by the current master to
---
indicate the beginning and duration of an access.
FRAME# is asserted to indicate the beginning of a bus
transaction. While FRAME# is asserted, data transfers
continue. FRAME# is de-asserted when the transaction
is in the final data phase.
This signal is internally connected to a pull-up resistor.
IRDY#F2I/OInitiator Ready. IRDY# is asserted to indicate that the
D14
bus master is able to complete the current data phase of
the transaction. IRDY# is used in conjunction with
TRDY#. A data phase is completed on any PCI clock in
which both IRDY# and TRDY# are sampled as asserted.
During a write, IRDY# indicates that valid data is present
on AD[31:0]. During a read, it indicates that the master is
prepared to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together.
This signal is internally connected to a pull-up resistor.
TRDY#F1I/OTarget Ready. TRDY# is asserted to indicate that the tar-
D13
get agent is able to complete the current data phase of
the transaction. TRDY# is used in conjunction with
IRDY#. A data phase is complete on any PCI clock in
which both TRDY# and IRDY# are sampled as asserted.
During a read, TRDY# indicates that valid data is present
on AD[31:0]. During a write, it indicates that the target is
prepared to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted together.
This signal is internally connected to a pull-up resistor.
56AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.7PCI Bus Interface Signals (Continued)
Signal NameBalL No.TypeDescriptionMux
STOP#G1I/OTa rge t S t o p. STOP# is asserted to indicate that the cur-
rent target is requesting that the master stop the current
transaction. This signal is used with DEVSEL# to indicate
retry, disconnect, or target abort. If STOP# is sampled
active by the master, FRAME# is de-asserted and the
cycle is stopped within three PCI clock cycles. As an
input, STOP# can be asserted in the following cases:
1)If a PCI master tries to access memory that has
been locked by another master. This condition is
detected if FRAME# and LOCK# are asserted during an address phase.
2)If the PCI write buffers are full or if a previously buff-
ered cycle has not completed.
3)On read cycles that cross cache line boundaries.
This is conditional based upon the programming of
GX1 module’s PCI Configuration Register, Index
41h[1].
This signal is internally connected to a pull-up resistor.
LOCK#H3I/OLock Operation. LOCK# indicates an atomic operation
that may require multiple transactions to complete. When
LOCK# is asserted, non-exclusive transactions may proceed to an address that is not currently locked (at least
16 bytes must be locked). A grant to start a transaction
on PCI does not guarantee control of LOCK#. Control of
LOCK# is obtained under its own protocol in conjunction
with GNT#.
It is possible for different agents to use PCI while a single
master retains ownership of LOCK#. The arbiter can
implement a complete system lock. In this mode, if
LOCK# is active, no other master can gain access to the
system until the LOCK# is de-asserted.
This signal is internally connected to a pull-up resistor.
DEVSEL#E4I/ODevice Select. DEVSEL# indicates that the driving
device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether
any device on the bus has been selected. DEVSEL# is
also driven by any agent that has the ability to accept
cycles on a subtractive decode basis. As a master, if no
DEVSEL# is detected within and up to the subtractive
decode clock, a master abort cycle is initiated (except for
special cycles which do not expect a DEVSEL#
returned).
This signal is internally connected to a pull-up resistor.
D15
---
BHE#
AMD Geode™ SC1200/SC1201 Processor Data Book57
32579B
Signal Definitions
3.4.7PCI Bus Interface Signals (Continued)
Signal NameBalL No.TypeDescriptionMux
PERR#H2I/OParity Error. PERR# is used for reporting data parity
--errors during all PCI transactions except a Special Cycle.
The PERR# line is driven two PCI clocks after the data in
which the error was detected. This is one PCI clock after
the PAR that is attached to the data. The minimum duration of PERR# is one PCI clock for each data phase in
which a data parity error is detected. PERR# must be
driven high for one PCI clock before being placed in TRISTATE. A target asserts PERR# on write cycles if it has
claimed the cycle with DEVSEL#. The master asserts
PERR# on read cycles.
This signal is internally connected to a pull-up resistor.
SERR#H1I/OSystem Error. SERR# can be asserted by any agent for
--reporting errors other than PCI parity. When the PFS bit
is enabled in the GX1 module’s PCI Control Function 2
register (Index 41h[5]), SERR# is asserted upon assertion of PERR#.
This signal is internally connected to a pull-up resistor.
REQ1#A5IRequest Lines. REQ[1:0]# indicate to the arbiter that an
REQ0#B5---
agent requires the bus. Each master has its own REQ#
line. REQ# priorities (in order) are:
---
1)VIP
2)IDE Channel 0
3)IDE Channel 1
4)Audio
5)USB
6)External REQ0#
7)External REQ1#.
Each REQ# is internally connected to a pull-up resistor.
GNT1#C6OGrant Lines. GNT[1:0]# indicate to the requesting mas-
GNT0#C5DID0 (Strap)
ter that it has been granted access to the bus. Each master has its own GNT# line. GNT# can be retracted at any
DID1 (Strap)
time a higher REQ# is received or if the master does not
begin a cycle within a minimum period of time (16 PCI
clocks).
Each of these signals is internally connected to a pull-up
resistor.
GNT0# must have a pull-down resistor of 1.5 KΩ, GNT1#
must have a pull-down resistor of 1.5 KΩ.
58AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.8Sub-ISA Interface Signals
Signal NameBall No.TypeDescriptionMux
A[23:0]See
OAddress LinesAD[23:0]
Table 3-3
on page
40
D15See
D14IRDY#
D13TRDY#
Table 3-3
on page
40
I/OData BusSTOP#
D12PA R
D11C/BE3#
D10C/BE2#
D9C/BE1#
D8C/BE0#
D[7:0]AD[31:24]
BHE#E4OByte High Enable. With A0, defines byte accessed for
DEVSEL#
16 bit wide bus cycles.
IOCS1#D10OI/O Chip SelectsGPIO1+TFTD12
N30AB1D+GPIO1
IOCS0#A10GPIO17+TFTDCK
ROMCS#C8OROM or Flash ROM Chip SelectBOOT16 (Strap)
DOCCS#A9ODiskOnChip or NAND Flash Chip SelectGPIO20+TFTD0
N31AB1C+GPIO20
TRDE#D11OTransceiver Data Enable Control. Active low for Sub-
GPIO0
ISA data transfers. The signal timing is as follows:
• In a read cycle, TRDE# has the same timing as RD#.
• In a write cycle, TRDE# is asserted (to active low) at
the time WR# is asserted. It continues being asserted
for one PCI clock cycle after WR# has been negated,
then it is negated.
RD#B8OMemory or I/O Read. Active on any read cycle.CLKSEL0 (Strap)
WR#B9OMemory or I/O Write. Active on any write cycle.---
IOR#D9OI/O Read. Active on any I/O read cycle.DOCR#+GPIO14
IOW#A8OI/O Write. Active on any I/O write cycle.DOCW#+GPIO15
DOCR#D9ODiskOnChip or NAND Flash Read. Active on any mem-
IOR#+GPIO14
ory read cycle to DiskOnChip.
DOCW#A8ODiskOnChip or NAND Flash Write. Active on any mem-
IOW#+GPIO15
ory write cycle to DiskOnChip.
IRQ9AA3IInterrupt 9 Request Input. Active high.
IDE_DATA6
Note: If IRQ9 function is selected but not used, tie
IRQ9 low.
IOCHRDYC9II/O Channel Ready
GPIO19+INTC#
Note: If IOCHRDY function is selected but not used, tie
LDRQ#L28ILPC DMA Request. Encoded DMA request for LPC
GPIO36
interface.
Note: If LDRQ# function is selected but not used, tie
LDRQ# high.
LFRAME#K31OLPC Frame. A low pulse indicates the beginning of a
GPIO37
new LPC cycle or termination of a broken cycle.
LPCPD#K28OLPC Power-Down. Signals the LPC device to prepare for
GPIO38/IRRX2
power shutdown on the LPC interface.
SERIRQJ31I/OSerial IRQ. The interrupt requests are serialized over a
GPIO39
single signal, where each IRQ level is delivered during a
designated time slot.
Note: If SERIRQ function is selected but not used, tie
SERIRQ high.
60AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.10IDE Interface Signals
Signal NameBall No.TypeDescriptionMux
IDE_RST#AA1OIDE Reset. This signal resets all devices attached to the
TFTDCK
IDE interface.
IDE_ADDR2U2OIDE Address Bits. These address bits are used to
IDE_ADDR1AE1TFTD2
access a register or data port in a device on the IDE bus.
TFTD4
IDE_ADDR0AD3TFTD3
IDE_DATA[15:0]See
Table 3-3
on page
40
I/OIDE Data Lines. IDE_DATA[15:0] transfers data to/from
the IDE devices.
The IDE interface is
muxed with the TFT
interface. See Table
3-5 on page 45 for
muxing details.
IDE_IOR0#Y4OIDE I/O Read Channels 0 and 1. IDE_IOR0# is the read
IDE_IOR1#D28OGPIO6+DTR2#/
signal for Channel 0 and IDE_IOR1# is the read signal
for Channel 1. Each signal is asserted at read accesses
to the corresponding IDE port addresses.
IDE_IOW0#AD2OIDE I/O Write Channels 0 and 1. IDE_IOW0# is the
IDE_IOW1#C28OGPIO9+DCD2#+
write signal for Channel 0. IDE_IOW1# is the write signal
for Channel 1. Each signal is asserted at write accesses
to corresponding IDE port addresses.
IDE_CS0#AF2OIDE Chip Selects 0 and 1. These signals are used to
IDE_CS1#P2OTFTDE
select the command block registers in an IDE device.
IDE_IORDY0AD1II/O Ready Channels 0 and 1. When de-asserted, these
IDE_IORDY1B29IGPIO10+DSR2#+
signals extend the transfer cycle of any host register
access if the required device is not ready to respond to
the data transfer request.
TFTD10
BOUT2+SDTEST5#
TFTD9
SDTEST2
TFTD5
TFTD11
SDTEST1
Note: If selected as IDE_IORDY0 or IDE_IORDY1
function(s) but not used, then signal(s) should be
tied high.
IDE_DREQ0AC4IDMA Request Channels 0 and 1. The IDE_DREQ sig-
IDE_DREQ1C31IGPIO8+CTS2#
nals are used to request a DMA transfer from the
SC1200/SC1201 processor. The direction of transfer is
determined by the IDE_IOR/IOW signals.
TFTD8
+SDTEST5
Note: If selected as IDE_DREQ0/ IDE_DREQ1 func-
tion but not used, tie IDE_DREQ0/IDE_DREQ1
low.
IDE_DACK0#AD4ODMA Acknowledge Channels 0 and 1. The
IDE_DACK1#C30OGPIO7+RTS2#
IDE_DACK# signals acknowledge the DREQ request to
initiate DMA transfers.
IRQ14AF1IInterrupt Request Channels 0 and 1. These input sig-
IRQ15AJ8IGPIO11+RI2#
nals are edge-sensitive interrupts that indicate when the
IDE device is requesting a CPU interrupt service.
TFTD0
+SDTEST0
TFTD1
Note: If selected as IRQ14/IRQ15 function but not
used, tie IRQ14/IRQ15 low.
AMD Geode™ SC1200/SC1201 Processor Data Book61
32579B
Signal Definitions
3.4.11Universal Serial Bus (USB) Interface Signals
Signal NameBall No.TypeDescriptionMux
POWER_ENAH1OPower Enable. This signal enables the power to a self-
---
powered USB hub.
OVER_CUR#AF4IOvercurrent. This signal indicates that the USB hub has
---
detected an overcurrent on the USB.
DPOS_PORT1A28I/O
DNEG_PORT1A29I/O
DPOS_PORT2B27I/O
DNEG_PORT2B28I/O
DPOS_PORT3A26I/O
DNEG_PORT3A27I/O
USB Port 1 Data Positive for Port 1.
USB Port 1 Data Negative for Port 1.
USB Port 2 Data Positive for Port 2.
USB Port 2 Data Negative for Port 2.
USB Port 3 Data Positive for Port 3.
USB Port 3 Data Negative for Port 3.
1
1
1
1
1
1
---
---
---
---
---
---
1.A 15 KΩ pull-down resistor is required on all ports (even if unused).
3.4.12Serial Ports (UARTs) Interface Signals
Signal Name Ball No.TypeDescriptionMux
SIN1AG2ISerial Inputs. Receive composite serial data from the
SIN2E28SDTEST3
SIN3AK8IRRX1
communications link (peripheral device, modem or other
data transfer device).
Note: If selected as SIN2 or SIN3 function(s) but not
used, then signal(s) should be tied high.
SOUT1AF3OSerial Outputs. Send composite serial data to the com-
SOUT2D29CLKSEL2 (Strap)
SOUT3C11IRTX
munications link (peripheral device, modem or other data
transfer device). These signals are set active high after a
system reset.
CLKSEL1 (Strap)
RTS2#C30ORequest to Send. When low, indicates to the modem or
other data transfer device that the corresponding UART
is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them
inactive.
CTS2#C31IClear to Send. When low, indicates that the modem or
other data transfer device is ready to exchange data.
Note: If selected as CTS2# function but not used, tie
CTS2# low.
DTR1#/BOUT1AG1OData Terminal Ready Outputs. When low, indicate to
DTR2#/BOUT2D28GPIO6+IDE_IOR1#
the modem or other data transfer device that the UART is
ready to establish a communications link. After a system
reset, these balls provide the DTR# function and set
these signals to inactive high. Loopback operation drive
them inactive.
Baud Outputs. Provide the associated serial channel
baud rate generator output signal if test mode is selected
(i.e., bit 7 of the EXCR1 Register is set).
RI2#AJ8IRing Indicator. When low, indicates to the modem that a
GPIO11+IRQ15
telephone ring signal has been received by the modem.
They are monitored during power-off for wakeup event
detection.
Note: If selected as RI2# function but not used, tie
RI2# high.
DCD2#C28IData Carrier Detected. When low, indicates that the
data transfer device (e.g., modem) is ready to establish a
GPIO9+IDE_IOW1#
+SDTEST2
communications link.
Note: If selected as DCD2# function but not used, tie
DCD2# high.
DSR2#B29IData Set Ready. When low, indicates that the data trans-
fer device (e.g., modem) is ready to establish a communi-
GPIO10+
IDE_IORDY1
cations link.
Note: If selected as DSR2# function but not used, tie
DSR2# low.
3.4.13Parallel Port Interface Signals
Signal NameBall No.TypeDescriptionMux
ACK# B18IAcknowledge. Pulsed low by the printer to indicate that it
has received data from the Parallel Port.
AFD#/DSTRB# D22 OAutomatic Feed. When low, instructs the printer to auto-
matically feed a line after printing each line. This signal is
in TRI-STATE after a 0 is loaded into the corresponding
control register bit. An external 4.7 KΩ pull-up resistor
should be attached to this ball.
Data Strobe (EPP). Active low, used in EPP mode to
denote a data cycle. When the cycle is aborted, DSTRB#
becomes inactive (high).
BUSY/WAIT#B17IBusy. Set high by the printer when it cannot accept
another character.
Wait. In EPP mode, the Parallel Port device uses this
active low signal to extend its access cycle.
ERR#D21IError. Set active low by the printer when it detects an
error.
INIT#B21OInitialize. When low, initializes the printer. This signal is
in TRI-STATE after a 1 is loaded into the corresponding
control register bit. Use an external 4.7 KΩ pull-up resistor.
TFTDE+VOPCK+
FPCICLK
TFTD2+VOPD1+
INTR_O
TFTD3+VOPD2+
F_C/BE1#
TFTD4+VOPD3+
F_C/BE0#
TFTD5+VOPD4+
SMI_O
AMD Geode™ SC1200/SC1201 Processor Data Book63
32579B
Signal Definitions
3.4.13Parallel Port Interface Signals (Continued)
Signal NameBall No.TypeDescriptionMux
PD7A18I/OParallel Port Data. Transfer data to and from the periph-
PD6A20TFTD1+VOPD0+
eral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability.
TFTD13+F_AD7
F_AD6
PD5C19TFTD11+F_AD5
PD4C18TFTD10+F_AD4
PD3C20TFTD9+F_AD3
PD2D20TFTD8+VOPD7+
F_AD2
PD1A21TFTD7+VOPD6+
F_AD1
PD0C21TFTD6+VOPD5+
F_AD0
PED17IPaper End. Set high by the printer when it is out of
TFTD14+F_C/BE2#
paper.
This ball has an internal weak pull-up or pull-down resistor that is programmed by software.
SLCTC17ISelect. Set active high by the printer when the printer is
TFTD15+F_C/BE3#
selected.
SLIN#/ASTRB# B20OSelect Input. When low, selects the printer. This signal
is in TRI-STATE after a 0 is loaded into the corresponding
TFTD16+
F_IRDY#
control register bit. Uses an external 4.7 KΩ pull-up resistor.
Address Strobe (EPP). Active low, used in EPP mode to
denote an address or data cycle. When the cycle is
aborted, ASTRB# becomes inactive (high).
STB#/WRITE#A22OData Strobe. When low, indicates to the printer that valid
data is available at the printer port. This signal is in TRI-
TFTD17+
F_FRAME#
STATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor should be
employed.
Write Strobe. Active low, used in EPP mode to denote
an address or data cycle. When the cycle is aborted,
WRITE# becomes inactive (high).
3.4.14Fast Infrared (IR) Port Interface Signals
Signal Name Ball No.TypeDescriptionMux
IRRX1AK8IIR Receive. Primary input to receive serial data from the
IR transceiver. Monitored during power-off for wakeup
event detection.
Note: If selected as IRRX1 function but not used, tie
IRRX1 high.
IRRX2/GPIO38K28IIR Receive 2. Auxiliary IR receiver input to support a
second transceiver. This input signal can be used when
GPIO38 is selected using PMR[14], and when
AUX_IRRX bit in register IRCR2 of the IR module in
internal SuperI/O is set.
IRTXC11OIR Transmit. IR serial output data.SOUT3
64AMD Geode™ SC1200/SC1201 Processor Data Book
SIN3
LPCPD#
Signal Definitions
32579B
3.4.15AC97 Audio Interface Signals
Signal Name Ball No.TypeDescriptionMux
BIT_CLKU30IAudio Bit Clock. The serial bit clock from the codec.
F_TRDY#
Note: If selected as BIT_CLK function but not used, tie
BIT_CLK low.
SDATA_OUTP29OSerial Data Output. This output transmits audio serial
TFT_PRSNT (Strap)
data to the codec.
SDATA_INU31ISerial Data Input. This input receives serial data from
F_GNT0#
the primary codec.
Note: If selected as SDATA_IN function but not used,
tie SDATA_IN low.
SDATA_IN2AL8ISerial Data Input 2. This input receives serial data from
---
the secondary codec. This signal has wakeup capability.
SYNCP30OSerial Bus Synchronization. This bit is asserted to syn-
CLKSEL3 (Strap)
chronize the transfer of data between the SC1200/
SC1201 processor and the AC97 codec.
AC97_CLKP31OCodec Clock. It is twice the frequency of the Audio Bit
---
Clock.
AC97_RST#U29OCodec Reset. S3 to S5 wakeup is not supported
because AC97_RST# is powered by V
. If wakeup from
IO
F_STOP#
states S3 to S5 are needed, a circuit in the system board
should be used to reset the AC97 codec.
PWRBTN#AH5IPower Button. An input used by the power management
--logic to monitor external system events, most typically a
system on/off button or switch.
The signal has an internal pull-up of 100 KΩ, a Schmitt-
trigger input buffer and programmable debounce protection (F1BAR1+I/O Offset 07h[0]) of at least 16 ms.
ACPI is non-functional and all ACPI outputs are undefined when the power-up sequence does not include
using the power button. SUSP# is an internal signal generated from the ACPI block. Without an ACPI reset,
SUSP# can be permanently asserted. If the USE_SUSP
bit in CCR2 of GX1 module is enabled (Index C2h[7] = 1),
the CPU will stop.
If ACPI functionality is desired, or the situation described
above avoided, the power button must be toggled. This
can be done externally or internally. GPIO63 is internally
connected to PWRBTN#. To toggle the power button with
software, GPIO63 must be programmed as an output
using the normal GPIO programming protocol (see Section 6.4.1.1 "GPIO Support Registers" on page 224).
GPIO63 must be pulsed low for at least 16 ms and not
more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is
asserted and ACPI was active prior to POR#, then ACPI
will remain active after POR#. Therefore, BIOS must
ensure that ACPI is inactive before GPIO63 is pulsed
low.
PWRCNT1AK6OSuspend Power Plane Control 1 and 2. Control signal
PWRCNT2AL7O---
asserted during power management Suspend states.
These signals are open-drain outputs.
THRM#AK4IThermal Event. Active low signal generated by external
---
--hardware indicating that the system temperature is too
high.
66AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
3.4.17GPIO Interface Signals
Signal Name Ball No.TypeDescriptionMux
GPIO0D11I/OGPIO Port 0. Each signal is configured independently as
GPIO1D10IOCS1#+TFTD12
N30AB1D+IOCS1#
GPIO6D28DTR2#/BOUT2+
an input or I/O, with or without static pull-up, and with
either open-drain or totem-pole output type.
A debouncer and an interrupt can be enabled or masked
for each of signals GPIO[00:01] and [06:15] independently.
Note: GPIO12, GPIO13, GPIO16 inputs: If GPIOx func-
GPIO7C30RTS2#+IDE_DACK1#
tion is selected but not used, tie GPIOx low.
TRDE#
IDE_IOR1#+
SDTEST5
+SDTEST0
GPIO8C31CTS2#+IDE_DREQ1
+SDTEST4
GPIO9C28DCD2#+IDE_IOW1#+
SDTEST2
GPIO10B29DSR2#+IDE_IORDY1
+SDTEST1
GPIO11AJ8RI2#+IRQ15
GPIO12N29AB2C
GPIO13M29AB2D
GPIO14D9IOR#+DOCR#
GPIO15A8IOW#+DOCW#
GPIO16V31PC_BEEP+
F_DEVSEL#
GPIO17A10IOCS0#+TFTDCK
GPIO18AG1DTR1#/BOUT1
GPIO19C9INTC#+IOCHRDY
GPIO20A9DOCCS#+TFTD0
N31AB1C+DOCCS#
GPIO32M28I/OGPIO Port 1. Each signal is configured independently as
GPIO33L31LAD1
GPIO34L30LAD2
GPIO35L29LAD3
an input or I/O, with or without static pull-up, and with
either open-drain or totem-pole output type.
A debouncer and an interrupt can be enabled or masked
for each of signals GPIO[32:41] independently.
LAD0
GPIO36L28LDRQ#
GPIO37K31LFRAME#
GPIO38/IRRX2K28LPCPD#
GPIO39J31SERIRQ
GPIO40Y3IDE_DATA8
GPIO41W4IDE_DATA11
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Signal Definitions
3.4.18Debug Monitoring Interface Signals
Signal NameBall No.TypeDescriptionMux
FPCICLKB18OFast-PCI Bus Monitoring Signals. When enabled, this
group of signals provides for monitoring of the internal
F_AD7A18OPD7+TFTD13
Fast-PCI bus for debug purposes. To enable, pull up
FPCI_MON (ball A4).
ACK#+TFTDE+
VOPCK
F_AD6A20OPD6+TFTD1+
VOPD0
F_AD5C19OPD5+TFTD11
F_AD4C18OPD4+TFTD10
F_AD3C20OPD3+TFTD9
F_AD2D20OPD2+TFTD8+
VOPD7
F_AD1A21OPD1+TFTD7+
VOPD6
F_AD0C21OPD0+TFTD6+
VOPD5
F_C/BE3#C17OSLCT+TFTD15
F_C/BE2#D17OPE+TFTD14
F_C/BE1#B17OBUSY/WAIT#+
TFTD3+VOPD2
F_C/BE0#D21OERR#+TFTD4+
VOPD3
F_FRAME#A22OSTB#/WRITE#+
TFTD17
F_IRDY#B20OSLIN#/ASTRB#+
TFTD16
F_STOP#U29OAC97_RST#
F_DEVSEL#V31OGPIO16+
PC_BEEP
F_GNT0#U31OSDATA_IN
F_TRDY#U30OBIT_CLK
INTR_OD22OCPU Core Interrupt. When enabled, this signal provides
for monitoring of the internal GX1 core INTR signal for
AFD#/DSTRB#+
TFTD2+VOPD1
debug purposes. To enable, pull up FPCI_MON (ball A4).
SMI_OB21OSystem Management Interrupt. This is the input to the
GX1 core. When enabled, this signal provides for monitor-
INIT#+TFTD5+
VOPD4+
ing of the internal GX1 core SMI# signal for debug purposes. To enable, pull up FPCI_MON (ball A4).
3.4.19JTAG Interface Signals
Signal NameBall No.TypeDescriptionMux
TCKE31IJTAG Test Clock. This signal has an internal weak pull-up
resistor.
TDIF29IJTAG Test Data Input. This signal has an internal weak
pull-up resistor.
68AMD Geode™ SC1200/SC1201 Processor Data Book
---
---
Signal Definitions
32579B
3.4.19JTAG Interface Signals (Continued)
Signal NameBall No.TypeDescriptionMux
TDOE30OJTAG Test Data Output---
TMSF28IJTAG Test Mode Select. This signal has an internal weak
pull-up resistor.
TRST#E29IJTAG Test Reset. This signal has an internal weak pull-up
resistor.
For normal JTAG operation, this signal should be active at
power-up.
If the JTAG interface is not being used, this signal can be
tied low.
3.4.20Test and Measurement Interface Signals
Signal NameBall No.TypeDescriptionMux
---
---
GXCLKV30OGX Clock. This signal is for internal testing only. For nor-
mal operation either program as FP_VDD_ON or leave
FP_VDD_ON+
TEST3
unconnected.
TEST3V30OInternal Test Signal. This signal is used for internal test-
ing only. For normal operation leave unconnected, unless
FP_VDD_ON+
GXCLK
programmed as FP_VDD_ON.
TEST2AJ1OInternal Test Signals. These signals are used for internal
TEST1AG4OPLL6B
testing only. For normal operation leave unconnected.
PLL5B
TEST0AH3OPLL2B
GTESTF30IGlobal Test. This signal is used for internal testing only.
---
For normal operation this signal should be pulled down
with 1.5 KΩ.
PLL6BAG4I/OPLL6, PLL5 and PLL2 Bypass. These signals are used
PLL5BAJ1I/OTEST2
PLL2BAH3I/OTEST0
for internal testing only and requires additional test modes
to observe the PLLs. These modes are not described in
this specification. For normal operation leave uncon-
TEST1
nected.
SDTEST5D28OMemory Internal Test Signals. These signals are used
for internal testing only. For normal operation, these signals should be programmed as one of their muxed
SDTEST4 C31OGPIO8+CTS2#+
options.
GPIO6+
DTR2#/BOUT2+
IDE_IOR1#
IDE_DREQ1
SDTEST3 E28OSIN2
SDTEST2 C28OGPIO9+DCD2#+
IDE_IOW1#
SDTEST1 B29OGPIO10+DSR2#+
IDE_IORDY1
SDTEST0 C30OGPIO7+RTS2#+
IDE_DACK1#
TDPD30I/OThermal Diode Positive / Negative. These signals are for
TDND31I/O---
internal testing only. For normal operation leave unconnected.
---
AMD Geode™ SC1200/SC1201 Processor Data Book69
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Signal Definitions
3.4.21Power and Ground Connections
1
Signal NameBall No.TypeDescription
AV
AV
V
PLL2
SSPLL2
SSPLL3
C16GNDAnalog PLL2 Ground Connection.
AK3GNDAnalog PLL3 Ground Connection.
A17PWR3.3V PLL2 Analog Power Connection. Low noise power for PLL2 and
PLL5.
V
PLL3
AJ4PWR3.3V PLL3 Analog Power Connection. Low noise power for PLL3,
PLL4, and PLL6.
AV
AV
AV
AV
CCUSB
SSUSB
CCCRT
SSCRT
D27PWR3.3V Analog USB Power Connection. Low noise power for USB.
C27GNDAnalog USB Ground Connection.
A12, C13, D15PWR3.3V Analog CRT DAC Power Connections. Low noise power.
D12PWR1.8V CRT DAC Digital Power Connection. Can be directly connected to
V
on PCB (printed circuit board).
CORE
C12GNDCRT DAC Digital Ground Connection. Can be directly connected to VSS
on PCB.
AV
AV
V
CCTV
SSTV
BAT
D23PWR3.3V Analog TV DAC Power Connection. Low noise power.
B24GNDAnalog TV DAC Ground Connection. Return current.
AL3PWRBattery. Provides battery back-up to the RTC and ACPI registers, when
VSB is lower than the minimum value (see Table 9-3 on page 366). The
ball is connected to the internal logic through a series resistor for UL pro-
tection. If battery backup is not desired, connect V
V
SB
AL5PWR3.3V Standby Power Supply. Provides power to the Real-Time Clock
(RTC) and ACPI circuitry while the main power supply is turned off.
V
SBL
AL6PWR1.8V Standby Power Supply. Provides power to the internal logic while
the main power supply is turned off. This signal requires a 0.1 μF bypass
capacitor to V
V
CORE
See Table 3-3
PWR1.8V Core Processor Power Connections.
on page 40
(Total of 28)
V
IO
See Table 3-3
PWR3.3V I/O Power Connections.
on page 40
(Total of 42)
V
SS
See Table 3-3
GNDGround Connections.
on page 40
(Total of 91)
1.All power sources except V
must be connected, even if the function is not used.
BAT
to VSS.
BAT
. This supply must be present when VSB is present.
SS
70AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block32579B
4.0General Configuration Block
4
The General Configuration block includes registers for:
• Pin Multiplexing and Miscellaneous Configuration
• WATCHDOG Timer
• High-Resolution Timer
• Clock Generators
A selectable interrupt is shared by all these functions.
4.1Configuration Block Addresses
Registers of the General Configuration block are I/O
mapped in a 64-byte address range. These registers are
physically connected to the internal Fast-PCI bus, but do
Table 4-1. General Configuration Block Register Summary
3Eh-3Fh16ROCBA. Configuration Base AddressxxxxhPage 78
Width
(Bits)TypeNameReset ValueReference
not have a register block in PCI configuration space (i.e.,
they do not appear to software as PCI registers).
After system reset, the Base Address register is located at
I/O address 02EAh. This address can be used only once.
Before accessing any PCI registers, the BOOT code must
program this 16-bit register to the I/O base address for the
General Configuration block registers. All subsequent
writes to this address, are ignored until system reset.
Note: Location of the General Configuration Block cannot
be determined by software. See the AMD Geode™
SC1200/SC1201 Processor Specification Update
document.
Reserved bits in the General Configuration block should be
read as written unless otherwise specified.
AMD Geode™ SC1200/SC1201 Processor Data Book71
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General Configuration Block
4.2Pin Multiplexing, Interrupt Selection, and Base Address Registers
The registers described in Table 4-2 are used to determine
general configuration for the SC1200/SC1201 processor.
These registers also indicate which multiplexed signals are
issued via balls from which more than one signal may be
Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers
This register configures pins with multiple functions. See Section 3.1 on page 27 for more information about multiplexing information.
31:30Reserved: Always write 0.
29Test Signals. Selects ball functions.
Ball #0: Internal Test Signals 1: Internal Test Signals
NameAdd’l DependenciesNameAdd’l Dependencies
D28 / AH3PLL2BNoneTEST0None
C28 / AG4PLL6BNoneTEST1None
B29 / AJ1PLL5BNoneTEST2None
AL16 / V30GXCLKSee PMR[23]TEST3PMR[23] = 0
28Test Signals. Selects ball function.
Ball #0: AC97 Signal 1: Internal Test Signal
NameAdd’l DependenciesNameAdd’l Dependencies
AJ4 / E28SIN2NoneSDTEST3See Note.
Note:If this bit is set, PMR[8] and PMR[18] must be set by software.
27FPCI_MON (Fast-PCI Monitoring). Selects Fast-PCI monitoring output signals instead of Parallel Port signals.
Fast-PCI monitoring output signals can be enabled in two ways: by setting this bit to 1 or by strapping FPCI_MON (ball A4)
high. (The strapped value can be read back at MCR[30].) Listed below is how these two options work together and the signals that are enabled (enabling overrides add’l dependencies except FPCI_MON = 1). Note that the FPCI monitoring signals
that are muxed with Audio signals are not enabled via this bit. They are only enabled using the strap option.
PMR[27] FPCI_MON
0 0Disable all Fast-PCI monitoring signals
0 1Enable all Fast-PCI monitoring signals
1 0Enable Fast-PCI monitoring signals muxed with Parallel Port signals only
1 1Enable all Fast-PCI monitoring signals
31DID0 (Ball C5) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in
conjunction with bit 29.
30FPCI_MON (Ball A4) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset.
Indicates if Fast-PCI monitoring output signals (instead of Parallel Port and some audio signals) are enabled. The state of
this bit along with PMR[27] control the Fast-PCI monitoring function. See PMR[27] definition.
29DID1 (Ball C6) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in
conjunction with bit 31.
28:20Reserved.
NameAdd’l DependenciesNameAdd’l Dependencies
F_DEVSEL#FPCI_MON = 1F_DEVSEL#FPCI_MON = 1
76AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block
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Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
BitDescription
19:18PLL1 and TV Encoder Clock Frequency. PLL1 supplies the clock for the TV Encoder.
00: TV Encoder clock is 27 MHz from crystal oscillator. PLL1 is powered down.
01: TV Encoder clock is PLL1 output. PLL1 output is 27 MHz.
10: TV Encoder clock is PLL1 output. PLL1 output is 24.545454 MHz.
11: TV Encoder clock is PLL1 output. PLL1 output is 29.5 MHz.
17HSYNC Timing. HSYNC timing control for TFT.
0: HSYNC timing suited for CRT.
1: HSYNC timing suited for TFT.
16Delay HSYNC. HSYNC delay by two TFT clock cycles.
0: There is no delay on HSYNC.
1: HYSNC is delayed twice by rising edge of TFT clock. Enables delay between VSYNC and HSYNC suited for TFT dis-
play.
15Reserved. Write as read.
14IBUS16 (Invert BUS16). This bit inverts the meaning of MCR[3] (bit 3 of this register).
0: BUS16 is as described for MCR[3].
1: BUS16 meaning is inverted: if MCR[3] = 0, ROMCS# access is 16 bits wide; if MCR[3] = 1, ROMCS# access is 8 bits
wide.
13Reserved. Must be set to 0.
12IO1ZWS (Enable ZWS# for IOCS1# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS1# access.
0: ZWS# is not active for IOCS1# access.
1: ZWS# is active for IOCS1# access.
11IO0ZWS (Enable ZWS# for IOCS0# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS0# access.
0: ZWS# is not active for IOCS0# access.
1: ZWS# is active for IOCS0# access.
10DOCZWS (Enable ZWS# for DOCCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
DOCCS# access.
0: ZWS# is not active for DOCCS# access.
1: ZWS# is active for DOCCS# access.
9ROMZWS (Enable ZWS# for ROMCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
ROMCS# access.
0: ZWS# is not active for ROMCS# access.
1: ZWS# is active for ROMCS# access.
8IO1_16 (Enable 16-Bit Wide IOCS1# Access). This bit enables the16-line access to IOCS1# in the Sub-ISA interface.
0: 8-bit wide IOCS1# access is used.
1: 16-bit wide IOCS1# access is used.
7IO0_16 (Enable 16-Bit Wide IOCS0# Access). This bit enables the 16-line access to IOCS0# in the Sub-ISA interface.
0: 8-bit wide IOCS0# access is used.
1: 16-bit wide IOCS0# access is used.
6DOC16 (Enable 16-Bit Wide DOCCS# Access). This bit enables the 16-line access to DOCCS# in the Sub-ISA interface.
0: 8-bit wide DOCCS# access is used.
1: 16-bit wide DOCCS# access is used.
5Reserved. Write as read.
4IRTXEN (Infrared Transmitter Enable). This bit enables drive of Infrared transmitter output.
0: IRTX+SOUT3 line (ball C11) is HiZ.
1: IRTX+SOUT3 line (ball C11) is enabled.
AMD Geode™ SC1200/SC1201 Processor Data Book77
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General Configuration Block
Table 4-2. Pin Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
BitDescription
3BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit reports the status of the BOOT16 strap (ball C8). If the BOOT16
strap is pulled high, at reset 16-bit access to ROM in the Sub-ISA interface is enabled. MCR[14] = 1 inverts the meaning of
this register.
0: 8-bit wide ROM.
1: 16-bit wide ROM.
2:1Reserved. Write as read.
0SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis-
ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI slave.
SDBE[1:0]
00: Read and Write disconnect on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register (Index
41h).
01: Write disconnects on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register. Read discon-
nects on cache line boundary of 16 bytes.
1x: Read and Write disconnect on cache line boundary of 16 bytes.
This bit is reset to 1.
All PCI bus masters (including SC1200/SC1201 processor’s on-chip PCI bus masters, e.g., the USB Controller) must be disabled while modifying this bit. When accessing this register while any PCI bus master is enabled, use read-modify-write to
ensure these bit contents are unchanged.
This register selects the IRQ signal of the combined WATCHDOG and High-Resolution timer interrupt. This interrupt is shareable with
other interrupt sources.
7:4Reserved. Write as read.
3:0CBIRQ. Configuration Block Interrupt.
0000: Disable0100: IRQ41000: IRQ8#1100: IRQ12
0001: IRQ10101: IRQ51001: IRQ91101: Reserved
0010: Reserved0110: IRQ61010: IRQ101110: IRQ14
0011: IRQ30111: IRQ71011: IRQ111111: IRQ15
Offset 39h-3BhReserved - RSVD
Offset 3ChDevice Identification Number Register - ID (RO)Reset Value: xxh
This register identifies the device. SC1200 = 04h. SC1201 = 05h.
This register identifies the device revision. See the AMD Geode™ SC1200/SC1201 Processor Specification Update document for value.
Offset 3Eh-3FhConfiguration Base Address Register - CBA (RO)Reset Value: xxh
This register sets the base address of the Configuration block.
15:6Configuration Base Address. These bits are the high bits of the Configuration Base Address.
5:0Configuration Base Address. These bits are the low bits of the Configuration Base Address. These bits are set to 0.
78AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block
4.3WATCHDOG
The SC1200/SC1201 processor includes a WATCHDOG
function to serve as a fail-safe mechanism in case the system becomes hung. When triggered, the WATCHDOG
mechanism returns the system to a known state by generating an interrupt, an SMI, or a system reset (depending on
configuration).
4.3.1Functional Description
WATCHDOG is enabled when the WATCHDOG Timeout
(WDTO) register (Offset 00h) is set to a non-zero value.
The WATCHDOG timer starts with this value and counts
down until either the count reaches 0, or a trigger event
restarts the count (with the WDTO register value).
The WATCHDOG timer is restarted in any of the following
cases:
• The WDTO register is set with a non-zero value.
• The WATCHDOG timer reaches 0 and the WATCHDOG
Overflow bit, WDOVF (Offset 04h[0]), is 0.
The WATCHDOG function is disabled in any of the following cases:
• System reset occurs.
• The WDTO register is set to 0.
• The WDOVF bit is already 1 when the timer reaches 0.
4.3.1.1WATCHDOG Timer
The WATCHDOG timer is a 16-bit down counter. Its input
clock is a 32 KHz clock divided by a predefined value (see
WDPRES field, Offset 02h[3:0]). The 32 KHz input clock is
enabled when either:
32579B
• The GX1 module’s internal SUSPA# signal is 1.
or
• The GX1 module’s internal SUSPA# signal is 0 and the
WD32KPD bit (Offset 02h[8]) is 0.
The 32 KHz input clock is disabled, when:
• The GX1 module’s internal SUSPA# signal is 0 and the
WD32KPD bit is 1.
For more information about signal SUSPA#, refer to the
AMD Geode™ GX1 Processor Data Book.
When the WATCHDOG timer reaches 0:
• If the WDOVF bit in the WDSTS register (Offset 04h[0])
is 0, an interrupt, an SMI or a system reset is generated,
depending on the value of the WDTYPE1 field in the
WDCNFG register (Offset 02h[5:4]).
• If the WDOVF bit in the WDSTS register is already 1
when the WATCHDOG timer reaches 0, an interrupt, an
SMI or a system reset is generated according to the
WDTYPE2 field (Offset 02h[7:6]), and the timer is
disabled. The WATCHDOG timer is re-enabled when a
non-zero value is written to the WDTO register (Offset
00h).
The interrupt or SMI is de-asserted when the WDOVF bit is
set to 0. The reset generated by the WATCHDOG function
is used to trigger a system reset via the Core Logic module. The value of the WDOVF bit, the WDTYPE1 field, and
the WDTYPE2 field are not affected by a system reset
(except when generated by power-on reset).
The SC1200/SC1201 processor also allows no action to be
taken when the timer reaches 0 (according to WDTYPE1
field and WDTYPE2 field). In this case only the WDOVF bit
is set to 1.
Internal Fast-PCI Bus
SUSPA#
32 KHz
POR#
WATCHDOG
WDPRES
WDTO
TimerWDOVF
WDTYPE1 or
WDTYPE2
Reset IRQ SMI
Figure 4-1. WATCHDOG Block Diagram
AMD Geode™ SC1200/SC1201 Processor Data Book79
32579B
General Configuration Block
WATCHDOG Interrupt
The WATCHDOG interrupt (if configured and enabled) is
4.3.2WATCHDOG Registers
Table 4-3 describes the WATCHDOG registers.
routed to an IRQ signal. The IRQ signal is programmable
via the INTSEL register (Offset 38h, described in Table 4-2
"Pin Multiplexing, Interrupt Selection, and Base Address
Registers" on page 72). The WATCHDOG interrupt is a
shareable, active low, level interrupt.
WATCHDOG SMI
The WATCHDOG SMI is recognized by the Core Logic
module as internal input signal EXT_SMI0#. To use the
WATCHDOG SMI, Core Logic registers must be configured
appropriately.
4.3.2.1Usage Hints
• SMM code should set bit 8 of the WDCNFG register to 1
when entering ACPI C3 state, if the WATCHDOG timer
is to be suspended. If this is not done, the WATCHDOG
timer is functional during C3 state.
• SMM code should set bit 8 of the WDCNFG register to
1, when entering ACPI S1 and S2 states if the
WATCHDOG timer is to be suspended. If this is not
done, the WATCHDOG timer is functional during S1 and
S2 states.
This register selects the signal to be generated when the timer reaches 0, whether or not to disable the 32 KHz input clock during low
power states, and the prescaler value of the clock input.
15:9Reserved. Write as read.
8WD32KPD (WATCHDOG 32 KHz Power Down).
0: 32 KHz clock is enabled.
1: 32 KHz clock is disabled, when the GX1 module asserts its internal SUSPA# signal.
This bit is cleared to 0, when POR# is asserted or when the GX1 module de-asserts its internal SUSPA# signal (i.e., on
SUSPA# rising edge). See Section 4.3.2.1 "Usage Hints" on page 80.
7:6WDTYPE2 (WATCHDOG Event Type 2).
00: No action
01: Interrupt
10: SMI
11: System reset
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.
5:4WDTYPE1 (WATCHDOG Event Type 1).
00: No action
01: Interrupt
10: SMI
11: System reset
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.
Offset 04h WATCHDOG Status Register - WDSTS (R/WC)Reset Value: 00h
This register contains WATCHDOG status information.
7:4Reserved. Write as read.
3WDRST (WATCHDOG Reset Asserted). (Read Only) This bit is set to 1 when WATCHDOG Reset is asserted. It is set to
0 when POR# is asserted, or when the WDOVF bit is set to 0.
2WDSMI (WATCHDOG SMI Asserted). (Read Only) This bit is set to 1 when WATCHDOG SMI is asserted. It is set to 0
when POR# is asserted, or when the WDOVF bit is set to 0.
1WDINT (WATCHDOG Interrupt Asserted). (Read Only) This bit is set to 1 when the WATCHDOG Interrupt is asserted. It
is set to 0 when POR# is asserted, or when the WDOVF bit is set to 0.
0WDOVF (WATCHDOG Overflow). This bit is set to 1 when the WATCHDOG Timer reaches 0. It is set to 0 when POR# is
asserted, or when a 1 is written to this bit by software. Other system reset sources do not affect this bit.
Offset 05h-07hReserved - RSVD
4.4High-Resolution Timer
The SC1200/SC1201 processor provides an accurate time
value that can be used as a time stamp by system software. This time is called the High-Resolution Timer. The
length of the timer value can be extended via software. It is
normally enabled while the system is in the C0 and C1
states. Optionally, software can be programmed to enable
use of the High-Resolution Timer during C3 state and/or
S1 state as well. In all other power states the High-Resolution Timer is disabled.
4.4.1Functional Description
The High-Resolution Timer is a 32-bit free-running countup timer that uses the oscillator clock or the oscillator clock
divided by 27. Bit TMCLKSEL of the TMCNFG register
(Offset 0Dh[1]) can be set via software to determine which
clock should be used for the High-Resolution Timer.
When the most significant bit (bit 31) of the timer changes
from 1 to 0, bit TMSTS of the TMSTS register (Offset
0Ch[0]) is set to 1. When both bit TMSTS and bit TMEN
(Offset 0Dh[0]) are 1, an interrupt is asserted. Otherwise,
the interrupt is de-asserted. This interrupt enables software
emulation of a larger timer.
The High-Resolution Timer interrupt is routed to an IRQ
signal. The IRQ signal is programmable via the INTSEL
register (Offset 38h). For more information about this register, see section Section 4.2 "Pin Multiplexing, Interrupt
Selection, and Base Address Registers" on page 72.
System software uses the read-only TMVALUE register
(Offset 08h[31:0]) to read the current value of the timer.
The TMVALUE register has no default value.
The input clock (derived from the 27 MHz crystal oscillator)
is enabled when:
• The GX1 module’s internal SUSPA# signal is 1.
or
• The GX1 module’s internal SUSPA# signal is 0 and bit
TM27MPD (Offset 0Dh[2]) is 0.
The input clock is disabled, when the GX1 module’s internal SUSPA# signal is 0 and the TM27MPD bit is 1.
For more information about signal SUSPA# see Section
4.4.2.1 "Usage Hints" on page 81 and the AMD Geode™
GX1 Processor Data Book.
The High-Resolution Timer function resides on the internal
Fast-PCI bus and its registers are in General Configuration
Block address space. Only one complete register should
be accessed at-a-time (e.g., DWORD access should be
used for DWORD wide registers and byte access should be
used for byte-wide registers).
4.4.2High-Resolution Timer Registers
Table 4-4 on page 82 describes the registers for the HighResolution Timer (TIMER).
4.4.2.1Usage Hints
• SMM code should set bit 2 of the TMCNFG register to 1
when entering ACPI C3 state if the High-Resolution
Timer should be disabled. If this is not done, the HighResolution Timer is functional during C3 state.
• SMM code should set bit 2 of the TMCNFG register to 1
when entering ACPI S1 state if the High-Resolution
Timer should be disabled. If this is not done, the HighResolution Timer is functional during S1 state.
AMD Geode™ SC1200/SC1201 Processor Data Book81
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General Configuration Block
Table 4-4. High-Resolution Timer Registers
BitDescription
Offset 08h-0BhTIMER Value Register - TMVALUE (RO) Reset Value: xxxxxxxxh
This register contains the current value of the High-Resolution Timer.
This register enables the High-Resolution Timer interrupt; selects the Timer clock; and disables the 27 MHz internal clock during low
power states.
7:3Reserved.
2TM27MPD (TIMER 27 MHz Power Down). This bit is cleared to 0 when POR# is asserted or when the GX1 module de-
asserts its internal SUSPA# signal (i.e., on SUSPA# rising edge). See Section 4.4.2.1 "Usage Hints" on page 81.
0: 27 MHz input clock is enabled.
1: 27 MHz input clock is disabled when the GX1 module asserts its internal SUSPA# signal.
1TMCLKSEL (TIMER Clock Select).
0: Count-up timer uses the oscillator clock divided by 27.
1: Count-up timer uses the oscillator clock, 27 MHz clock.
0TMEN (TIMER Interrupt Enable).
0: High-Resolution Timer interrupt is disabled.
1: High-Resolution Timer interrupt is enabled.
Offset 0Eh-0FhReserved - RSVD
82AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block
4.5Clock Generators and PLLs
This section describes the registers for the clocks required
by the GX1 module, Core Logic module, and the Video
Processor, and how these clocks are generated. See Figure 4-2 for a clock generation diagram.
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The clock generators are based on 32.768 KHz and 27.000
MHz crystal oscillators. The 32.768 KHz crystal oscillator is
described in Section 5.5.2 "RTC Clock Generation" on
page 105 (functional description of the RTC).
32.768 KHz
Crystal
Oscillator
27 MHz
Crystal
Oscillator
32.768 KHz
Shutdown
Shutdown
Shutdown
Shutdown
Shutdown
DISABLE
Shutdown
(ACPI)
PLL4
48 MHz
24.576 MHz
PLL6
57.273 MHz
CLK
PLL2
25-135 MHz
PLL5
66.67 MHz
Divide
PLL3
by 2
Divide
by 4
48 MHz
66 MHz
33 MHz
Real-Time Clock (RTC)
USB Clock (48 MHz)
and I/O Block Clock
DISABLE
AC97_CLK
(24.576 MHz)
High-Resolution Timer Clock
ACPI Clock (14.318 MHz)
CLK27M Ball
Dot Clock
Internal Fast-PCI Clock
External PCI Clock
(33.3 MHz)
DISABLE
To PA D
Core Clock
SDRAM Clock
Note: V
powers PLL2 and PLL5. V
PLL2
Shutdown
(ACPI)
ADL
100-333 MHz
Divider
powers PLL3, PLL4, and PLL6.
PLL3
Figure 4-2. Clock Generation Block Diagram
AMD Geode™ SC1200/SC1201 Processor Data Book83
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4.5.127 MHz Crystal Oscillator
The internal oscillator employs an external crystal connected to the on-chip amplifier. The on-chip amplifier is
accessible on the X27I input and X27O output signals. See
Figure 4-3 for the recommended external circuit and Table
4-5 for a list of the circuit components.
Choose C1 and C2 capacitors to match the crystal’s load
capacitance. The load capacitance CL “seen” by crystal Y
is comprised of C
in series with C2 and in parallel with the
1
parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and
socket (if any), and can vary from 0 to 10 pF. The rule of
thumb in choosing these capacitors is:
= (C1 * C2) / (C1 + C2) + C
C
L
PARASITIC
Example 1:
Crystal CL = 10 pF, C
PARASITIC
= 8.2 pF
C1 = 3.6 pF, C2 = 3.6 pF
Example 2:
Crystal C
= 20 pF, C
L
PARASITIC
= 8 pF
C1 = 24 pF, C2 = 24 pF
Table 4-5. Crystal Oscillator Circuit Components
General Configuration Block
To other
modules
Internal
X27I
R
1
R
2
C
Y
1
X27O
C
2
External
Figure 4-3. Recommended Oscillator External
Circuitry
ComponentParametersValuesTolerance
CrystalResonance Frequency27.00 MHz Parallel mode50 PPM or better
TypeAT-cut or BT-cut
Serial Resistance40 ΩMax
Shunt Capacitance7 pFMax
Load Capacitance, C
L
10-20 pF
Temperature CoefficientUser-defined
Resistor R
Resistor R
Capacitor C
Capacitor C
1
1
2
1
2
Resistance20 MΩ5%
Resistance100 Ω5%
1
Capacitance3-24 pF5%
1
Capacitance3-24 pF5%
1.The value of these components is recommended. It should be tuned according to crystal and board parameters.
84AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block
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4.5.2GX1 Module Core Clock
The core clock is generated by an Analog Delay Loop
(ADL) clock generator from the internal Fast-PCI clock. The
clock can be any whole number multiple of the input clock
between 4 and 10. Possible values are listed in Table 4-6.
At power-on reset, the core clock multiplier value is set
according to the value of four strapped balls - CLKSEL[3:0]
(balls P30, D29, AF3, B8). These balls also select the clock
which is used as input to the multiplier, as shown in Table
4-7.
4.5.3Internal Fast-PCI Clock
The internal Fast-PCI clock can be configured to 33, 48, or
66 MHz via strap options on the CLKSEL1 and CLKSEL0
balls. These can be read in the internal Fast-PCI Clock field
in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See
Table 4-8 on page 87 details on the CCFC register.)
Table 4-7. Strapped Core Clock Frequency
Internal Fast-PCI Clock
CLKSEL[3:0]
Straps
(GCB+I/O Offset 1Eh[9:8])
Freq. (MHz)
Multiply By
Table 4-6. Core Clock Frequency
ADL
Multiplier
Val ue
4133.3192266.7
5166.7240---
6200288---
7233.3------
8266.7------
9---------
10---------
Default ADL Multiplier
(GCB+I/O Offset 1Eh[3:0])
Internal Fast-PCI Clock Freq. (MHz)
33.334866.67
Multiplier Value
Maximum Core
Clock Freq. (MHz)
011133.3340100133
101150101167
111160110200
000070111233
010081000266
100091001Reserved
1100101010Reserved
00014840100192
010150101240
100160110288
11017 0111Reserved
011066.6740100266
10105 0101Reserved
Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page
441.
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General Configuration Block
4.5.4SuperI/O Clocks
The SuperI/O module requires a 48 MHz input for Fast
infrared (FIR), UART, and other functions. This clock is supplied by PLL4 using a multiplier value of 576/(108x3) to
generate 48 MHz.
4.5.5Core Logic Module Clocks
The Core Logic module requires the following clock
sources:
Real-Time Clock (RTC)
RTC requires a 32.768 KHz clock which is supplied directly
from an internal low-power crystal oscillator. This oscillator
uses battery power and has very low current consumption.
USB
The USB requires a 48 MHz input which is supplied by
PLL4. The required total frequency accuracy and slow jitter
for USB is 500 PPM; edge to edge jitter is ±1.2%.
ACPI
The ACPI logic block uses a 14.32 MHz clock supplied by
PLL6. PLL6 creates this clock from the 32.768 KHz clock,
with a multiplier value of 6992/4 to output a 57.278 MHz
clock that is divided by 4.
External PCI
The PCI Interface uses a 33.3 MHz clock that is created by
PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to
output a 66.67 MHz clock. PLL5 has a frequency accuracy
of ± 0.1%.
AC97
The SC1200/SC1201 processor generates the 24.576
MHz clock required by the audio codec. Therefore, no crystal need be included for the audio codec on the system
board.
PLL3 uses the crystal oscillator clock, to generate a 24.576
MHz clock. This clock is driven on the AC97_CLK ball. The
accuracy of the clock supplied by the SC1200/SC1201 processor is 50 PPM.
4.5.6Video Processor Clocks
The Video processor requires the following clock sources:
Dot
The Dot clock is generated by PLL2. It is supplied to the
Display Controller in the GX1 module (DCLK) that creates
the pixel information, and is returned to the Graphics block
(PCLK) with this information. PLL2 uses the 27 MHz clock
to generate the Dot clock.
Video
The Video clock source depends on the source of the video
data.
• If the video data is coming from the GX1 module
(Capture Video mode), the video clock is generated by
the Display Controller.
• If the video data is coming directly from the VIP block
(Direct Video mode), the Video Clock is generated by
the VIP block.
86AMD Geode™ SC1200/SC1201 Processor Data Book
General Configuration Block
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4.5.7Clock Registers
The clock generator and PLL registers are described in Table 4-8.
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock
multiplied by this value.
7:4Reserved.
3:0MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It
Offset 11hReserved - RSVD
Offset 12hPLL Power Control Register - PPCR (R/W) Reset Value: 2Fh
Offset 1Eh-1FhCore Clock Frequency Control Register - CCFC (R/W) Reset Value: Strapped Value
This register controls the configuration of the core clock multiplier and the reference clocks.
15:14Reserved.
13Reserved. Must be set to 0.
12Reserved. Must be set to 0.
11:10Reserved.
9:8FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module
that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0].
00: 33.3 MHz
01: 48 MHz
10: 66.7 MHz
11: 33.3 MHz
7:4Reserved.
3:0MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock
Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is different from the multiplier indicated in the MCCM register.
0100: Multiply by 4
0101: Multiply by 5
0110: Multiply by 6
0111: Multiply by 7
1000: Multiply by 8
1001: Multiply by 9
1010: Multiply by 10
Other: Reserved
88AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module32579B
5.0SuperI/O Module
5
The SuperI/O (SIO) module is a PC98 and ACPI compliant
SIO that offers a single-cell solution to the most commonly
used ISA peripherals.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
Serial
Interface
Serial Port 1
System Wakeup
Control
Serial
Interface
Serial Port 2
Infrared /Serial
Interface
IR Comunication
Port/Serial Port 3
ACCESS.bus 1
Outstanding Features
• Full compatibility with ACPI Revision 1.0 requirements.
• System Wakeup Control powered by V
power-up request and a PME (power management
event) in response to SDATA_IN2 (an audio codec),
IRRX1 (a pre-programmed CEIR), or a RI2# (serial port
ring indicate) event.
• Advanced RTC, Y2K compliant.
V
Real-Time Clock
ACCESS.bus 2
BAT
V
SB
IEEE 1284
Parallel Por t
, generates
SB
ISA
Interface
Host Interface
Wakeup
Events
AMD Geode™ SC1200/SC1201 Processor Data Book89
AB1DAB1C
Figure 5-1. SIO Block Diagram
AB2C
AB2DPWUREQ
Parallel Por t
Interface
5.1Features
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SuperI/O Module
PC98 and ACPI Compliant
• PnP Configuration Register structure
• Flexible resource allocation for all logical devices:
• Enhanced Parallel Port (EPP) compatible with version
EPP 1.9 and IEEE 1284 compliant
• EPP support for version EPP 1.7 of the Xircom specification
• EPP support as mode 4 of the Extended Capabilities
Por t (EC P)
• IEEE 1284 compliant ECP, including level 2
• Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
• PCI bus utilization reduction by supporting a demand
DMA mode mechanism and a DMA fairness mechanism
• Protection circuit that prevents damage to the parallel
port when a printer connected to it powers up or is operated at high voltages, even if the device is in powerdown
• Output buffers that can sink and source 14 mA
Serial Port 1
• 16550A compatible (SIN1, SOUT1, DTR1#/BOUT1
signals only)
Serial Port 2
• 16550A compatible
Serial Port 3 / Infrared (IR) Communication Port
• Serial Port 3
— SIN and SOUT signals only
— Data rate of up to 1.5 Mbps
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— DMA support
• IR Communication Port
— IrDA 1.1 and 1.0 compatible
— Data rate of up to 115.2 Kbps (HP-SIR)
— Data rate of 1.152 Mbps (MIR)
— Data rate of 4.0 Mbps (FIR)
— Selectable internal or external modulation/demodula-
tion (ASK-IR and DASK-IR options of SHARP-IR)
— Consumer-IR (TV-Remote) mode
— Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
— DMA support
System Wakeup Control (SWC)
• Power-up request upon detection of RI2#, CEIR, or
SDATA_IN2 activity:
— Optional routing of power-up request on IRQ line
• Pre-programmed CEIR address in a pre-selected
standard (any NEC, RCA or RC-5)
• Powered by V
SB
• Battery-backed wakeup setup
• Power-fail recovery support
Real-Time Clock
• A modifiable address that is referenced by a 16-bit
programmable register
• DS1287, MC146818 and PC87911 compatibility
• 242 bytes of battery backed up CMOS RAM in two
banks
• Selective lock mechanisms for the CMOS RAM
• Battery backed up century calendar in days, day of the
week, date of month, months, years and century, with
automatic leap-year adjustment
• Battery backed-up time of day in seconds, minutes and
hours that allows a 12 or 24 hour format and adjustments for daylight savings time
• BCD or binary format for time keeping
• Three different maskable interrupt flags:
— Periodic interrupts - At intervals from 122 msec to
500 msec
— Time-of-Month alarm - At intervals from once per
second to once per month
— Update Ended Interrupt - Once per second upon
completion of update
• Separate battery pin, 3.0V operation that includes an
internal UL protection resistor
• 7 µA typical power consumption during power down
• Double-buffer time registers
• Y2K Compliant
Clock Sources
• 48 MHz clock input
• On-chip low frequency clock generator for wakeup
• 32.768 KHz crystal with an internal frequency multiplier
to generate all required internal frequencies
90AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
5.2Module Architecture
The SIO module comprises a collection of generic functional blocks. Each functional block is described in detail
later in this chapter. The beginning of this chapter
describes the SIO structure and provides all device specific
information, including special implementation of generic
blocks, system interface and device configuration.
The SIO module is based on eight logical devices, the host
interface, and a central configuration register set, all built
around a central, internal 8-bit bus.
The host interface serves as a bridge between the external
ISA interface and the internal bus. It supports 8-bit I/O
read, 8-bit I/O write and 8-bit DMA transactions, as defined
in Personal Computer Bus Standard P996.
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The central configuration register set supports ACPI compliant PnP configuration. The configuration registers are
structured as a subset of the Plug and Play Standard Registers, defined in Appendix A of the Plug and Play ISASpecification Version 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O
address space, DMA channels and IRQ lines) are configured in, and managed by, the central configuration register
set. In addition, some function-specific parameters are configurable through this unit and distributed to the functional
blocks through special control signals.
The source of the device internal clocks is the 48 MHz
clock signal or through the 32.768 KHz crystal with an
internal frequency multiplier. RTC operates on a 32 KHz
clock.
This section describes the structure of the configuration
register file, and the method of accessing the configuration
registers.
5.3.1Index-Data Register Pair
The SIO configuration access is performed via an IndexData register pair, using only two system I/O byte locations.
The base address of this register pair is determined
according to the state of the IO_SIOCFG_IN bit field of the
Core Logic module (F5BAR0+I/O Offset 00h[26:25]). Table
5-1 shows the selected base addresses as a function of the
IO_SIOCFG_IN bit field.
Table 5-1. SIO Configuration Options
I/O Address
IO_SIOCFG_IN
Settings
00--SIO disabled
01--Configuration
10002Eh002FhBase address 1
11015Ch015DhBase address 2
The Index Register is an 8-bit R/W register located at the
selected base address (Base+0). It is used as a pointer to
the configuration register file, and holds the index of the
configuration register that is currently accessible via the
Data Register. Reading the Index Register returns the last
value written to it (or the default of 00h after reset).
The Data Register is an 8-bit virtual register, used as a
data path to any configuration register. Accessing the data
register results with physically accessing the configuration
register that is currently pointed by the Index Register.
5.3.2Banked Logical Device Registers
Each functional block is associated with a Logical Device
Number (LDN). The configuration registers are grouped
into banks, where each bank holds the standard configuration registers of the corresponding logical device. Table 5-2
shows the LDNs of the device functional blocks.
Index
Register
Data
Register
Description
access disabled
selected
selected
Table 5-2. LDN Assignments
LDNFunctional BlockReference
00hReal-Time Clock (RTC)Page 98
01hSystem Wakeup Control (SWC)Page 100
02hInfrared Communication Port
(IRCP) or Serial Port 3 (SP3)
03hSerial Port 1 (SP1)Page 102
05hACCESS.bus 1 (ACB1)Page 103
06hACCESS.bus 2 (ACB2)
07hParallel Port (PP)Page 104
08hSerial Port 2 (SP2)Page 102
Figure 5-3 shows the structure of the standard PnP configuration register file. The SIO Control And Configuration
registers are not banked and are accessed by the IndexData register pair only (as described above). However, the
Logical Device Control and Configuration registers are
duplicated over eight banks for eight logical devices. Therefore, accessing a specific register in a specific bank is performed by two-dimensional indexing, where the LDN
register selects the bank (or logical device), and the Index
register selects the register within the bank. Accessing the
Data register while the Index register holds a value of 30h
or higher results in a physical access to the Logical Device
Configuration registers currently pointed to by the Index
register, within the logical device bank currently selected by
the LDN register.
07h
20h
2Fh
30h
60h
63h
70h
71h
74h
75h
F0h
FEh
Logical Device Number Register
SIO Configuration Registers
Logical Device Control Register
Standard Logical Device
Standard Registers
Special (Vendor-defined)
Logical Device
Configuration Registers
Page 101
Bank
Select
Banks
(One per Logical Device)
Figure 5-3. Standard Configuration Register File
Structure
92AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
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Write accesses to unimplemented registers (i.e., accessing
the Data register while the Index register points to a nonexisting register or the LDN is 07h or higher than 08h), are
ignored and a read returns 00h on all addresses except for
74h and 75h (DMA configuration registers) which returns
04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.
5.3.3Default Configuration Setup
The device has four reset types:
Software Reset
This reset is generated by bit 1 of the SIOCF1 register,
which resets all logical devices. A software reset also
resets most bits in the SIO Configuration and Control registers (see Section 5.4.1 on page 97 for the bits not affected).
This reset does not affect register bits that are locked for
write access.
Hardware Reset
This reset is activated by the system reset signal. This
resets all logical devices, with the exception of the RTC and
the SWC, and all SIO Configuration and Control registers,
with the exception of the SIOCF2 register. It also resets all
SuperI/O control and configuration registers, except for
those that are battery-backed.
Power-Up Reset
V
PP
This reset is activated when either VSB or V
on after both have been off. VPP is an internal voltage
which is a combination of V
and V
SB
. VPP is taken from
BAT
VSB if VSB is greater than the minimum (Min) value defined
in Section 9.1.4 "Operating Conditions" on page 366; otherwise, V
is used as the VPP source. This reset resets
BAT
all registers whose values are retained by V
VSB Power-Up Reset
This is an internally generated reset that resets the SWC,
excluding those SWC registers whose values are retained
. This reset is activated after VSB is powered up.
by V
PP
BAT
PP.
is powered
The SIO module wakes up with the default setup, as follows:
• When a hardware reset occurs:
— The configuration base address is 2Eh, 15Ch or
None, according to the IO_SIOCFG_IN bit values, as
shown in Table 5-1 on page 92.
— All Logical devices are disabled, with the exception of
the RTC and the SWC, which remains functional but
whose registers cannot be accessed.
• When either a hardware or a software reset occurs:
— The legacy devices are assigned with their legacy
system resource allocation.
— The AMD proprietary functions are not assigned with
any default resources and the default values of their
base addresses are all 00h.
5.3.4Address Decoding
A full 16-bit address decoding is applied when accessing
the configuration I/O space, as well as the registers of the
functional blocks. However, the number of configurable bits in
the base address registers vary for each device.
The lower 1, 2, 3 or 4 address bits are decoded within the
functional block to determine the offset of the accessed
register, within the device’s I/O range of 2, 4, 8 or 16 bytes,
respectively. The rest of the bits are matched with the base
address register to decode the entire I/O range allocated to
the device. Therefore the lower bits of the base address
register are forced to 0 (RO), and the base address is
forced to be 2, 4, 8 or 16 byte aligned, according to the size
of the I/O range.
The base address of the RTC, Serial Port 1, Serial Port 2,
and the Infrared Communication Port are limited to the I/O
address range of 00h to 7Fxh only (bits [15:11] are forced
to 0). The Parallel Port base address is limited to the I/O
address range of 00h to 3F8h. The addresses of the nonlegacy devices are configurable within the full 16-bit
address range (up to FFFxh).
In some special cases, other address bits are used for
internal decoding (such as 10 in the Parallel Port). For
more details, please see the detailed description of the
base address register for each specific logical device.
AMD Geode™ SC1200/SC1201 Processor Data Book93
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5.4Standard Configuration Registers
As illustrated in Figure 5-4, the Standard Configuration registers are broadly divided into two categories: SIO Control
and Configuration registers and Logical Device Control and
Configuration registers (one per logical device, some are
optional).
SIO Control and Configuration Registers
The only PnP control register in the SIO module is the Logical Device Number register at Index 07h. All other standard PnP control registers are associated with PnP
protocol for ISA add-in cards, and are not supported by the
SIO module.
The SIO Configuration registers at Index 20h-27h are
mainly used for part identification. (See Section 5.4.1 "SIO
Control and Configuration Registers" on page 97 for further
details.)
Logical Device Control and Configuration Registers
A subset of these registers is implemented for each logical
device. (See Table 5-2 on page 92 for LDN assignment and
Section 5.4.2 "Logical Device Control and Configuration"
on page 98 for register details.)
Logical Device Control Register (Index 30h): The only
implemented Logical Device Control register is the Activate
register at Index 30. Bit 0 of the Activate register and bit 0
of the SIO Configuration 1 register (Global Device Enable
bit) control the activation of the associated function block
IndexRegister Name
07hLogical Device Number
20hSIO ID
SIO Control and
Configuration Registers
Logical Device Control and
Configuration Registers one per logical device
(some are optional)
21hSIO Configuration 1
22hSIO Configuration 2
27hSIO Revision ID
2EhReserved exclusively for AMD use
30hLogical Device Control (Activate)
60hI/O Port Base Address Descriptor 0 Bits [15:8]
61hI/O Port Base Address Descriptor 0 Bits [7:0]
62hI/O Port Base Address Descriptor 1 Bits [15:8]
63hI/O Port Base Address Descriptor 1 Bits [7:0]
70hInterrupt Number Select
71hInterrupt Type Select
74hDMA Channel Select 0
75hDMA Channel Select 1
F0hDevice Specific Logical Device Configuration 1
F1hDevice Specific Logical Device Configuration 2
F2hDevice Specific Logical Device Configuration 3
F3hDevice Specific Logical Device Configuration 4
SuperI/O Module
(except for the RTC and the SWC). Activation of the block
enables access to the block’s registers, and attaches its
system resources, which are unused as long as the block is
not activated. Activation of the block may also result in
other effects (e.g., clock enable and active signaling), for
certain functions.
Standard Logical Device Configuration Registers
(Index 60h-75h): These registers are used to manage the
resource allocation to the functional blocks. The I/O port
base address descriptor 0 is a pair of registers at Index
60h-61h, holding the (first or only) 16-bit base address for
the register set of the functional block. An optional second
base-address (descriptor 1) at Index 62h-63h is used for
devices with more than one continuous register set. Interrupt Number Select (Index 70h) and Interrupt Type Select
(Index 71h) allocate an IRQ line to the block and control its
type. DMA Channel Select 0 (Index 74h) allocates a DMA
channel to the block, where applicable. DMA Channel
Select 1 (Index 75h) allocates a second DMA channel,
where applicable.
Special Logical Device Configuration Registers (F0hF3h): The vendor-defined registers, starting at Index F0h
are used to control function-specific parameters such as
operation modes, power saving modes, pin TRI-STATE,
clock rate selection, and non-standard extensions to
generic functions.
Figure 5-4. Standard Configuration Registers Map
94AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
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Table 5-3 provides the bit definitions for the Standard Configuration registers.
• All reserved bits return 0 on reads, except where noted
otherwise. They must not be modified as such modifica-
write to prevent the values of reserved bits from being
changed during write.
• Write only registers should not use read-modify-write
during updates.
tion may cause unpredictable results. Use read-modify-
Table 5-3. Standard Configuration Registers
BitDescription
Index 07hLogical Device Number (R/W)
This register selects the current logical device. See Table 5-2 for valid numbers. All other values are reserved.
7:0Logical Device number.
Index 20h-2FhSIO Configuration (R/W)
SIO configuration and ID registers. See Section 5.4.1 "SIO Control and Configuration Registers" on page 97 for register/bit details.
Index 30hActivate (R/W)
7:1Reserved.
0Logical Device Activation Control.
0: Disable
1: Enable
Index 60hI/O Port Base Address Bits [15:8] Descriptor 0 (R/W)
3:0Interrupt Number. These bits select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to
IRQ12).
Note: IRQ0 is not a valid interrupt selection.
Index 71hInterrupt Request Type Select (R/W)
Selects the type and level of the interrupt request number selected in the previous register.
7:2Reserved.
1Interrupt Level Requested. Level of interrupt request selected in previous register.
0: Low polarity.
1: High polarity.
This bit must be set to 1 (high polarity), except for IRQ8#, that must be low polarity.
0Interrupt Type Requested. Type of interrupt request selected in previous register.
0: Edge.
1: Level.
Index 74hDMA Channel Select 0 (R/W)
Selects selected DMA channel for DMA 0 of the logical device (0 - the first DMA channel in case of using more than one DMA channel).
7:3Reserved.
2:0DMA 0 Channel Select. This bit field selects the DMA channel for DMA 0.
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
Values 5-7 are reserved.
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SuperI/O Module
Table 5-3. Standard Configuration Registers
BitDescription
Index 75hDMA Channel Select 1 (R/W)
Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA
channel).
7:3Reserved.
2:0DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1.
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
Values 5-7 are reserved.
Index F0h-FEhLogical Device Configuration (R/W)
Special (vendor-defined) configuration options.
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5.4.1SIO Control and Configuration Registers
Table 5-4 lists the SIO Control and Configuration registers and Table 5-5 provides their bit formats.
Table 5-4. SIO Control and Configuration Register Map
IndexTypeNamePower RailReset Value
20hROSID. SIO ID V
21hR/WSIOCF1. SIO Configuration 1 V
22hR/WSIOCF2. SIO Configuration 2 V
27hROSRID. SIO Revision ID V
CORE
CORE
PP
CORE
F5h
01h
02h
01h
2Eh---RSVD. Reserved exclusively for AMD use.------
Table 5-5. SIO Control and Configuration Registers
BitDescription
Index 20hSIO ID Register - SID (RO)Reset Value: F5h
7:0Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.
Index 21hSIO Configuration 1 Register - SIOCF1 (RW)Reset Value: 01h
7:6General Purpose Scratch. When bit 5 is set to 1, these bits are RO. After reset, these bits can be read or write. Once
changed to RO, the bits can be changed back to R/W only by a hardware reset.
5Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be cleared to 0 only
by a hardware reset.
0: Bits 7 and 6 of this register are R/W bits. (Default)
1: Bits 7 and 6 of this register are RO bits.
4:2Reserved.
1SW Reset. Read always returns 0.
0: Ignored. (Default)
1: Resets all devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC.
0Global Device Enable. This bit controls the function enable of all the logical devices in the SIO module, except the SWC
and the RTC. It allows them to be disabled simultaneously by writing to a single bit.
0: All logical devices in the SIO module are disabled, except the SWC and the RTC.
1: Each logical device is enabled according to its Activate register at Index 30h. (Default)
Index 22hSIO Configuration 2 Register - SIOCF2 (R/W)Reset Value: 02h
Note:This register is reset only when V
7Reserved.
6:4General Purpose Scratch. Battery-backed.
3:2Reserved.
1Reserved.
0Reserved. (RO)
Index 27hSIO Revision ID Register - SRID (RO)Reset Value: 01h
7:0SIO Revision ID. (RO) This RO register contains the identity number of the chip revision. SRID is incremented on each revi-
sion.
is first applied.
PP
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5.4.2Logical Device Control and Configuration
As described in Section 5.3.2 "Banked Logical Device Registers" on page 92, each functional block is associated with
a Logical Device Number (LDN). This section provides the
register descriptions for each LDN.
The register descriptions in this subsection use the following abbreviations for Type:
• R/W= Read/Write
• R= Read from a specific address returns the
value of a specific register. Write to the
same address is to a different register.
•W=Write
• RO= Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit
clears it to 0. Writing 0 has no effect.
5.4.2.1LDN 00h - Real-Time Clock
Table 5-6 lists the registers which are relevant to configuration of the Real-Time Clock (RTC). Only the last registers
(F0h-F3h) are described here (Table 5-7). See Table 5-3
"Standard Configuration Registers" on page 95 for descriptions of the other registers.
Table 5-6. Relevant RTC Configuration Registers
IndexTypeConfiguration Register or Action
30hR/W
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.
60hR/WStandard Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.00h
61hR/WStandard Base Address LSB register. Bit 0 (for A0) is RO, 0b.70h
62hR/WExtended Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.00h
63hR/WExtended Base Address LSB register. Bit 0 (for A0) is RO, 0b.72h
70hR/WInterrupt Number. 08h
71hR/WInterrupt Type. Bit 1 is R/W; other bits are RO.00h
74hROReport no DMA assignment. 04h
75hROReport no DMA assignment. 04h
F0hR/WRAM Lock register (RLR). 00h
F1hR/WDate of Month Alarm Offset register (DOMAO). Sets index of Date of Month Alarm
register in the standard base address.
F2hR/WMonth Alarm Offset register (MONAO). Sets index of Month Alarm register in the
standard base address.
F3hR/WCentury Offset register (CENO). Sets index of Century register in the standard base
address.
1.The logical device registers are maintained, and all RTC mechanisms are functional.
1
Reset
Val ue
00h
00h
00h
00h
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Table 5-7. RTC Configuration Registers
BitDescription
Index F0h RAM Lock Register - RLR (R/W)
When any non-reserved bit in this register is set to 1, it can be cleared only by hardware reset.
7Block Standard RAM.
0: No effect on Standard RAM access. (Default)
1: Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads return FFh.
6Block RAM Write.
0: No effect on RAM access. (Default)
1: Writes to RAM (Standard and Extended) are ignored.
5Block Extended RAM Write. This bit controls writes to bytes 00h-1Fh of the Extended RAM.
0: No effect on the Extended RAM access. (Default)
1: Writes to bytes 00h-1Fh of the Extended RAM are ignored.
4Block Extended RAM Read. This bit controls read from bytes 00h-1Fh of the Extended RAM.
0: No effect on Extended RAM access. (Default)
1: Reads to bytes 00h-1Fh of the Extended RAM are ignored.
3Block Extended RAM. This bit controls access to the Extended RAM 128 bytes.
0: No effect on Extended RAM access. (Default)
1: Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh.
2:0Reserved.
Index F1hDate Of Month Alarm Register Offset Register - DOMAO (R/W)
7Reserved.
6:0Date of Month Alarm Register Offset Value.
Index F2hMonth Alarm Register Offset Register - MANAO (R/W)
7Reserved.
6:0Month Alarm Register Offset Value.
Index F3hCentury Register Offset Register - CENO (R/W)
7Reserved.
6:0Century Register Offset Value.
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5.4.2.2LDN 01h - System Wakeup Control
Table 5-8 lists registers that are relevant to the configura-
described earlier in Table 5-3 "Standard Configuration Registers" on page 95.
tion of System Wakeup Control (SWC). These registers are
Table 5-8. Relevant SWC Registers
IndexTypeConfiguration Register or Action
30hR/W
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.