AMD RX 480 Schematics
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Mechanical Key
RSVD_B82
PRSNT2_B81
GND
PETn15
PETp15
GND
GND
PETn14
PETp14
GND
GND
PETn13
PETp13
GND
GND
PETn12
GND
PERn15
PERp15
GND
GND
PERn14
PERp14
GND
GND
PERn13
PERp13
GND
GND
PERn12
PERp12
GND
PERn0
PETp12
GND
GND
PETn11
PETp11
GND
GND
PETn10
PETp10
GND
GND
PETn9
PETp9
GND
GND
PETn8
PETp8
GND
PRSNT2_B48
GND
PETn7
PETp7
GND
GND
PETn6
PETp6
GND
GND
PETn5
PETp5
GND
GND
PETn4
PETp4
GND
PRSNT2_B31
RSVD_B30
GND
PETn3
PETp3
GND
GND
PETn2
PETp2
GND
GND
PETn1
PETp1
GND
PRSNT2_B17
GND
PETn0
PETp0
GND
RSVD_B12
WAKE_
3.3Vaux
JTAG1
+3.3V
GND
SMDAT
SMCLK
GND
+12V
+12V
+12V
GND
PERn11
PERp11
GND
GND
PERn10
PERp10
GND
GND
PERn9
PERp9
GND
GND
PERn8
PERp8
GND
RSVD_A50
GND
PERn7
PERp7
GND
GND
PERn6
PERp6
GND
GND
PERn5
PERp5
GND
GND
PERn4
PERp4
GND
RSVD_A33
RSVD_A32
GND
PERn3
PERp3
GND
GND
PERn2
PERp2
GND
GND
PERn1
PERp1
GND
RSVD_A19
GND
PERp0
GND
REFCLK-
REFCLK+
GND
PERST_
+3.3V
+3.3V
JTAG5
JTAG4
JTAG3
JTAG2
GND
+12V
+12V
PRSNT1_A1
BI
IN
C
VCC
Y
A
GND
B
ININBI
OUT
OUTININININININININININININININININININININININININININININ
OUT
OUTINININININOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
8
7
6
345
2
1
C
A
(1) PCI-EXPRESS EDGE CONNECTOR
(1) PCI-EXPRESS EDGE CONNECTOR
LMSMCLK
G_SMBCLK
G_SMBCLK
G_SMBDAT
G_SMBDAT
LMSMDATA
LMSMDATA
0.15uF
0.15uF
16V
16V
C155
C155
0.01uF
0.01uF
1uF
1uF
LMSMCLK
R113
R113
R112
R112
7
7
OUT
C156
C156
10V
10V
C165
C165
10uF
10uF
6.3V6.3V
6.3V6.3V
21
21
21
21
G_WAKEb
G_WAKEb
24
24
IN
8 24
8 24
24 8
24 8
PLACE THESE CAPS AS CLOSE TO
PLACE THESE CAPS AS CLOSE TO
PCIE CONNECTOR AS POSSIBLE
PCIE CONNECTOR AS POSSIBLE
+12V_BUS
+12V_BUS
+3.3V_BUS +3.3V_BUS
+3.3V_BUS +3.3V_BUS
IN
BI
24
24
BI
C157
C151 C152
C157
C151 C152
10uF
10uF
0.15uF
0.15uF
16V
16V
16V
16V
C153 C154
C153 C154
10uF 0.1uF
10uF 0.1uF
8
6.3V 6.3V
6.3V 6.3V
0R
5%
0R
5%
0R 5%
0R 5%
+3.3V_BUS
+3.3V_BUS
LIMITED TO OBFF
LIMITED TO OBFF
7
+3.3V_BUS
+3.3V_BUS
R107
R107
2.2K
2.2K
5%
5%
2 1
2 1
R103
45.3K
45.3K
1% 1%
1% 1%
2 1
2 1
+12V_BUS
+12V_BUS
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
+3.3V_BUS
1
1
Q100
R104
R104R103 R109
45.3K
45.3K
2 1
2 1
R110
R110
MR110
MR110
R105
R105
R106
R106
+3.3V_BUS
+3.3V_BUS
21
21
0R 5%
0R
21
21
R108
R108
5%0R
5%0R
5%
1
2
213
0R
0R
2
2
BSH111
BSH111
2
2
Q101
Q101
BSH111
BSH111
3
21
21
Q100
3
3
2 1
IN
2 1
1
1
5%
21
5%
21
21
21
3
3
Q110
Q110
BSH111
BSH111
1
1
5%
5%
0R
0R
5%
5%
0R
0R
7
7
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
2
2
OUT
6
+3.3V_AUX +3.3V_BUS
+3.3V_AUX +3.3V_BUS
R109
10K
10K
5%
5%
SMCLK
SMCLK
SMDAT
SMDAT
WAKEb
WAKEb
CLKREQb
CLKREQb
PETp0_GFXRp0
PETp0_GFXRp0
PETn0_GFXRn0
PETn0_GFXRn0
PETp1_GFXRp1
PETp1_GFXRp1
PETn1_GFXRn1
PETn1_GFXRn1
PETp2_GFXRp2
PETp2_GFXRp2
PETn2_GFXRn2
PETn2_GFXRn2
PETp3_GFXRp3
PETp3_GFXRp3
PETn3_GFXRn3
PETn3_GFXRn3
PETp4_GFXRp4
PETp4_GFXRp4
PETn4_GFXRn4
PETn4_GFXRn4
PETp5_GFXRp5
PETp5_GFXRp5
PETn5_GFXRn5
PETn5_GFXRn5
PETp6_GFXRp6
PETp6_GFXRp6
PETn6_GFXRn6
PETn6_GFXRn6
PETp7_GFXRp7
PETp7_GFXRp7
PETn7_GFXRn7
PETn7_GFXRn7
PETp8_GFXRp8
PETp8_GFXRp8
PETn8_GFXRn8
PETn8_GFXRn8
PETp9_GFXRp9
PETp9_GFXRp9
PETn9_GFXRn9
PETn9_GFXRn9
PETp10_GFXRp10
PETp10_GFXRp10
PETn10_GFXRn10
PETn10_GFXRn10
PETp11_GFXRp11
PETp11_GFXRp11
PETn11_GFXRn11
PETn11_GFXRn11
PETp12_GFXRp12
PETp12_GFXRp12
PETn12_GFXRn12
PETn12_GFXRn12
PETp13_GFXRp13
PETp13_GFXRp13
PETn13_GFXRn13
PETn13_GFXRn13
PETp14_GFXRp14
PETp14_GFXRp14
PETn14_GFXRn14
PETn14_GFXRn14
PETp15_GFXRp15
PETp15_GFXRp15
PETn15_GFXRn15
PETn15_GFXRn15
PRESENCE
PRESENCE
+12V_BUS
+12V_BUS
B10
B10
B11
B11
B12
B12
B13
B13
B14
B14
B15
B15
B16
B16
B17
B17
B18
B18
B19
B19
B20
B20
B21
B21
B22
B22
B23
B23
B24
B24
B25
B25
B26
B26
B27
B27
B28
B28
B29
B29
B30
B30
B31
B31
B32
B32
B33
B33
B34
B34
B35
B35
B36
B36
B37
B37
B38
B38
B39
B39
B40
B40
B41
B41
B42
B42
B43
B43
B44
B44
B45
B45
B46
B46
B47
B47
B48
B48
B49
B49
B50
B50
B51
B51
B52
B52
B53
B53
B54
B54
B55
B55
B56
B56
B57
B57
B58
B58
B59
B59
B60
B60
B61
B61
B62
B62
B63
B63
B64
B64
B65
B65
B66
B66
B67
B67
B68
B68
B69
B69
B70
B70
B71
B71
B72
B72
B73
B73
B74
B74
B75
B75
B76
B76
B77
B77
B78
B78
B79
B79
B80
B80
B81
B81
B82
B82
5
B1
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
+12V
+12V
+12V
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE_
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT2_B17
GND
PETp1
PETn1
GND
GND
PETp2
PETn2
GND
GND
PETp3
PETn3
GND
RSVD_B30
PRSNT2_B31
GND
PETp4
PETn4
GND
GND
PETp5
PETn5
GND
GND
PETp6
PETn6
GND
GND
PETp7
PETn7
GND
PRSNT2_B48
GND
PETp8
PETn8
GND
GND
PETp9
PETn9
GND
GND
PETp10
PETn10
GND
GND
PETp11
PETn11
GND
GND
PETp12
PETn12
GND
GND
PETp13
PETn13
GND
GND
PETp14
PETn14
GND
GND
PETp15
PETn15
GND
PRSNT2_B81
RSVD_B82
MPCIE1
MPCIE1
Mechanical Key
x16 PCIe
x16 PCIe
PRSNT1_A1
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST_
GND
REFCLK+
REFCLK-
GND
PERp0
PERn0
GND
RSVD_A19
GND
PERp1
PERn1
GND
GND
PERp2
PERn2
GND
GND
PERp3
PERn3
GND
RSVD_A32
RSVD_A33
GND
PERp4
PERn4
GND
GND
PERp5
PERn5
GND
GND
PERp6
PERn6
GND
GND
PERp7
PERn7
GND
RSVD_A50
GND
PERp8
PERn8
GND
GND
PERp9
PERn9
GND
GND
PERp10
PERn10
GND
GND
PERp11
PERn11
GND
GND
PERp12
PERn12
GND
GND
PERp13
PERn13
GND
GND
PERp14
PERn14
GND
GND
PERp15
PERn15
GND
+12V_BUS
+12V_BUS
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A10
A11
A11
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A17
A17
A18
A18
A19
A19
A20
A20
A21
A21
A22
A22
A23
A23
A24
A24
A25
A25
A26
A26
A27
A27
A28
A28
A29
A29
A30
A30
A31
A31
A32
A32
A33
A33
A34
A34
A35
A35
A36
A36
A37
A37
A38
A38
A39
A39
A40
A40
A41
A41
A42
A42
A43
A43
A44
A44
A45
A45
A46
A46
A47
A47
A48
A48
A49
A49
A50
A50
A51
A51
A52
A52
A53
A53
A54
A54
A55
A55
A56
A56
A57
A57
A58
A58
A59
A59
A60
A60
A61
A61
A62
A62
A63
A63
A64
A64
A65
A65
A66
A66
A67
A67
A68
A68
A69
A69
A70
A70
A71
A71
A72
A72
A73
A73
A74
A74
A75
A75
A76
A76
A77
A77
A78
A78
A79
A79
A80
A80
A81
A81
A82
A82
DD
+3.3V_BUS
+3.3V_BUS
PRESENCE
PRESENCE
JTDIO_LOOP
JTDIO_LOOP
PCIE_REFCLKP
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN
PERp0
PERp0
PERn0
PERn0
PERp1
PERp1
PERn1
PERn1
PERp2
PERp2
PERn2
PERn2
PERp3
PERp3
PERn3
PERn3
1
1
SYSTEM JTAG TDI AND
SYSTEM JTAG TDI AND
TDO ARE HARD WIRED.
TDO ARE HARD WIRED.
20 21
20 21
2
2
OUT
2
2
OUT
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
1.8V_EN
1.8V_EN
R102
R102
PERSTb
PERSTb
C159
C159
6.3V
6.3V
0R
0R
5%
21 4
21
5%
2 1
2 1
R111
R111
10K0.1uF
10K0.1uF
5%
5%
+3.3V_BUS
+3.3V_BUS
R120
R120
C158
C158
0.1uF
0.1uF
6.3V
6.3V
U100
U100
3
3
A
1
1
B
C
74AUP1G57GM
74AUP1G57GM
DNI
DNI
VCC
GND
5
5
4
Y
26
26
5%
5%
21
21
1K
1K
PERSTb_BUF
PERSTb_BUF
23 21 2
OUTIN
23 21 2
C
PERp4
PERp4
PERn4
PERn4
PERp5
PERp5
PERn5
PERn5
PERp6
PERp6
PERn6
PERn6
PERp7
PERp7
PERn7
PERn7
PERp8
PERp8
PERn8
PERn8
PERp9
PERp9
PERn9
PERn9
PERp10
PERp10
PERn10
PERn10
PERp11
PERp11
PERn11
PERn11
PERp12
PERp12
PERn12
PERn12
PERp13
PERp13
PERn13
PERn13
PERp14
PERp14
PERn14
PERn14
PERp15
PERp15
PERn15
PERn15
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
4
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
2
2
IN
PCIE EDGE CONNECTOR
PCIE EDGE CONNECTOR
Wed Apr 13 17:02:06 2016 1.0
Wed Apr 13 17:02:06 2016 1.0
1 26
1 26
OF
105_D009XX_00
105_D009XX_00
REV:
3
SYMBOL LEGEND
SYMBOL LEGEND
DNI
DNI
b or #
b or #
BUO
BUO
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
1
DO NOT
DO NOT
INSTALL
INSTALL
ACTIVE
ACTIVE
LOW
LOW
BRING UP
BRING UP
ONLY
ONLY
DIGITAL
DIGITAL
GROUND
GROUND
ANALOG
ANALOG
GROUND
GROUND
BB
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
INININININININININININININ
REV 0.90
S
S
E
R
P
X
E
I
C
P
PART 2 OF 18
VSS
VSS
VDD_08
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
PCIE_ZVSS
PX_EN
PCIE_RX15N
PCIE_RX15P
PCIE_RX14N
PCIE_RX14P
PCIE_RX13N
PCIE_RX13P
PCIE_RX12N
PCIE_RX12P
PCIE_RX11N
PCIE_RX11P
PCIE_RX10N
PCIE_RX10P
PCIE_RX9N
PCIE_RX9P
PCIE_RX8N
PCIE_RX8P
PCIE_RX7N
PCIE_RX7P
PCIE_RX6N
PCIE_RX6P
PCIE_RX5N
PCIE_RX5P
PCIE_RX4N
PCIE_RX4P
PCIE_RX3N
PCIE_RX3P
PCIE_RX2N
PCIE_RX2P
PCIE_RX1N
PCIE_RX1P
PCIE_RX0N
PCIE_RX0P
PCIE_REFCLKN
PCIE_REFCLKP
PERSTB
PCIE_TX15N
PCIE_TX15P
PCIE_TX14N
PCIE_TX14P
PCIE_TX13N
PCIE_TX13P
PCIE_TX12N
PCIE_TX12P
PCIE_TX11N
PCIE_TX11P
PCIE_TX10N
PCIE_TX10P
PCIE_TX9N
PCIE_TX9P
PCIE_TX8N
PCIE_TX8P
PCIE_TX7N
PCIE_TX7P
PCIE_TX6N
PCIE_TX6P
PCIE_TX5N
PCIE_TX5P
PCIE_TX4N
PCIE_TX4P
PCIE_TX3N
PCIE_TX3P
PCIE_TX2N
PCIE_TX2P
PCIE_TX1N
PCIE_TX1P
PCIE_TX0N
PCIE_TX0P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININININININININININININININININININININININ
IN
8
7
6
345
2
1
C
(2) ELLESMERE PCIE INTERFACE
(2) ELLESMERE PCIE INTERFACE
+1.8V
+1.8V
+0.8V
+0.8V
1uF 1uF
1uF 1uF
6.3V
6.3V
C1703
C1703
6.3V
6.3V
C1706
C1706
6.3V
6.3V
2 1
2 1
OVERLAP
OVERLAP
1uF
1uF
6.3V
6.3V
C1704
C1704
6.3V 6.3V
6.3V 6.3V
MC1707
MC1707
C1707
C1707
4.7uF
22uF4.7uF
4.7uF
22uF4.7uF
6.3V4V
6.3V4V
6.3V
6.3V
C1705
C1705
0.1uF0.1uF0.1uF
0.1uF0.1uF0.1uF
6.3V
6.3V
C1708
C1708
4.7uF
4.7uF
6.3V
6.3V
C1738C1702C1701C1700
C1738C1702C1701C1700
1uF
1uF
C1719
C1719
0.1uF
0.1uF
C1709
C1709
4.7uF
4.7uF
6.3V
6.3V
+0.8V
+0.8V
C1711
C1711
1uF
1uF
6.3V
6.3V
C1714C1713
C1714C1713
0.1uF
0.1uF
0.1uF
0.1uF
6.3V
6.3V
6.3V
6.3V
MC1717
MC1717
22uF
22uF
4V
4V
2 1
2 1
OVERLAP
OVERLAP
C1717
C1717
4.7uF
4.7uF
6.3V
6.3V
+1.8V
+1.8V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+0.8V
+0.8V
MC141
MC141
10uF
10uF
6.3V
6.3V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OVERLAP
OVERLAP
C133
C133
1uF
1uF
6.3V
6.3V
C147
C147
1uF
1uF
6.3V
6.3V
0.1uF
0.1uF
6.3V
6.3V
TP101
TP101
TP102
TP102
TP117
TP117
TP118
TP118
1uF
1uF
6.3V 6.3V
6.3V 6.3V
4.7uF
4.7uF
6.3V
6.3V
C137
C137
1uF
1uF
6.3V
6.3V
C162C161
C162C161
0.1uF
0.1uF
6.3V
6.3V
PETp0_GFXRp0
PETp0_GFXRp0
PETn0_GFXRn0
PETn0_GFXRn0
PETp1_GFXRp1
PETp1_GFXRp1
PETn1_GFXRn1
PETn1_GFXRn1
PETp2_GFXRp2
PETp2_GFXRp2
PETn2_GFXRn2
PETn2_GFXRn2
PETp3_GFXRp3
PETp3_GFXRp3
PETn3_GFXRn3
PETn3_GFXRn3
PETp4_GFXRp4
PETp4_GFXRp4
PETn4_GFXRn4
PETn4_GFXRn4
PETp5_GFXRp5
PETp5_GFXRp5
PETn5_GFXRn5
PETn5_GFXRn5
PETp6_GFXRp6
PETp6_GFXRp6
PETn6_GFXRn6
PETn6_GFXRn6
PETp7_GFXRp7
PETp7_GFXRp7
PETn7_GFXRn7
PETn7_GFXRn7
PETp8_GFXRp8
PETp8_GFXRp8
PETn8_GFXRn8
PETn8_GFXRn8
PETp9_GFXRp9
PETp9_GFXRp9
PETn9_GFXRn9
PETn9_GFXRn9
PETp10_GFXRp10
PETp10_GFXRp10
PETn10_GFXRn10
PETn10_GFXRn10
PETp11_GFXRp11
PETp11_GFXRp11
PETn11_GFXRn11
PETn11_GFXRn11
PETp12_GFXRp12
PETp12_GFXRp12
PETn12_GFXRn12
PETn12_GFXRn12
PETp13_GFXRp13
PETp13_GFXRp13
PETn13_GFXRn13
PETn13_GFXRn13
PETp14_GFXRp14
PETp14_GFXRp14
PETn14_GFXRn14
PETn14_GFXRn14
PETp15_GFXRp15
PETp15_GFXRp15
PETn15_GFXRn15
PETn15_GFXRn15
PCIE_REFCLKP
C139
C139
0.1uF
0.1uF
6.3V
6.3V
C142
C142
6.3V
6.3V
C145
C145
1uF
1uF
6.3V
6.3V
1uF
1uF
6.3V
6.3V
10u
10u
C160
C160
10uF
10uF
4V
4V
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_REFCLKN
PERSTb_BUF
PERSTb_BUF
C172
C172
1uF
1uF
6.3V
6.3V
C140
C140
0.01uF
0.01uF
6.3V
6.3V
C30
C30
1uF1uF
1uF1uF
6.3V
6.3V
C146
C146
1uF
1uF
6.3V
6.3V
C1319
C1319
1uF
1uF
6.3V
6.3V
C148
C148
4.7uF
4.7uF
6.3V
6.3V
2 1
2 1
1uF
1uF
6.3V6.3V
6.3V6.3V
MC148
MC148
22uF
22uF
4V
4V
1
1
IN
1
1
IN
1 21 23
1 21 23
IN
C177C176 C173
C177C176 C173
1uF
1uF
C136C141
C136C141
1uF
1uF
6.3V
6.3V
C138
C138
1uF
1uF
6.3V
6.3V
C1284
C150
C150
C1284
1uF
1uF
6.3V
6.3V
2 1
2 1
AN42
AN42
AN43
AN43
AN41
AN41
AM41
AM41
AM43
AM43
AM42
AM42
AK43
AK43
AK42
AK42
AJ42
AJ42
AJ43
AJ43
AJ41
AJ41
AG41
AG41
AG43
AG43
AG42
AG42
AF43
AF43
AF42
AF42
AE42
AE42
AE43
AE43
AE41
AE41
AD41
AD41
AD43
AD43
AD42
AD42
AC43
AC43
AC42
AC42
AA42
AA42
AA43
AA43
AA41
AA41
Y41
Y41
Y43
Y43
Y42
Y42
W42
W42
W43
W43
AR42
AR42
AR43
AR43
AV42
AV42
AM25
AM25
AN25
AN25
AN26
AN26
AP26
AP26
AP27
AP27
AR27
AR27
AA34
AA34
AA35
AA35
AD36
AD36
AE35
AE35
AF35
AF35
AG36
AG36
AJ35
AJ35
AK35
AK35
AM36
AM36
AN35
AN35
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_18
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
VDD_08
U1
U1
PART 2 OF 18
P
C
I
E
X
P
R
E
S
S
ellesmere_l4
ellesmere_l4
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_ZVSS
PX_EN
VDD_08
VSS
VSS
REV 0.90
AR38
AR38
AR39
AR39
AR37
AR37
AN37
AN37
AN39
AN39
AN38
AN38
AM39
AM39
AM38
AM38
AK38
AK38
AK39
AK39
AK37
AK37
AJ37
AJ37
AJ39
AJ39
AJ38
AJ38
AG39
AG39
AG38
AG38
AF38
AF38
AF39
AF39
AF37
AF37
AE37
AE37
AE39
AE39
AE38
AE38
AD39
AD39
AD38
AD38
AC38
AC38
AC39
AC39
AC37
AC37
AA37
AA37
AA39
AA39
AA38
AA38
Y38
Y38
Y39
Y39
AK30
AK30
V40
V40
AJ30
AJ30
AJ29
AJ29
AK29
AK29
PCIE_TX0P
PCIE_TX0P
PCIE_TX0N
PCIE_TX0N
PCIE_TX1P
PCIE_TX1P
PCIE_TX1N
PCIE_TX1N
PCIE_TX2P
PCIE_TX2P
PCIE_TX2N
PCIE_TX2N
PCIE_TX3P
PCIE_TX3P
PCIE_TX3N
PCIE_TX3N
PCIE_TX4P
PCIE_TX4P
PCIE_TX4N
PCIE_TX4N
PCIE_TX5P
PCIE_TX5P
PCIE_TX5N
PCIE_TX5N
PCIE_TX6P
PCIE_TX6P
PCIE_TX6N
PCIE_TX6N
PCIE_TX7P
PCIE_TX7P
PCIE_TX7N
PCIE_TX7N
PCIE_TX8P
PCIE_TX8P
PCIE_TX8N
PCIE_TX8N
PCIE_TX9P
PCIE_TX9P
PCIE_TX9N
PCIE_TX9N
PCIE_TX10P
PCIE_TX10P
PCIE_TX10N
PCIE_TX10N
PCIE_TX11P
PCIE_TX11P
PCIE_TX11N
PCIE_TX11N
PCIE_TX12P
PCIE_TX12P
PCIE_TX12N
PCIE_TX12N
PCIE_TX13P
PCIE_TX13P
PCIE_TX13N
PCIE_TX13N
PCIE_TX14P
PCIE_TX14P
PCIE_TX14N
PCIE_TX14N
PCIE_TX15P
PCIE_TX15P
PCIE_TX15N
PCIE_TX15N
PCIE_ZVSS
PCIE_ZVSS
R155
R156
R150
R150
DNI
DNI
PERp0
PX_EN
PX_EN
0.1uF
0.1uF
PERp0
PERn0
PERn0
PERp1
PERp1
PERn1
PERn1
PERp2
PERp2
PERn2
PERn2
PERp3
PERp3
PERn3
PERn3
PERp4
PERp4
PERn4
PERn4
PERp5
PERp5
PERn5
PERn5
PERp6
PERp6
PERn6
PERn6
PERp7
PERp7
PERn7
PERn7
PERp8
PERp8
PERn8
PERn8
PERp9
PERp9
PERn9
PERn9
PERp10
PERp10
PERn10
PERn10
PERp11
PERp11
PERn11
PERn11
PERp12
PERp12
PERn12
PERn12
PERp13
PERp13
PERn13
PERn13
PERp14
PERp14
PERn14
PERn14
PERp15
PERp15
PERn15
PERn15
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
21 24
21 24 23
23
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C100
C100
C101
C101
C102
C102
C103
C103
C104
C104
C105
C105
C106
C106
C107
C107
C108
C108
C109
C109
C111
C111
C110
C110
C112
C112
C113
C113
C114
C114
C115
C115
C116
C116
C117
C117
C118
C118
C119
C119
C120
C120
C121
C121
C122
C122
C123
C123
C124
C124
C125
C125
C126
C126
C127
C127
C128
C128
C129
C129
C130
C130
C131
C131
21
21R155
21R156
21
0R 5%
0R 5%
1K
1K
5%
5%
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
0.22uF
6.3V
6.3V
0.22uF
0.22uF
6.3V
0.22uF
6.3V
6.3V
0.22uF
6.3V
0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
0.22uF
0.22uF
6.3V
6.3V
6.3V
6.3V
0.22uF
0.22uF
0.22uF
6.3V
6.3V
0.22uF
0.22uF
0.22uF
6.3V
6.3V
6.3V0.22uF
6.3V0.22uF
0.22uF 6.3V
0.22uF 6.3V
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V
0.22uF
6.3V
0.22uF
0.22uF
6.3V
6.3V
0.22uF
6.3V
6.3V
0.22uF
0.22uF
6.3V
6.3V
0.22uF
0.22uF
6.3V
0.22uF
0.22uF
6.3V
6.3V0.22uF
6.3V0.22uF
0.22uF 6.3V
0.22uF 6.3V
6.3V0.22uF
6.3V0.22uF
0.22uF 6.3V
0.22uF 6.3V
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
6.3V0.22uF
0.22uF 6.3V
0.22uF 6.3V
0.22uF 6.3V
0.22uF 6.3V
0.22uF 6.3V
0.22uF 6.3V
1%200R
1%200R
C258
C258
6.3V
6.3V
2 1
2 1
DD
C
BB
+0.8V
+0.8V
EVDDQ_G
EVDDQ_G
R4302
R4302
1K
1K
5%
5%
2 1
2 1
R4301
R4301
0R
0R
21
21
EVDDQ5%
5%
EVDDQ
IN
24
24
Check BOM for more detail
A
7
8
Check BOM for more detail
6
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
5
4
ELLESMERE PCIE INTERFACE
ELLESMERE PCIE INTERFACE
Wed Apr 13 17:02:07 2016 1.0
Wed Apr 13 17:02:07 2016 1.0
2 26
2 26
OF
105_D009XX_00
105_D009XX_00
REV:
3
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
2
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
1
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
OUT
OUT
OUT
OUTBIBIBIBI
OUT
REV 0.90
B
K
N
A
B
E
C
A
F
R
E
T
N
I
Y
R
O
M
E
M
PART 4 OF 18
DRAM_RSTB
MEM_CALRB
MAB1_9MAB0_9
CLKB1B
CLKB1
CKEB1
WCKB1B_1
WCKB1_1
WCKB1B_0
WCKB1_0
ADBIB1
RASB1B
CASB1B
CSB1B_0
WEB1B
DDBIB1_3
DDBIB1_2
DDBIB1_1
DDBIB1_0
EDCB1_3
EDCB1_2
EDCB1_1
EDCB1_0
MVREFDB
CLKB0B
CLKB0
CKEB0
RASB0B
CASB0B
CSB0B_0
WEB0B
DDBIB0_3
DDBIB0_2
DDBIB0_1
DDBIB0_0
EDCB0_3
EDCB0_2
EDCB0_1
EDCB0_0
WCKB0B_1
WCKB0_1
WCKB0B_0
WCKB0_0
ADBIB0
MAB0_8
MAB0_7
MAB0_6
MAB0_5
MAB0_4
MAB0_3
MAB0_2
MAB0_1
MAB0_0
MAB1_8
MAB1_7
MAB1_6
MAB1_5
MAB1_4
MAB1_3
MAB1_2
MAB1_1
MAB1_0
DQB1_31
DQB1_30
DQB1_29
DQB1_28
DQB1_27
DQB1_26
DQB1_25
DQB1_24
DQB1_23
DQB1_22
DQB1_21
DQB1_20
DQB1_19
DQB1_18
DQB1_17
DQB1_16
DQB1_15
DQB1_14
DQB1_13
DQB1_12
DQB1_11
DQB1_10
DQB1_9
DQB1_8
DQB1_7
DQB1_6
DQB1_5
DQB1_4
DQB1_3
DQB1_2
DQB1_1
DQB1_0
DQB0_31
DQB0_30
DQB0_29
DQB0_28
DQB0_27
DQB0_26
DQB0_25
DQB0_24
DQB0_23
DQB0_22
DQB0_21
DQB0_20
DQB0_19
DQB0_18
DQB0_17
DQB0_16
DQB0_15
DQB0_14
DQB0_13
DQB0_12
DQB0_11
DQB0_10
DQB0_9
DQB0_8
DQB0_7
DQB0_6
DQB0_5
DQB0_4
DQB0_3
DQB0_2
DQB0_1
DQB0_0
REV 0.90
PART 3 OF 18
A
K
N
A
B
E
C
A
F
R
E
T
N
I
Y
R
O
M
E
M
DRAM_RSTA
MEM_CALRA
MAA1_9MAA0_9
CLKA0B
CLKA0
CLKA1B
CLKA1
CKEA1
RASA1B
CASA1B
CSA1B_0
WEA1B
DDBIA1_3
DDBIA1_2
DDBIA1_1
DDBIA1_0
EDCA1_3
EDCA1_2
EDCA1_1
EDCA1_0
WCKA1B_1
WCKA1_1
WCKA1B_0
WCKA1_0
MVREFDA
CKEA0
RASA0B
CASA0B
CSA0B_0
WEA0B
DDBIA0_3
DDBIA0_2
DDBIA0_1
DDBIA0_0
EDCA0_3
EDCA0_2
EDCA0_1
EDCA0_0
WCKA0B_1
WCKA0_1
WCKA0B_0
WCKA0_0
ADBIA0 ADBIA1
MAA1_8
MAA1_7
MAA1_6
MAA1_5
MAA1_4
MAA1_3
MAA1_2
MAA1_1
MAA1_0
DQA1_31
DQA1_30
DQA1_29
DQA1_28
DQA1_27
DQA1_26
DQA1_25
DQA1_24
DQA1_23
DQA1_22
DQA1_21
DQA1_20
DQA1_19
DQA1_18
DQA1_17
DQA1_16
DQA1_15
DQA1_14
DQA1_13
DQA1_12
DQA1_11
DQA1_10
DQA1_9
DQA1_8
DQA1_7
DQA1_6
DQA1_5
DQA1_4
DQA1_3
DQA1_2
DQA1_1
DQA1_0
MAA0_8
MAA0_7
MAA0_6
MAA0_5
MAA0_4
MAA0_3
MAA0_2
MAA0_1
MAA0_0
DQA0_31
DQA0_30
DQA0_29
DQA0_28
DQA0_27
DQA0_26
DQA0_25
DQA0_24
DQA0_23
DQA0_22
DQA0_21
DQA0_20
DQA0_19
DQA0_18
DQA0_17
DQA0_16
DQA0_15
DQA0_14
DQA0_13
DQA0_12
DQA0_11
DQA0_10
DQA0_9
DQA0_8
DQA0_7
DQA0_6
DQA0_5
DQA0_4
DQA0_3
DQA0_2
DQA0_1
DQA0_0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBI
BI
8
7
6
345
2
1
C
(3) ELLESMERE MEM INTERFACE CH A/B
(3) ELLESMERE MEM INTERFACE CH A/B
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
MAA0_<9..0> MAB1_<9..0>
5 3 5 3
5 3 5 3
2 1
2 1
120R
120R
MAA0_<9..0> MAB1_<9..0>
OUT OUT OUTOUT
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5 5
5 5
BI
5
5
OUT
5
5
OUT
5
5
OUT
5
5
OUT
5
5
OUT
5
5
OUT
5 5
5 5
OUT
1%
1%
R3610
R3610
MEM_CALRA
MEM_CALRA
U1
U1
5
5
3
DQA0_<0>
3
DQA0_<0>
0
0
DQA0_<1>
DQA0_<1>
1
1
DQA0_<2>
DQA0_<2>
2
2
DQA0_<3>
DQA0_<3>
3
3
DQA0_<4>
DQA0_<4>
4
4
DQA0_<5>
DQA0_<5>
5
5
DQA0_<6>
DQA0_<6>
6
6
DQA0_<7>
DQA0_<7>
7
7
DQA0_<8>
DQA0_<8>
8
8
DQA0_<9>
DQA0_<9>
9
9
DQA0_<10>
DQA0_<10>
10
10
DQA0_<11>
DQA0_<11>
11
11
DQA0_<12>
DQA0_<12>
12
12
DQA0_<13>
DQA0_<13>
13
13
DQA0_<14>
DQA0_<14>
14
14
DQA0_<15>
DQA0_<15>
15
15
DQA0_<16>
DQA0_<16>
16
16
DQA0_<17>
DQA0_<17>
17
17
DQA0_<18>
DQA0_<18>
18
18
DQA0_<19>
DQA0_<19>
19
19
DQA0_<20>
DQA0_<20>
20
20
DQA0_<21>
DQA0_<21>
21
21
DQA0_<22>
DQA0_<22>
22
22
DQA0_<23>
DQA0_<23>
23
23
DQA0_<24>
DQA0_<24>
24
24
DQA0_<25>
DQA0_<25>
25
25
DQA0_<26>
DQA0_<26>
26
26
DQA0_<27>
DQA0_<27>
27
27
DQA0_<28>
DQA0_<28>
28
28
DQA0_<29>
DQA0_<29>
29
29
DQA0_<30>
DQA0_<30>
30
30
DQA0_<31>
DQA0_<31>
31
31
5
5
3
MAA0_<0>
MAA0_<0>
3
0
0
MAA0_<1>
MAA0_<1>
1
1
MAA0_<2>
MAA0_<2>
2
2
MAA0_<3>
MAA0_<3>
3
3
MAA0_<4>
MAA0_<4>
4
4
MAA0_<5>
MAA0_<5>
5
5
MAA0_<6>
MAA0_<6>
6
6
MAA0_<7>
MAA0_<7>
7
7
MAA0_<8>
MAA0_<8>
8
8
WCKA0_0
WCKA0_0
WCKA0b_0
WCKA0b_0
WCKA0_1
WCKA0_1
WCKA0b_1
WCKA0b_1
EDCA0_0
EDCA0_0
EDCA0_1
EDCA0_1
EDCA0_2
EDCA0_2
EDCA0_3
EDCA0_3
DDBIA0_0
DDBIA0_0
DDBIA0_1
DDBIA0_1
DDBIA0_2
DDBIA0_2
DDBIA0_3
DDBIA0_3
ADBIA0 ADBIA1
ADBIA0 ADBIA1
CSA0b_0
CSA0b_0
CASA0b
CASA0b
RASA0b
RASA0b
WEA0b
WEA0b
CKEA0
CKEA0
CLKA0
CLKA0
CLKA0b CLKA1b
CLKA0b CLKA1b
U43
U43
DQA0_0
U41
U41
DQA0_1
U40
U40
DQA0_2
R42
R42
DQA0_3
P42
P42
DQA0_4
M43
M43
DQA0_5
M41
M41
DQA0_6
M40
M40
DQA0_7
J43
J43
DQA0_8
J42
J42
DQA0_9
H43
H43
DQA0_10
H41
H41
DQA0_11
F41
F41
DQA0_12
E43
E43
DQA0_13
C43
C43
DQA0_14
D42
D42
DQA0_15
U38
U38
DQA0_16
U37
U37
DQA0_17
R38
R38
DQA0_18
R36
R36
DQA0_19
P39
P39
DQA0_20
P37
P37
DQA0_21
M38
M38
DQA0_22
M37
M37
DQA0_23
L36
L36
DQA0_24
J40
J40
DQA0_25
J39
J39
DQA0_26
J37
J37
DQA0_27
E40
E40
DQA0_28
E41
E41
DQA0_29
D39
D39
DQA0_30
C39
C39
DQA0_31
U32
U32
MAA0_0
U34
U34
MAA0_1
V31
V31
MAA0_2
U35
U35
MAA0_3
V36
V36
MAA0_4
V33
V33
MAA0_5
R33
R33
MAA0_6
R35
R35
MAA0_7
U31
U31
MAA0_8
W35
W35
L42
L42
WCKA0_0
L41
L41
WCKA0B_0
L39
L39
WCKA0_1
L38
L38
WCKA0B_1
R41
R41
EDCA0_0
F42
F42
EDCA0_1
R39
R39
EDCA0_2
H38
H38
EDCA0_3
P43
P43
DDBIA0_0
H40
H40
DDBIA0_1
P40
P40
DDBIA0_2
F39
F39
DDBIA0_3
ADBIA0 ADBIA1
CSA0B_0
CASA0B
RASA0B
WEA0B
CKEA0
W32
W32
CLKA0
W33
W33
CLKA0B
Y31
Y31
MEM_CALRA
PART 3 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
A
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8
MAA1_9MAA0_9
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3
CSA1B_0
CASA1B
RASA1B
CLKA1B
MVREFDA
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
WEA1B
CKEA1
CLKA1
DQB0_<31..0>
A41
A41
B40
B40
A39
A39
C38
C38
C36
C36
A36
A36
B35
B35
A35
A35
A32
A32
C32
C32
D32
D32
B30
B30
B29
B29
D27
D27
C27
C27
A27
A27
E38
E38
H36
H36
F36
F36
G35
G35
E33
E33
F33
F33
F32
F32
G32
G32
G30
G30
J29
J29
E29
E29
F29
F29
F27
F27
D26
D26
E26
E26
G26
G26
H33
H33
M32
M32
J32
J32
K32
K32
K30
K30
L30
L30
H35
H35
L33
L33
J33
J33
N27
N27
B33
B33
C33
C33
D30
D30
E30
E30
B38
B38
C29
C29
D35
D35
G27
G27
D36
D36
A30
A30
E35
E35
H29
H29
J36P36
J36P36
M27Y34
M27Y34
L35R32
L35R32
M35P33
M35P33
H30V34
H30V34
M34P34
M34P34
M29
M29
L29
L29
P25
P25
5
5
DQA1_<0>
3
DQA1_<0>
3
DQA1_<1>
DQA1_<1>
DQA1_<2>
DQA1_<2>
DQA1_<3>
DQA1_<3>
DQA1_<4>
DQA1_<4>
DQA1_<5>
DQA1_<5>
DQA1_<6>
DQA1_<6>
DQA1_<7>
DQA1_<7>
DQA1_<8>
DQA1_<8>
DQA1_<9>
DQA1_<9>
DQA1_<10>
DQA1_<10>
DQA1_<11>
DQA1_<11>
DQA1_<12>
DQA1_<12>
DQA1_<13>
DQA1_<13>
DQA1_<14>
DQA1_<14>
DQA1_<15>
DQA1_<15>
DQA1_<16>
DQA1_<16>
DQA1_<17>
DQA1_<17>
DQA1_<18>
DQA1_<18>
DQA1_<19>
DQA1_<19>
DQA1_<20>
DQA1_<20>
DQA1_<21>
DQA1_<21>
DQA1_<22>
DQA1_<22>
DQA1_<23>
DQA1_<23>
DQA1_<24>
DQA1_<24>
DQA1_<25>
DQA1_<25>
DQA1_<26>
DQA1_<26>
DQA1_<27>
DQA1_<27>
DQA1_<28>
DQA1_<28>
DQA1_<29>
DQA1_<29>
DQA1_<30>
DQA1_<30>
DQA1_<31>
DQA1_<31>
5
5
MAA1_<0>
3
MAA1_<0>
3
MAA1_<1>
MAA1_<1>
MAA1_<2>
MAA1_<2>
MAA1_<3>
MAA1_<3>
MAA1_<4>
MAA1_<4>
MAA1_<5>
MAA1_<5>
MAA1_<6>
MAA1_<6>
MAA1_<7>
MAA1_<7>
MAA1_<8>
MAA1_<8>
WCKA1_0
WCKA1_0
WCKA1b_0
WCKA1b_0
WCKA1_1
WCKA1_1
WCKA1b_1
WCKA1b_1
EDCA1_0
EDCA1_0
EDCA1_1
EDCA1_1
EDCA1_2
EDCA1_2
EDCA1_3
EDCA1_3
DDBIA1_0
DDBIA1_0
DDBIA1_1
DDBIA1_1
DDBIA1_2
DDBIA1_2
DDBIA1_3
DDBIA1_3
CSA1b_0
CSA1b_0
CASA1b
CASA1b
RASA1b
RASA1b
WEA1b
WEA1b
CKEA1
CKEA1
CLKA1
CLKA1
MVREF_A
MVREF_A
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DQA1_<31..0>DQA0_<31..0>
DQA1_<31..0>DQA0_<31..0>
MAA1_<9..0>
MAA1_<9..0>
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
5
5
BI
BI
5
5
5
5
5
5
5
5
5
5
5
5
+MVDD
+MVDD
R3602
R3602
40.2R
40.2R
1%
1%
BI
5 3
5 3
5 3
5 3 5 3
5 3 5 3
5 3
5 3
5 3
BIBI
R3601
R3601
DQB0_<31..0>
MAB0_<9..0>
MAB0_<9..0>
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
1%120R
1%120R
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEM_CALRB
MEM_CALRB
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
5
5
DQB0_<0>
3
DQB0_<0>
3
DQB0_<1>
DQB0_<1>
DQB0_<2>
DQB0_<2>
DQB0_<3>
DQB0_<3>
DQB0_<4>
DQB0_<4>
DQB0_<5>
DQB0_<5>
DQB0_<6>
DQB0_<6>
DQB0_<7>
DQB0_<7>
DQB0_<8>
DQB0_<8>
DQB0_<9>
DQB0_<9>
DQB0_<10>
DQB0_<10>
DQB0_<11>
DQB0_<11>
DQB0_<12>
DQB0_<12>
DQB0_<13>
DQB0_<13>
DQB0_<14>
DQB0_<14>
DQB0_<15>
DQB0_<15>
DQB0_<16>
DQB0_<16>
DQB0_<17>
DQB0_<17>
DQB0_<18>
DQB0_<18>
DQB0_<19>
DQB0_<19>
DQB0_<20>
DQB0_<20>
DQB0_<21>
DQB0_<21>
DQB0_<22>
DQB0_<22>
DQB0_<23>
DQB0_<23>
DQB0_<24>
DQB0_<24>
DQB0_<25>
DQB0_<25>
DQB0_<26>
DQB0_<26>
DQB0_<27>
DQB0_<27>
DQB0_<28>
DQB0_<28>
DQB0_<29>
DQB0_<29>
DQB0_<30>
DQB0_<30>
DQB0_<31>
DQB0_<31>
5
5
3
MAB0_<0>
MAB0_<0>
3
MAB0_<1>
MAB0_<1>
MAB0_<2>
MAB0_<2>
MAB0_<3>
MAB0_<3>
MAB0_<4>
MAB0_<4>
MAB0_<5>
MAB0_<5>
MAB0_<6>
MAB0_<6>
MAB0_<7>
MAB0_<7>
MAB0_<8>
MAB0_<8>
WCKB0_0
WCKB0_0
WCKB0b_0
WCKB0b_0
WCKB0_1
WCKB0_1
WCKB0b_1
WCKB0b_1
EDCB0_0
EDCB0_0
EDCB0_1
EDCB0_1
EDCB0_2
EDCB0_2
EDCB0_3
EDCB0_3
DDBIB0_0
DDBIB0_0
DDBIB0_1
DDBIB0_1
DDBIB0_2
DDBIB0_2
DDBIB0_3
DDBIB0_3
ADBIB0
ADBIB0
CSB0b_0
CSB0b_0
CASB0b
CASB0b
RASB0b
RASB0b
WEB0b
WEB0b
CKEB0
CKEB0
CLKB0
CLKB0
CLKB0b
CLKB0b
K26
K26
E25
E25
F25
F25
H25
H25
J24
J24
D23
D23
E23
E23
G23
G23
E21
E21
J20
J20
G20
G20
F20
F20
E19
E19
F19
F19
E18
E18
D18
D18
C20
C20
A20
A20
D20
D20
B19
B19
B18
B18
A17
A17
C17
C17
D17
D17
A26
A26
B26
B26
C25
C25
B25
B25
A24
A24
A23
A23
B23
B23
D21
D21
H23
H23
N24
N24
K24
K24
M24
M24
L25
L25
M25
M25
N23
N23
L23
L23
K23
K23
J27
J27
G21
G21
H21
H21
A21
A21
B21
B21
F24
F24
J19
J19
A18
A18
D24
D24
G24
G24
H19
H19
C19
C19
C24
C24
P26
P26
N26
N26
P15
P15
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB0_8
WCKB0_0
WCKB0B_0
WCKB0_1
WCKB0B_1
EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3
ADBIB0
CSB0B_0
CASB0B
RASB0B
WEB0B
CKEB0
CLKB0
CLKB0B
MEM_CALRB
U1
U1
PART 4 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
B
DQB1_0
3 5
3 5
DQB1_1
3 5
3 5
DQB1_2
3 5
3 5
DQB1_3
3 5
3 5
DQB1_4
3 5
3 5
DQB1_5
3 5
3 5
DQB1_6
3 5
3 5
DQB1_7
3 5
3 5
DQB1_8
3 5
3 5
DQB1_9
3 5
3 5
DQB1_10
3 5
3 5
DQB1_11
3 5
3 5
DQB1_12
3 5
3 5
DQB1_13
3 5
3 5
DQB1_14
3 5
3 5
DQB1_15
3 5
3 5
DQB1_16
3 5
3 5
DQB1_17
3 5
3 5
DQB1_18
3 5
3 5
DQB1_19
3 5
3 5
DQB1_20
3 5
3 5
DQB1_21
3 5
3 5
DQB1_22
3 5
3 5
DQB1_23
3 5
3 5
DQB1_24
3 5
3 5
DQB1_25
3 5
3 5
DQB1_26
3 5
3 5
DQB1_27
3 5
3 5
DQB1_28
3 5
3 5
DQB1_29
3 5
3 5
DQB1_30
3 5
3 5
DQB1_31
MAB1_0
3 5
3 5
MAB1_1
3 5
3 5
MAB1_2
3 5
3 5
MAB1_3
3 5
3 5
MAB1_4
3 5
3 5
MAB1_5
3 5
3 5
MAB1_6
3 5
3 5
MAB1_7
3 5
3 5
MAB1_8
MAB1_9MAB0_9
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3
ADBIB1
CSB1B_0
CASB1B
RASB1B
WEB1B
CKEB1
CLKB1
CLKB1B
MVREFDB
G18
G18
H18
H18
F17
F17
G17
G17
F15
F15
H15
H15
D14
D14
E14
E14
J12
J12
E11
E11
F11
F11
H11
H11
E9
E9
G9
G9
H9
H9
F8
F8
B15
B15
C15
C15
A14
A14
B14
B14
D12
D12
B11
B11
C11
C11
A9
A9
C8
C8
D8
D8
C6
C6
B6
B6
D5
D5
C4
C4
B4
B4
A3
A3
N18
N18
K17
K17
N17
N17
M17
M17
L15
L15
J15
J15
P19
P19
K18
K18
L18
L18
K14
K14
F12
F12
G12
G12
A8
A8
B9
B9
E15
E15
D9
D9
A12
A12
B5
B5
J17
J17
J11
J11
C12
C12
A5
A5
L19L21
L19L21
K12L26
K12L26
M19K21
M19K21
M20K20
M20K20
M15J25
M15J25
N20N21
N20N21
H14
H14
G14
G14
P20
P20
5
5
3
DQB1_<0>
DQB1_<0>
3
DQB1_<1>
DQB1_<1>
DQB1_<2>
DQB1_<2>
DQB1_<3>
DQB1_<3>
DQB1_<4>
DQB1_<4>
DQB1_<5>
DQB1_<5>
DQB1_<6>
DQB1_<6>
DQB1_<7>
DQB1_<7>
DQB1_<8>
DQB1_<8>
DQB1_<9>
DQB1_<9>
DQB1_<10>
DQB1_<10>
DQB1_<11>
DQB1_<11>
DQB1_<12>
DQB1_<12>
DQB1_<13>
DQB1_<13>
DQB1_<14>
DQB1_<14>
DQB1_<15>
DQB1_<15>
DQB1_<16>
DQB1_<16>
DQB1_<17>
DQB1_<17>
DQB1_<18>
DQB1_<18>
DQB1_<19>
DQB1_<19>
DQB1_<20>
DQB1_<20>
DQB1_<21>
DQB1_<21>
DQB1_<22>
DQB1_<22>
DQB1_<23>
DQB1_<23>
DQB1_<24>
DQB1_<24>
DQB1_<25>
DQB1_<25>
DQB1_<26>
DQB1_<26>
DQB1_<27>
DQB1_<27>
DQB1_<28>
DQB1_<28>
DQB1_<29>
DQB1_<29>
DQB1_<30>
DQB1_<30>
DQB1_<31>
DQB1_<31>
5
5
MAB1_<0>
3
MAB1_<0>
3
MAB1_<1>
MAB1_<1>
MAB1_<2>
MAB1_<2>
MAB1_<3>
MAB1_<3>
MAB1_<4>
MAB1_<4>
MAB1_<5>
MAB1_<5>
MAB1_<6>
MAB1_<6>
MAB1_<7>
MAB1_<7>
MAB1_<8>
MAB1_<8>
WCKB1_0
WCKB1_0
WCKB1b_0
WCKB1b_0
WCKB1_1
WCKB1_1
WCKB1b_1
WCKB1b_1
EDCB1_0
EDCB1_0
EDCB1_1
EDCB1_1
EDCB1_2
EDCB1_2
EDCB1_3
EDCB1_3
DDBIB1_0
DDBIB1_0
DDBIB1_1
DDBIB1_1
DDBIB1_2
DDBIB1_2
DDBIB1_3
DDBIB1_3
ADBIB1
ADBIB1
CSB1b_0
CSB1b_0
CASB1b
CASB1b
RASB1b
RASB1b
WEB1b
WEB1b
CKEB1
CKEB1
CLKB1
CLKB1
CLKB1b
CLKB1b
MVREF_B
MVREF_B
DQB1_<31..0>
DQB1_<31..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
+MVDD
+MVDD
R3603
R3603
40.2R
40.2R
1%
1%
BI
5 3
5 3
DD
C
BB
A
21
21
OUT
DRAM_RSTA
DRAM_RSTA
W30
W30
DRAM_RSTA
REV 0.90
ellesmere_l4
ellesmere_l4
MVREFD/S = 0.7 * VDDR1
MVREFD/S = 0.7 * VDDR1
R3606
C3602 R3607
R3606
C3602 R3607
100R
1uF
100R
1uF
6.3V 1%
6.3V 1%
M14
M14
DRAM_RSTB
R3630
DRAM_RST1
OUT
DRAM_RST1
5
5
R3630
49.9R 1%
49.9R 1%
R3615
R3615
C3607
C3607
120pF
120pF
50V
50V
DRAM_RST1_RDRAM_RST1_RR
10R 1%
10R 1%
DRAM_RST1_RDRAM_RST1_RR
R3612
R3612
5.1K
5.1K
1%
1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
ELLESMERE MEM CH AB
ELLESMERE MEM CH AB
REV 0.90
Wed Apr 13 17:02:15 2016 1.0
Wed Apr 13 17:02:15 2016 1.0
ellesmere_l4
ellesmere_l4
3 26
3 26
OF
105_D009XX_00
105_D009XX_00
MVREFD/S = 0.7 * VDDR1
MVREFD/S = 0.7 * VDDR1
REV:
C3603
C3603
100R
1uF
100R
1uF
1%
6.3V
1%
6.3V
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
A
8
7
6
5
4
3
2
1
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
REV 0.90
D
K
N
A
B
E
C
A
F
R
E
T
N
I
Y
R
O
M
E
M
PART 6 OF 18
DRAM_RSTD
MEM_CALRD
MAD1_9MAD0_9
CLKD1B
CLKD1
CKED1
WCKD1B_1
WCKD1_1
WCKD1B_0
WCKD1_0
ADBID1
RASD1B
CASD1B
CSD1B_0
WED1B
DDBID1_3
DDBID1_2
DDBID1_1
DDBID1_0
EDCD1_3
EDCD1_2
EDCD1_1
EDCD1_0
MVREFDD
CLKD0B
CLKD0
CKED0
RASD0B
CASD0B
CSD0B_0
WED0B
DDBID0_3
DDBID0_2
DDBID0_1
DDBID0_0
EDCD0_3
EDCD0_2
EDCD0_1
EDCD0_0
WCKD0B_1
WCKD0_1
WCKD0B_0
WCKD0_0
ADBID0
MAD0_8
MAD0_7
MAD0_6
MAD0_5
MAD0_4
MAD0_3
MAD0_2
MAD0_1
MAD0_0
MAD1_8
MAD1_7
MAD1_6
MAD1_5
MAD1_4
MAD1_3
MAD1_2
MAD1_1
MAD1_0
DQD1_31
DQD1_30
DQD1_29
DQD1_28
DQD1_27
DQD1_26
DQD1_25
DQD1_24
DQD1_23
DQD1_22
DQD1_21
DQD1_20
DQD1_19
DQD1_18
DQD1_17
DQD1_16
DQD1_15
DQD1_14
DQD1_13
DQD1_12
DQD1_11
DQD1_10
DQD1_9
DQD1_8
DQD1_7
DQD1_6
DQD1_5
DQD1_4
DQD1_3
DQD1_2
DQD1_1
DQD1_0
DQD0_31
DQD0_30
DQD0_29
DQD0_28
DQD0_27
DQD0_26
DQD0_25
DQD0_24
DQD0_23
DQD0_22
DQD0_21
DQD0_20
DQD0_19
DQD0_18
DQD0_17
DQD0_16
DQD0_15
DQD0_14
DQD0_13
DQD0_12
DQD0_11
DQD0_10
DQD0_9
DQD0_8
DQD0_7
DQD0_6
DQD0_5
DQD0_4
DQD0_3
DQD0_2
DQD0_1
DQD0_0
REV 0.90
C
K
N
A
B
E
C
A
F
R
E
T
N
I
Y
R
O
M
E
M
PART 5 OF 18
DRAM_RSTC
MEM_CALRC
MAC1_9MAC0_9
CLKC1B
CLKC1
CKEC1
WCKC1B_1
WCKC1_1
WCKC1B_0
WCKC1_0
ADBIC1
RASC1B
CASC1B
CSC1B_0
WEC1B
DDBIC1_3
DDBIC1_2
DDBIC1_1
DDBIC1_0
EDCC1_3
EDCC1_2
EDCC1_1
EDCC1_0
MVREFDC
CLKC0B
CLKC0
CKEC0
RASC0B
CASC0B
CSC0B_0
WEC0B
DDBIC0_3
DDBIC0_2
DDBIC0_1
DDBIC0_0
EDCC0_3
EDCC0_2
EDCC0_1
EDCC0_0
WCKC0B_1
WCKC0_1
WCKC0B_0
WCKC0_0
ADBIC0
MAC0_8
MAC0_7
MAC0_6
MAC0_5
MAC0_4
MAC0_3
MAC0_2
MAC0_1
MAC0_0
MAC1_8
MAC1_7
MAC1_6
MAC1_5
MAC1_4
MAC1_3
MAC1_2
MAC1_1
MAC1_0
DQC1_31
DQC1_30
DQC1_29
DQC1_28
DQC1_27
DQC1_26
DQC1_25
DQC1_24
DQC1_23
DQC1_22
DQC1_21
DQC1_20
DQC1_19
DQC1_18
DQC1_17
DQC1_16
DQC1_15
DQC1_14
DQC1_13
DQC1_12
DQC1_11
DQC1_10
DQC1_9
DQC1_8
DQC1_7
DQC1_6
DQC1_5
DQC1_4
DQC1_3
DQC1_2
DQC1_1
DQC1_0
DQC0_31
DQC0_30
DQC0_29
DQC0_28
DQC0_27
DQC0_26
DQC0_25
DQC0_24
DQC0_23
DQC0_22
DQC0_21
DQC0_20
DQC0_19
DQC0_18
DQC0_17
DQC0_16
DQC0_15
DQC0_14
DQC0_13
DQC0_12
DQC0_11
DQC0_10
DQC0_9
DQC0_8
DQC0_7
DQC0_6
DQC0_5
DQC0_4
DQC0_3
DQC0_2
DQC0_1
DQC0_0
OUT
OUT
OUT
OUT
OUTBIBIBIBI
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBI
BI
8
7
6
345
2
1
C
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
6
6
4
DQC0_<0>
DQC0_<0>
4
DQC0_<1>
DQC0_<1>
DQC0_<2>
DQC0_<2>
DQC0_<3>
DQC0_<3>
DQC0_<4>
DQC0_<4>
DQC0_<5>
DQC0_<5>
DQC0_<6>
DQC0_<6>
DQC0_<7>
DQC0_<7>
DQC0_<8>
DQC0_<8>
DQC0_<9>
DQC0_<9>
DQC0_<10>
DQC0_<10>
DQC0_<11>
DQC0_<11>
DQC0_<12>
DQC0_<12>
DQC0_<13>
DQC0_<13>
DQC0_<14>
DQC0_<14>
DQC0_<15>
DQC0_<15>
DQC0_<16>
DQC0_<16>
DQC0_<17>
DQC0_<17>
DQC0_<18>
DQC0_<18>
DQC0_<19>
DQC0_<19>
DQC0_<20>
DQC0_<20>
DQC0_<21>
DQC0_<21>
DQC0_<22>
DQC0_<22>
DQC0_<23>
DQC0_<23>
DQC0_<24>
DQC0_<24>
DQC0_<25>
DQC0_<25>
DQC0_<26>
DQC0_<26>
DQC0_<27>
DQC0_<27>
DQC0_<28>
DQC0_<28>
DQC0_<29>
DQC0_<29>
DQC0_<30>
DQC0_<30>
DQC0_<31>
DQC0_<31>
6
6
MAC0_<0>
MAC0_<0>
4
4
MAC0_<1>
MAC0_<1>
MAC0_<2>
MAC0_<2>
MAC0_<3>
MAC0_<3>
MAC0_<4>
MAC0_<4>
MAC0_<5>
MAC0_<5>
MAC0_<6>
MAC0_<6>
MAC0_<7>
MAC0_<7>
MAC0_<8>
MAC0_<8>
WCKC0_0
WCKC0_0
WCKC0b_0
WCKC0b_0
WCKC0_1
WCKC0_1
WCKC0b_1
WCKC0b_1
EDCC0_0
EDCC0_0
EDCC0_1
EDCC0_1
EDCC0_2
EDCC0_2
EDCC0_3
EDCC0_3
DDBIC0_0
DDBIC0_0
DDBIC0_1
DDBIC0_1
DDBIC0_2
DDBIC0_2
DDBIC0_3
DDBIC0_3
ADBIC0
ADBIC0
CSC0b_0
CSC0b_0
CASC0b
CASC0b
RASC0b
RASC0b
WEC0b
WEC0b
CKEC0
CKEC0
CLKC0
CLKC0
CLKC0b
CLKC0b
V13
V13
U10
U10
U13
U13
U12
U12
R11
R11
W14
W14
V10
V10
V11
V11
P10
P10
C1
C1
D2
D2
D3
D3
E4
E4
F2
F2
F3
F3
H4
H4
H3
H3
J1
J1
L3
L3
L2
L2
M4
M4
P2
P2
P1
P1
R3
R3
R2
R2
H6
H6
J8
J8
J7
J7
J5
J5
L8
L8
L6
L6
L5
L5
M9
M9
P5
P5
P4
P4
R8
R8
R6
R6
U7
U7
U6
U6
V8
V8
V7
V7
R9
R9
H1
H1
J2
J2
M6
M6
M7
M7
E2
E2
M1
M1
J4
J4
R5
R5
E1
E1
M3
M3
L9
L9
U9
U9
P8
P8
P7
P7
DQC0_0
DQC0_1
DQC0_2
DQC0_3
DQC0_4
DQC0_5
DQC0_6
DQC0_7
DQC0_8
DQC0_9
DQC0_10
DQC0_11
DQC0_12
DQC0_13
DQC0_14
DQC0_15
DQC0_16
DQC0_17
DQC0_18
DQC0_19
DQC0_20
DQC0_21
DQC0_22
DQC0_23
DQC0_24
DQC0_25
DQC0_26
DQC0_27
DQC0_28
DQC0_29
DQC0_30
DQC0_31
MAC0_0
MAC0_1
MAC0_2
MAC0_3
MAC0_4
MAC0_5
MAC0_6
MAC0_7
MAC0_8
WCKC0_0
WCKC0B_0
WCKC0_1
WCKC0B_1
EDCC0_0
EDCC0_1
EDCC0_2
EDCC0_3
DDBIC0_0
DDBIC0_1
DDBIC0_2
DDBIC0_3
ADBIC0
CSC0B_0
CASC0B
RASC0B
WEC0B
CKEC0
CLKC0
CLKC0B
MEM_CALRC
U1
U1
PART 5 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
C
WCKC1B_0
WCKC1B_1
DDBIC1_0
DDBIC1_1
DDBIC1_2
DDBIC1_3
(4) ELLESMERE MEM INTERFACE CH C/D
(4) ELLESMERE MEM INTERFACE CH C/D
DQC0_<31..0>
DQC0_<31..0> DQD0_<31..0>
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
6
4 6
4
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
MAC0_<9..0>
6 4 6 4
6 4 6 4
MAC0_<9..0> MAC1_<9..0>
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
MEM_CALRC
120R 1%
120R 1%
MEM_CALRC
6 4 6 4
6 4 6 4
R3614
R3614
DQC1_0
4 6
4 6
DQC1_1
4 6
4 6
DQC1_2
4 6
4 6
DQC1_3
4 6
4 6
DQC1_4
4 6
4 6
DQC1_5
4 6
4 6
DQC1_6
4 6
4 6
DQC1_7
4 6
4 6
DQC1_8
4 6
4 6
DQC1_9
4 6
4 6
DQC1_10
4 6
4 6
DQC1_11
4 6
4 6
DQC1_12
4 6
4 6
DQC1_13
4 6
4 6
DQC1_14
4 6
4 6
DQC1_15
4 6
4 6
DQC1_16
4 6
4 6
DQC1_17
4 6
4 6
DQC1_18
4 6
4 6
DQC1_19
4 6
4 6
DQC1_20
4 6
4 6
DQC1_21
4 6
4 6
DQC1_22
4 6
4 6
DQC1_23
4 6
4 6
DQC1_24
4 6
4 6
DQC1_25
4 6
4 6
DQC1_26
4 6
4 6
DQC1_27
4 6
4 6
DQC1_28
4 6
4 6
DQC1_29
4 6
4 6
DQC1_30
DQC1_31
MAC1_0
MAC1_1
MAC1_2
MAC1_3
MAC1_4
MAC1_5
MAC1_6
MAC1_7
MAC1_8
MAC1_9MAC0_9
WCKC1_0
WCKC1_1
EDCC1_0
EDCC1_1
EDCC1_2
EDCC1_3
ADBIC1
CSC1B_0
CASC1B
RASC1B
WEC1B
CKEC1
CLKC1
CLKC1B
MVREFDC
DQD0_<31..0>
BIBI BI BI
MAD0_<9..0>
MAD0_<9..0>
1%
1%
MEM_CALRD
R3639
R3639
MEM_CALRD
4 6
DQD0_<0>
DQD0_<0>
4 6
0
0
4 6
DQD0_<1>
DQD0_<1>
4 6
1
1
4 6
DQD0_<2>
DQD0_<2>
4 6
2
2
4 6
DQD0_<3>
DQD0_<3>
4 6
3
3
4 6
DQD0_<4>
DQD0_<4>
4 6
4
4
DQD0_<5>
4 6
DQD0_<5>
4 6
5
5
DQD0_<6>
DQD0_<6>
4 6
4 6
6
6
4 6
DQD0_<7>
DQD0_<7>
4 6
7
7
4 6
DQD0_<8>
DQD0_<8>
4 6
8
8
4 6
DQD0_<9>
DQD0_<9>
4 6
9
9
4 6
DQD0_<10>
DQD0_<10>
4 6
10
10
DQD0_<11>
DQD0_<11>
4 6
4 6
11
11
DQD0_<12>
DQD0_<12>
4 6
4 6
12
12
4 6
DQD0_<13>
DQD0_<13>
4 6
13
13
4 6
DQD0_<14>
DQD0_<14>
4 6
14
14
4 6
DQD0_<15>
DQD0_<15>
4 6
15
15
4 6
DQD0_<16>
DQD0_<16>
4 6
16
16
4 6
DQD0_<17>
DQD0_<17>
4 6
17
17
4 6
DQD0_<18>
DQD0_<18>
4 6
18
18
4 6
DQD0_<19>
DQD0_<19>
4 6
19
19
4 6
DQD0_<20>
DQD0_<20>
4 6
20
20
4 6
DQD0_<21>
DQD0_<21>
4 6
21
21
4 6
DQD0_<22>
DQD0_<22>
4 6
22
22
4 6
DQD0_<23>
DQD0_<23>
4 6
23
23
4 6
DQD0_<24>
DQD0_<24>
4 6
24
24
4 6
DQD0_<25>
DQD0_<25>
4 6
25
25
4 6
DQD0_<26>
DQD0_<26>
4 6
26
26
4 6
DQD0_<27>
DQD0_<27>
4 6
27
27
4 6
DQD0_<28>
DQD0_<28>
4 6
28
28
4 6
DQD0_<29>
DQD0_<29>
4 6
29
29
4 6
DQD0_<30>
DQD0_<30>
4 6
30
30
4 6
DQD0_<31>
DQD0_<31>
4 6
31
31
MAD0_<0>
4 6
MAD0_<0>
4 6
0
0
MAD0_<1>
4 6
MAD0_<1>
4 6
1
1
MAD0_<2>
4 6
MAD0_<2>
4 6
2
2
MAD0_<3>
4 6
MAD0_<3>
4 6
3
3
MAD0_<4>
4 6
MAD0_<4>
4 6
4
4
MAD0_<5>
MAD0_<5>
4 6
4 6
5
5
MAD0_<6>
MAD0_<6>
4 6
4 6
6
6
MAD0_<7>
MAD0_<7>
4 6
4 6
7
7
MAD0_<8>
MAD0_<8>
4 6
4 6
8
8
WCKD0_0
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
6
6
OUT
WCKD0_0
WCKD0b_0
WCKD0b_0
WCKD0_1
WCKD0_1
WCKD0b_1
WCKD0b_1
EDCD0_0
EDCD0_0
EDCD0_1
EDCD0_1
EDCD0_2
EDCD0_2
EDCD0_3
EDCD0_3
DDBID0_0
DDBID0_0
DDBID0_1
DDBID0_1
DDBID0_2
DDBID0_2
DDBID0_3
DDBID0_3
ADBID0
ADBID0
CSD0b_0
CSD0b_0
CASD0b
CASD0b
RASD0b
RASD0b
WED0b
WED0b
CKED0
CKED0
CLKD0
CLKD0
CLKD0b
CLKD0b
AF7
AF7
AF5
AF5
AF4
AF4
AG6
AG6
AJ6
AJ6
AJ5
AJ5
AJ9
AJ9
AK7
AK7
AM7
AM7
AM6
AM6
AN6
AN6
AN5
AN5
AR7
AR7
AT6
AT6
AT8
AT8
AV5
AV5
AG1
AG1
AG3
AG3
AG4
AG4
AJ2
AJ2
AK2
AK2
AM4
AM4
AM3
AM3
AM1
AM1
AR1
AR1
AR2
AR2
AT1
AT1
AT3
AT3
AV3
AV3
AW1
AW1
AY2
AY2
BA1
BA1
AN8
AN8
AM12
AM12
AM9
AM9
AM10
AM10
AK10
AK10
AK11
AK11
AR8
AR8
AN11
AN11
AN9
AN9
AG13 AK19
AG13
AG13
AG13
AK4
AK4
AK5
AK5
AN2
AN2
AN3
AN3
AG7
AG7
AR4
AR4
AJ3
AJ3
AV2
AV2
AJ8
AJ8
AR5
AR5
AK1
AK1
AT4
AT4
AJ12
AJ12
AJ11
AJ11
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
AA4
AA4
AC2
AC2
AC1
AC1
AD1
AD1
AE3
AE3
AE2
AE2
AF2
AF2
AF1
AF1
U4
U4
U3
U3
U1
U1
V2
V2
W2
W2
Y4
Y4
Y1
Y1
Y3
Y3
V4
V4
V5
V5
W6
W6
W5
W5
Y6
Y6
Y7
Y7
Y9
Y9
AA5
AA5
AC7
AC7
AC5
AC5
AC4
AC4
AD9
AD9
AE8
AE8
AE6
AE6
AE5
AE5
AF10
AF10
AC8
AC8
AD13
AD13
AD10
AD10
AD12
AD12
AE11
AE11
AE12
AE12
AC13
AC13
AC11
AC11
AC10
AC10
AG9
AG9
AA1
AA1
AA2
AA2
AA7
AA7
AA8
AA8
AD4
AD4
V1
V1
W9
W9
AD6
AD6
AD3
AD3
W3
W3
W8
W8
AD7
AD7
AA11W11
AA11W11
AF11M10
AF11M10
AA10W12
AA10W12
Y10Y12
Y10Y12
AE9R12
AE9R12
AA13Y13
AA13Y13
AF14
AF14
AF13
AF13
Y14R14
Y14R14
6
6
DQC1_<0>
DQC1_<0>
4
4
DQC1_<1>
DQC1_<1>
DQC1_<2>
DQC1_<2>
DQC1_<3>
DQC1_<3>
DQC1_<4>
DQC1_<4>
DQC1_<5>
DQC1_<5>
DQC1_<6>
DQC1_<6>
DQC1_<7>
DQC1_<7>
DQC1_<8>
DQC1_<8>
DQC1_<9>
DQC1_<9>
DQC1_<10>
DQC1_<10>
DQC1_<11>
DQC1_<11>
DQC1_<12>
DQC1_<12>
DQC1_<13>
DQC1_<13>
DQC1_<14>
DQC1_<14>
DQC1_<15>
DQC1_<15>
DQC1_<16>
DQC1_<16>
DQC1_<17>
DQC1_<17>
DQC1_<18>
DQC1_<18>
DQC1_<19>
DQC1_<19>
DQC1_<20>
DQC1_<20>
DQC1_<21>
DQC1_<21>
DQC1_<22>
DQC1_<22>
DQC1_<23>
DQC1_<23>
DQC1_<24>
DQC1_<24>
DQC1_<25>
DQC1_<25>
DQC1_<26>
DQC1_<26>
DQC1_<27>
DQC1_<27>
DQC1_<28>
DQC1_<28>
DQC1_<29>
DQC1_<29>
DQC1_<30>
DQC1_<30>
DQC1_<31>
DQC1_<31>
6
6
MAC1_<0>
MAC1_<0>
4
4
MAC1_<1>
MAC1_<1>
MAC1_<2>
MAC1_<2>
MAC1_<3>
MAC1_<3>
MAC1_<4>
MAC1_<4>
MAC1_<5>
MAC1_<5>
MAC1_<6>
MAC1_<6>
MAC1_<7>
MAC1_<7>
MAC1_<8>
MAC1_<8>
WCKC1_0
WCKC1_0
WCKC1b_0
WCKC1b_0
WCKC1_1
WCKC1_1
WCKC1b_1
WCKC1b_1
EDCC1_0
EDCC1_0
EDCC1_1
EDCC1_1
EDCC1_2
EDCC1_2
EDCC1_3
EDCC1_3
DDBIC1_0
DDBIC1_0
DDBIC1_1
DDBIC1_1
DDBIC1_2
DDBIC1_2
DDBIC1_3
DDBIC1_3
ADBIC1
ADBIC1
CSC1b_0
CSC1b_0
CASC1b
CASC1b
RASC1b
RASC1b
WEC1b
WEC1b
CKEC1
CKEC1
CLKC1
CLKC1
CLKC1b
CLKC1b
MVREF_C
MVREF_C
DQC1_<31..0>
DQC1_<31..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
MAC1_<9..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6 4
6 4
6 4
6 4
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
BI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
+MVDD +MVDD
+MVDD +MVDD
R3618 R3619
R3618 R3619
40.2R
40.2R
1%
1%
2 1
2 1
120R
120R
DQD0_0
DQD0_1
DQD0_2
DQD0_3
DQD0_4
DQD0_5
DQD0_6
DQD0_7
DQD0_8
DQD0_9
DQD0_10
DQD0_11
DQD0_12
DQD0_13
DQD0_14
DQD0_15
DQD0_16
DQD0_17
DQD0_18
DQD0_19
DQD0_20
DQD0_21
DQD0_22
DQD0_23
DQD0_24
DQD0_25
DQD0_26
DQD0_27
DQD0_28
DQD0_29
DQD0_30
DQD0_31
MAD0_0
MAD0_1
MAD0_2
MAD0_3
MAD0_4
MAD0_5
MAD0_6
MAD0_7
MAD0_8
WCKD0_0
WCKD0B_0
WCKD0_1
WCKD0B_1
EDCD0_0
EDCD0_1
EDCD0_2
EDCD0_3
DDBID0_0
DDBID0_1
DDBID0_2
DDBID0_3
ADBID0
CSD0B_0
CASD0B
RASD0B
WED0B
CKED0
CLKD0
CLKD0B
MEM_CALRD
?
?
U1
U1
PART 6 OF 18
M
E
M
O
R
Y
I
N
T
E
R
F
A
C
E
B
A
N
K
D
DQD1_0
4 6
4 6
DQD1_1
4 6
4 6
DQD1_2
4 6
4 6
DQD1_3
4 6
4 6
DQD1_4
4 6
4 6
DQD1_5
4 6
4 6
DQD1_6
DQD1_7
DQD1_8
DQD1_9
DQD1_10
DQD1_11
DQD1_12
DQD1_13
DQD1_14
DQD1_15
4 6
4 6
DQD1_16
4 6
4 6
DQD1_17
4 6
4 6
DQD1_18
4 6
4 6
DQD1_19
4 6
4 6
DQD1_20
4 6
4 6
DQD1_21
4 6
4 6
DQD1_22
4 6
4 6
DQD1_23
DQD1_24
DQD1_25
DQD1_26
DQD1_27
DQD1_28
DQD1_29
DQD1_30
DQD1_31
MAD1_0
MAD1_1
MAD1_2
MAD1_3
MAD1_4
MAD1_5
MAD1_6
MAD1_7
MAD1_8
MAD1_9MAD0_9
WCKD1_0
WCKD1B_0
WCKD1_1
WCKD1B_1
EDCD1_0
EDCD1_1
EDCD1_2
EDCD1_3
DDBID1_0
DDBID1_1
DDBID1_2
DDBID1_3
ADBID1
CSD1B_0
CASD1B
RASD1B
WED1B
CKED1
CLKD1
CLKD1B
MVREFDD
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
AW3
AW3
AW4
AW4
BA5
BA5
AY5
AY5
AU9
AU9
AW9
AW9
AY9
AY9
AT11
AT11
AU12
AU12
AV12
AV12
AU14
AU14
AW14
AW14
AT15
AT15
AV15
AV15
AU17
AU17
AV17
AV17
BB4
BB4
BC3
BC3
BC5
BC5
BA6
BA6
BA8
BA8
BC8
BC8
BB9
BB9
BC9
BC9
AY12
AY12
BA12
BA12
BC12
BC12
BB14
BB14
BB15
BB15
AY17
AY17
BA17
BA17
BC17
BC17
AM17
AM17
AP17
AP17
AL18
AL18
AR17
AR17
AT18
AT18
AN18
AN18
AN15
AN15
AR15
AR15
AL17
AL17
AK19
AR19
AR19
AW11
AW11
AV11
AV11
BB11
BB11
BA11
BA11
AV8
AV8
AW15
AW15
BB6
BB6
BA15
BA15
AW6
AW6
AY14
AY14
AY8
AY8
BC14
BC14
AT14AT9
AT14AT9
AP20AG12
AP20AG12
AM15AR11
AM15AR11
AN14AR12
AN14AR12
AP18AK8
AP18AK8
AP14AP12
AP14AP12
AM19
AM19
AN19
AN19
AE14AL20
AE14AL20
6
6
4
DQD1_<0>
DQD1_<0>
4
DQD1_<1>
DQD1_<1>
DQD1_<2>
DQD1_<2>
DQD1_<3>
DQD1_<3>
DQD1_<4>
DQD1_<4>
DQD1_<5>
DQD1_<5>
DQD1_<6>
DQD1_<6>
DQD1_<7>
DQD1_<7>
DQD1_<8>
DQD1_<8>
DQD1_<9>
DQD1_<9>
DQD1_<10>
DQD1_<10>
DQD1_<11>
DQD1_<11>
DQD1_<12>
DQD1_<12>
DQD1_<13>
DQD1_<13>
DQD1_<14>
DQD1_<14>
DQD1_<15>
DQD1_<15>
DQD1_<16>
DQD1_<16>
DQD1_<17>
DQD1_<17>
DQD1_<18>
DQD1_<18>
DQD1_<19>
DQD1_<19>
DQD1_<20>
DQD1_<20>
DQD1_<21>
DQD1_<21>
DQD1_<22>
DQD1_<22>
DQD1_<23>
DQD1_<23>
DQD1_<24>
DQD1_<24>
DQD1_<25>
DQD1_<25>
DQD1_<26>
DQD1_<26>
DQD1_<27>
DQD1_<27>
DQD1_<28>
DQD1_<28>
DQD1_<29>
DQD1_<29>
DQD1_<30>
DQD1_<30>
DQD1_<31>
DQD1_<31>
MAD1_<0>
MAD1_<0>
MAD1_<1>
MAD1_<1>
MAD1_<2>
MAD1_<2>
MAD1_<3>
MAD1_<3>
MAD1_<4>
MAD1_<4>
MAD1_<5>
MAD1_<5>
MAD1_<6>
MAD1_<6>
MAD1_<7>
MAD1_<7>
MAD1_<8>
MAD1_<8>
WCKD1_0
WCKD1_0
WCKD1b_0
WCKD1b_0
WCKD1_1
WCKD1_1
WCKD1b_1
WCKD1b_1
EDCD1_0
EDCD1_0
EDCD1_1
EDCD1_1
EDCD1_2
EDCD1_2
EDCD1_3
EDCD1_3
DDBID1_0
DDBID1_0
DDBID1_1
DDBID1_1
DDBID1_2
DDBID1_2
DDBID1_3
DDBID1_3
ADBID1
ADBID1
CSD1b_0
CSD1b_0
CASD1b
CASD1b
RASD1b
RASD1b
WED1b
WED1b
CKED1
CKED1
CLKD1
CLKD1
CLKD1b
CLKD1b
MVREF_D
MVREF_D
DQD1_<31..0>
DQD1_<31..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
MAD1_<9..0>
MAD1_<9..0>
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
6 4
6 4
6 4
6 4
OUTOUTOUT OUT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
40.2R
40.2R
1%
1%
DD
C
BB
A
R3620R3621
C3611C3612
R3620R3621
P12
P12
DRAM_RSTC
REV 0.90
ellesmere_l4
ellesmere_l4
MVREFD/S = 0.7 * VDDR1 MVREFD/S = 0.7 * VDDR1
MVREFD/S = 0.7 * VDDR1 MVREFD/S = 0.7 * VDDR1
1uF
1uF
6.3V
6.3V
100R
100R
1%
1%
AK19
AK19
DRAM_RSTD
DRAM_RST2_R
1%49.9R
R3629 R3616
6
6
OUT
R3629 R3616
1%49.9R
DRAM_RST2_RRDRAM_RST2
DRAM_RST2_RRDRAM_RST2
C3617
C3617
120pF
120pF
50V
50V
10R 1%
10R 1%
DRAM_RST2_R
REV 0.90
ellesmere_l4
R3627
R3627
5.1K
5.1K
1%
1%
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
ELLESMERE MEM CH CD
ELLESMERE MEM CH CD
Wed Apr 13 17:02:15 2016 1.0
Wed Apr 13 17:02:15 2016 1.0
ellesmere_l4
4 26
4 26
OF
105_D009XX_00
105_D009XX_00
REV:
C3611C3612
1uF
100R
1uF
100R
6.3V
1%
6.3V
1%
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
A
8
7
6
5
4
3
2
1
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
+++
+
OUT
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
OUT
OUT
OUTBIBIBIBIININ
IN
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
ININININININININININININININININININBIBIBIBIOUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTININININ
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
8
7
6
345
2
1
C
A
(5) GDDR5 MEMORY CH A/B
(5) GDDR5 MEMORY CH A/B
DQA0_<31..0>
3 5
3 5
3 5
3 5
+MVDD +MVDD +MVDD
+MVDD +MVDD +MVDD
R2001
R2001
R2000
R2000
DQA0_<31..0>
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5 3 5
3 5 3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
MAA0_<8..0>
MAA0_<8..0>
OUT
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3
3
IN
3
3
IN
3
3
IN
3
3
IN
3
3
OUT
3
3
OUT
3
3
OUT
3
3
OUT
3
3
BI
3
3
BI
3
3
BI
3
3
BI
3
3
IN
3
3
IN
1%60.4R
1%60.4R
1%60.4R
1%60.4R
3
3
IN
3
3
IN
3
3
IN
3
3
IN
3
3
IN
R2002
R2002
R2003
R2003
3 5
3 5
IN
R2004
R2004
R2009
R2009
R2010
R2010
C2005
C2005
C2007
C2007
0.1uF
0.1uF
+MVDD +MVDD
+MVDD +MVDD
C2019
C2019
1uF
1uF
C2008
C2008
0.1uF
0.1uF
C2020
C2020
1uF
1uF
1uF
1uF
3
3
IN IN
C2009
C2009
C2010
C2010
0.1uF
0.1uF
0.1uF
0.1uF
C2023
C2024
C2023
C2024
1uF
1uF
1uF
1uF
28
28
31
31
29
29
30
30
27
27
26
26
24
24
25
25
17
17
23
23
16
16
22
22
18
18
21
21
19
19
20
20
5
5
6
6
4
4
7
7
3
3
2
2
1
1
0
0
11
11
10
10
8
8
9
9
12
12
13
13
15
15
14
14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
120R 1%
120R 1%
5%1K
5%1K
5%1K
5%1K
1%2.37K
1%2.37K
1%5.49K
1%5.49K
6.3V
6.3V
C2013
C2012
C2013
C2012
0.1uF
0.1uF
0.1uF
0.1uF
C2026
C2026
C2025
C2025
1uF
1uF
1uF
1uF
5
5
3
3
DQA0_<28>
DQA0_<28>
DQA0_<31>
DQA0_<31>
DQA0_<29>
DQA0_<29>
DQA0_<30>
DQA0_<30>
DQA0_<27>
DQA0_<27>
DQA0_<26>
DQA0_<26>
DQA0_<24>
DQA0_<24>
DQA0_<25>
DQA0_<25>
DQA0_<17>
DQA0_<17>
DQA0_<23>
DQA0_<23>
DQA0_<16>
DQA0_<16>
DQA0_<22>
DQA0_<22>
DQA0_<18>
DQA0_<18>
DQA0_<21>
DQA0_<21>
DQA0_<19>
DQA0_<19> DQA1_<14>
DQA0_<20>
DQA0_<20>
DQA0_<5>
DQA0_<5>
DQA0_<6>
DQA0_<6>
DQA0_<4>
DQA0_<4>
DQA0_<7>
DQA0_<7>
DQA0_<3>
DQA0_<3>
DQA0_<2>
DQA0_<2>
DQA0_<1>
DQA0_<1>
DQA0_<0>
DQA0_<0>
DQA0_<11>
DQA0_<11>
DQA0_<10>
DQA0_<10>
DQA0_<8>
DQA0_<8>
DQA0_<9>
DQA0_<9>
DQA0_<12>
DQA0_<12>
DQA0_<13>
DQA0_<13>
DQA0_<15>
DQA0_<15>
DQA0_<14>
DQA0_<14>
5
5
MAA0_<8>
3
3
MAA0_<8>
MAA0_<7>
MAA0_<7>
MAA0_<6>
MAA0_<6>
MAA0_<5>
MAA0_<5>
MAA0_<4>
MAA0_<4>
MAA0_<3>
MAA0_<3>
MAA0_<1>
MAA0_<1>
MAA0_<0>
MAA0_<0>
WCKA0_0
WCKA0_0
WCKA0b_0
WCKA0b_0
WCKA0_1
WCKA0_1
WCKA0b_1
WCKA0b_1
EDCA0_3
EDCA0_3
EDCA0_2
EDCA0_2
EDCA0_0
EDCA0_0
EDCA0_1
EDCA0_1
DDBIA0_3
DDBIA0_3
DDBIA0_2
DDBIA0_2
DDBIA0_0
DDBIA0_0
DDBIA0_1
DDBIA0_1
RASA0b
RASA0b
CASA0b
CASA0b
CKEA0
CKEA0
CLKA0b
CLKA0b
CLKA0
CLKA0
CSA0b_0
CSA0b_0
WEA0b
WEA0b
ZQ_A0
ZQ_A0
SEN_A0
SEN_A0
DRAM_RST1
DRAM_RST1
MF_A0
MF_A0
VREFC_A0
VREFC_A0
ADBIA0
ADBIA0
C2015
C2015
C2014
C2014
0.1uF
0.1uF
0.1uF
0.1uF
C2029
C2028
C2029
C2028
1uF
1uF
1uF
1uF
22uF
22uF
4V
4V
2 1
2 1
C2040
C2040
M13
M13
M11
M11
N13
N13
N11
N11
T13
T13
T11
T11
V13
V13
V11
V11
F13
F13
F11
F11
E13
E13
E11
E11
B13
B13
B11
B11
A13
A13
A11
A11
K10
K10
K11
K11
H10
H10
H11
H11
R13
R13
C13
C13
P13
P13
D13
D13
J11
J11
J12
J12
G12
G12
L12
L12
J13
J13
J10
J10
A10
A10
V10
V10
J14
J14
M2
M2
M4
M4
N2
N2
N4
N4
T2
T2
T4
T4
V2
V2
V4
V4
F2
F2
F4
F4
E2
E2
E4
E4
B2
B2
B4
B4
A2
A2
A4
A4
J5
J5
K4
K4
K5
K5
H5
H5
H4
H4
D4
D4
D5
D5
P4
P4
P5
P5
R2
R2
C2
C2
P2
P2
D2
D2
G3
G3
L3
L3
J3
J3
J2
J2
J1
J1
A5
A5
V5
V5
J4
J4
22uF
22uF
4V
4V
2 1
2 1
8
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
+MVDD
+MVDD
C2041
C2041
23CNOPN001
23CNOPN001
U2000
U2000
C2107C2118
C2107C2118
1uF 0.1uF
1uF 0.1uF
7
C2108
C2108
0.1uF
0.1uF
C2119
C2119
1uF
1uF
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
C2110
C2109
C2110
C2109
0.1uF
0.1uF
0.1uF
0.1uF
C2121
C2120
C2121
C2120
1uF
1uF
1uF
1uF
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
C2112
C2112
0.1uF
0.1uF
C2122
C2122
1uF
1uF
+MVDD
+MVDD
+MVDD
+MVDD
C2115
C2115
0.1uF
0.1uF
C2126
C2126
1uF
1uF
C2116
C2116
0.1uF
0.1uF
C2127
C2127
1uF
1uF
C2117
C2117
0.1uF
0.1uF
C2129
C2129
1uF
1uF
2 1
2 1
+MVDD+MVDD
+MVDD+MVDD
C2140
C2140
22uF
22uF
3 5
3 5
R2101
R2101
R2100
R2100
22uF
22uF
4V
4V
2 1
2 1
+MVDD
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
C2309
C2309
0.1uF
0.1uF
C2322
C2322
1uF
1uF
+MVDD
C2311
C2311
0.1uF
0.1uF
C2323
C2323
1uF
1uF
+MVDD
+MVDD
C2312
C2312
0.1uF
0.1uF
C2324
C2324
1uF
1uF
C2314
C2314
0.1uF
0.1uF
C2325
C2325
1uF
1uF
+MVDD
+MVDD
+MVDD
+MVDD
C2316
C2316
0.1uF
0.1uF
C2326
C2326
1uF
1uF
+MVDD
+MVDD
C2317
C2317
0.1uF
0.1uF
C2328
C2328
1uF
1uF
3 5
3 5
OUT
R2201
R2201
R2200
R2200
12
12
+ +++
C2361
C2361 C2364C2363C2362
470uF
470uF
2V
2V
C2340
C2340
22uF
22uF
4V
4V
2 1
2 1
DQB0_<31..0>
DQB0_<31..0>
3 5
3 5
3 5
5
3
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
MAB0_<8..0>
MAB0_<8..0>
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5 3 5
3 5 3 5
3 5
3 5
3 5
3 5
3
3
IN
3
3
IN
3
3
IN
3
3
IN
3
3
OUT
3
3
OUT
3
3
OUT
3
3
OUT
3
3
BI
3
3
BI
3
3
BI
3
3
BI
3
3
IN
3
3
IN
1%60.4R
1%60.4R
3
3
IN
3
3
IN
3
3
IN
3
3
IN
3
3
IN
3 5
3 5
IN
2.37K
2.37K
1uF
1uF
3
3
IN
Reserved. detail please check BOM
Reserved. detail please check BOM
12
12
C2362
470uF
470uF
2V
2V
C2363
470uF
470uF
2V
2V
R2209
R2209
R2210
R2210
22uF
22uF
4V
4V
2 1
2 1
C2205
C2205
60.4R 1%
60.4R 1%
R2202
R2202
R2203
R2203
R2204
R2204
12
12
C2341
C2341
1%
1%
1%5.49K
1%5.49K
6.3V
6.3V
13
13
15
15
12
12
14
14
11
11
8
8
10
10
9
9
0
0
7
7
1
1
6
6
3
3
5
5
2
2
4
4
30
30
29
29
28
28
31
31
27
27
26
26
24
24
25
25
19
19
18
18
17
17
16
16
20
20
21
21
22
22
23
23
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
1%120R
1%120R
5%1K
5%1K
5%1K
5%1K
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
DQB0_<4>
DQB0_<4>
DQB0_<30>
DQB0_<30>
DQB0_<29>
DQB0_<29>
DQB0_<28>
DQB0_<28>
DQB0_<31>
DQB0_<31>
DQB0_<27>
DQB0_<27>
DQB0_<26>
DQB0_<26>
DQB0_<24>
DQB0_<24>
3 5
3 5
3 5
3 5
DQB0_<18>
DQB0_<18>
DQB0_<17>
DQB0_<17>
DQB0_<16>
DQB0_<16>
DQB0_<20>
DQB0_<20>
DQB0_<21>
DQB0_<21>
DQB0_<22>
DQB0_<22>
DQB0_<23>
DQB0_<23>
5
5
3
3
MAB0_<8>
MAB0_<8>
MAB0_<7>
MAB0_<7>
MAB0_<6>
MAB0_<6>
MAB0_<5>
MAB0_<5>
MAB0_<4>
MAB0_<4>
MAB0_<3>
MAB0_<3>
MAB0_<2>MAA0_<2>
MAB0_<2>MAA0_<2>
MAB0_<1>
MAB0_<1>
MAB0_<0>
MAB0_<0>
WCKB0_1
WCKB0_1
WCKB0b_1
WCKB0b_1
WCKB0_0
WCKB0_0
WCKB0b_0
WCKB0b_0
DDBIB0_1
DDBIB0_1
DDBIB0_0
DDBIB0_0
DDBIB0_3
DDBIB0_3
DDBIB0_2
DDBIB0_2
RASB0b
RASB0b
CASB0b
CASB0b
CKEB0
CKEB0
CLKB0b
CLKB0b
CLKB0
CLKB0
CSB0b_0
CSB0b_0
WEB0b
WEB0b
ZQ_B0
ZQ_B0
SEN_B0
SEN_B0
DRAM_RST1
DRAM_RST1
MF_B0
MF_B0
VREFC_B0
VREFC_B0
ADBIB0
ADBIB0
12
12
4
DQB0_<13>
DQB0_<13>
DQB0_<15>
DQB0_<15>
DQB0_<12>
DQB0_<12>
DQB0_<14>
DQB0_<14>
DQB0_<11>
DQB0_<11>
DQB0_<8>
DQB0_<8>
DQB0_<10>
DQB0_<10>
DQB0_<9>
DQB0_<9>
DQB0_<0>
DQB0_<0>
DQB0_<7>
DQB0_<7>
DQB0_<1>
DQB0_<1>
DQB0_<6>
DQB0_<6>
DQB0_<3>
DQB0_<3>
DQB0_<5>
DQB0_<5>
DQB0_<2>
3 5
3 5
DQB0_<2>
DQB0_<25>
DQB0_<25>
DQB0_<19>
DQB0_<19>
EDCB0_1
EDCB0_1
EDCB0_0
EDCB0_0
EDCB0_3
EDCB0_3
EDCB0_2
EDCB0_2
C2364
470uF
470uF
2V
2V
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
23CNOPN001
23CNOPN001
U2200
U2200
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
GDDR5 MEM CH AB
GDDR5 MEM CH AB
Wed Apr 13 17:02:16 2016
Wed Apr 13 17:02:16 2016
23CNOPN001
23CNOPN001
U2100
2 1
2 1
22uF22uF
22uF22uF
4V
4V
C2241
C2241
U2100
+MVDD
+MVDD
+MVDD
+MVDD
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
C2306
C2306
C2308
C2308
0.1uF
0.1uF
0.1uF
0.1uF
C2319
C2321
C2319
C2321
1uF
1uF
1uF
1uF
5
DQA1_<31..0>
DQA1_<31..0>
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
MAA1_<8..0>
OUT
MAA1_<8..0>
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
60.4R
60.4R
60.4R 1%
60.4R 1%
3
3
3
3
3
3
3
3
3
3
R2102
R2102
R2103
R2103
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
1%
1%
IN
IN
IN
IN
IN
3 5
3 5
IN
R2104
+MVDD
+MVDD
C2141
C2141
R2104
R2109
R2109
R2110
R2110
C2105 C2305
C2105 C2305
3
3
+MVDD+MVDD+MVDD
+MVDD+MVDD+MVDD
C2206
C2206
C2208
C2208
0.1uF
0.1uF
0.1uF
0.1uF
C2219
C2220
C2219
C2220
1uF
1uF
1uF
1uF
1K 5%
1K 5%
1%2.37K
1%2.37K
1%5.49K
1%5.49K
6.3V
6.3V
C2209
C2209
0.1uF
0.1uF
C2223
C2223
1uF
1uF
5
5
6
6
4
4
7
7
3
3
2
2
1
1
0
0
11
11
8
8
10
10
9
9
12
12
13
13
14
14
15
15
31
31
24
24
29
29
25
25
28
28
26
26
30
30
27
27
18
18
17
17
19
19
16
16
21
21
23
23
20
20
22
22
8
8
0
0
1
1
3
3
2
2
5
5
4
4
6
6
7
7
3 5
3 5
5%1K
5%1K
C2211
C2211
0.1uF
0.1uF
C2226
C2226
1uF
1uF
5
5
3
3
DQA1_<5>
DQA1_<5>
DQA1_<6>
DQA1_<6>
DQA1_<4>
DQA1_<4>
DQA1_<7>
DQA1_<7>
DQA1_<3>
DQA1_<3>
DQA1_<2>
DQA1_<2>
DQA1_<1>
DQA1_<1>
DQA1_<0>
DQA1_<0>
DQA1_<11>
DQA1_<11>
DQA1_<8>
DQA1_<10>
DQA1_<10>
DQA1_<9>
DQA1_<9>
DQA1_<12>
DQA1_<12>
DQA1_<13>
DQA1_<13>
DQA1_<14>
DQA1_<15>
DQA1_<15>
DQA1_<31>
DQA1_<31>
DQA1_<24>
DQA1_<24>
DQA1_<29>
DQA1_<29>
DQA1_<25>
DQA1_<25>
DQA1_<28>
DQA1_<28>
DQA1_<26>
DQA1_<26>
DQA1_<30>
DQA1_<30>
DQA1_<27>
DQA1_<27>
DQA1_<18>
DQA1_<18>
DQA1_<17>
DQA1_<17>
DQA1_<19>
DQA1_<19>
DQA1_<16>
DQA1_<16>
DQA1_<21>
DQA1_<21>
DQA1_<23>
DQA1_<23>
DQA1_<20>
DQA1_<20>
DQA1_<22>
DQA1_<22>
5
5
3
MAA1_<8>
3
MAA1_<8>
MAA1_<0>
MAA1_<0>
MAA1_<1>
MAA1_<1>
MAA1_<3>
MAA1_<3>
MAA1_<2>
MAA1_<2>
MAA1_<5>
MAA1_<5>
MAA1_<4>
MAA1_<4>
MAA1_<6>
MAA1_<6>
MAA1_<7>
MAA1_<7>
WCKA1_1
WCKA1_1
WCKA1b_1
WCKA1b_1
WCKA1_0
WCKA1_0
WCKA1b_0
WCKA1b_0
EDCA1_0
EDCA1_0
EDCA1_1
EDCA1_1
EDCA1_3
EDCA1_3
EDCA1_2
EDCA1_2
DDBIA1_0
DDBIA1_0
DDBIA1_1
DDBIA1_1
DDBIA1_3
DDBIA1_3
DDBIA1_2
DDBIA1_2
CASA1b
CASA1b
RASA1b
RASA1b
CKEA1
CKEA1
CLKA1b
CLKA1b
CLKA1
CLKA1
WEA1b
WEA1b
CSA1b_0
CSA1b_0
ZQ_A1
ZQ_A1
1%120R
1%120R
SEN_A1
SEN_A1
DRAM_RST1
DRAM_RST1
MF_A1
MF_A1
VREFC_A1
VREFC_A1
ADBIA1
ADBIA1
C2212
C2212
0.1uF
0.1uF
C2227
C2227
1uF
1uF
C2213
C2213
0.1uF
0.1uF
C2228
C2228
1uF
1uF
C2214
C2214
0.1uF
0.1uF
C2229
C2229
1uF
1uF
M2
M2
M4
M4
N2
N2
N4
N4
T2
T2
T4
T4
V2
V2
V4
V4
M13
M13
M11
M11
N13
N13
N11
N11
T13
T13
T11
T11
V13
V13
V11
V11
F13
F13
F11
F11
E13
E13
E11
E11
B13
B13
B11
B11
A13
A13
A11
A11
F2
F2
F4
F4
E2
E2
E4
E4
B2
B2
B4
B4
A2
A2
A4
A4
J5
J5
K4
K4
K5
K5
K10
K10
K11
K11
H10
H10
H11
H11
H5
H5
H4
H4
D4
D4
D5
D5
P4
P4
P5
P5
R2
R2
R13
R13
C13
C13
C2
C2
P2
P2
P13
P13
D13
D13
D2
D2
G3
G3
L3
L3
J3
J3
J11
J11
J12
J12
G12
G12
L12
L12
J13
J13
J10
J10
J2
J2
J1
J1
A5
A5
V5
V5
A10
A10
V10
V10
J14
J14
J4
J4
C2218
C2218
0.1uF
0.1uF
C2230
C2230
1uF
1uF
4V4V
4V4V
2 1
2 1
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
C2240
C2240
6
+MVDD +MVDD
+MVDD +MVDD
3 5 3 5
OF
3 5 3 5
+MVDD
+MVDD
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
+MVDD
+MVDD
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
5 26
5 26
105_D009XX_00
105_D009XX_00
3
BIBIBIBI
3 5
3 5
OUT
R2301
R2301
R2300
R2300
+MVDD
+MVDD
DQB1_<31..0>
DQB1_<31..0>
MAB1_<8..0>
MAB1_<8..0>
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
R2302
R2302
R2303
R2303
3 5
3 5
R2304
R2304
R2309
R2309
R2310
R2310
3
3
REV:
3
3
3
3
3
3
3
3
1%60.4R
1%60.4R
1%60.4R
1%60.4R
1uF1uF
1uF1uF
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5 3 5
3 5 3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
3 5
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
120R 1%
120R 1%
IN
1K 5%
1K 5%
6.3V
6.3V
IN
21
21
22
22
20
20
23
23
19
19
18
18
17
17
16
16
26
26
27
27
24
24
25
25
28
28
30
30
31
31
29
29
15
15
8
8
14
14
10
10
12
12
9
9
13
13
11
11
2
2
0
0
3
3
1
1
4
4
7
7
5
5
6
6
8
8
0
0
1
1
3
3
2
2
5
5
4
4
6
6
7
7
5%1K
5%1K
1%2.37K
1%2.37K
1%5.49K
1%5.49K
1.0
1.0
GDDR5
GDDR5
23CNOPN001
23CNOPN001
U2300
5
5
DQB1_<21>
3
3
DQB1_<21>
DQB1_<22>
DQB1_<22>
DQB1_<20>
DQB1_<20>
DQB1_<23>
DQB1_<23>
DQB1_<19>
DQB1_<19>
DQB1_<18>
DQB1_<18>
DQB1_<17>
DQB1_<17>
DQB1_<16>
DQB1_<16>
DQB1_<26>
DQB1_<26>
DQB1_<27>DQA1_<8>
DQB1_<27>
DQB1_<24>
DQB1_<24>
DQB1_<25>
DQB1_<25>
DQB1_<28>
DQB1_<28>
DQB1_<30>
DQB1_<30>
DQB1_<31>
DQB1_<31>
DQB1_<29>
DQB1_<29>
DQB1_<15>
3 5
3 5
DQB1_<15>
DQB1_<8>
DQB1_<8>
3 5
3 5
DQB1_<14>
3 5
3 5
DQB1_<14>
DQB1_<10>
3 5
3 5
DQB1_<10>
DQB1_<12>
3 5
3 5
DQB1_<12>
DQB1_<9>
3 5
3 5
DQB1_<9>
DQB1_<13>
3 5
3 5
DQB1_<13>
DQB1_<11>
3 5
3 5
DQB1_<11>
DQB1_<2>
3 5
3 5
DQB1_<2>
DQB1_<0>
3 5
3 5
DQB1_<0>
DQB1_<3>
3 5
3 5
DQB1_<3>
DQB1_<1>
3 5
3 5
DQB1_<1>
DQB1_<4>
3 5
3 5
DQB1_<4>
DQB1_<7>
3 5
3 5
DQB1_<7>
DQB1_<5>
3 5
3 5
DQB1_<5>
DQB1_<6>
3 5
3 5
DQB1_<6>
5
5
3
3
MAB1_<8>
MAB1_<8>
MAB1_<0>
MAB1_<0>
MAB1_<1>
MAB1_<1>
MAB1_<3>
MAB1_<3>
MAB1_<2>
MAB1_<2>
MAB1_<5>
MAB1_<5>
MAB1_<4>
MAB1_<4>
MAB1_<6>
MAB1_<6>
MAB1_<7>
MAB1_<7>
WCKB1_0
WCKB1_0
WCKB1b_0
WCKB1b_0
WCKB1_1
WCKB1_1
WCKB1b_1
WCKB1b_1
EDCB1_2
EDCB1_2
EDCB1_3
EDCB1_3
EDCB1_1
EDCB1_1
EDCB1_0
EDCB1_0
DDBIB1_2
DDBIB1_2
DDBIB1_3
DDBIB1_3
DDBIB1_1
DDBIB1_1
DDBIB1_0
DDBIB1_0
CASB1b
CASB1b
RASB1b
RASB1b
CKEB1
CKEB1
CLKB1b
CLKB1b
CLKB1
CLKB1
WEB1b
WEB1b
CSB1b_0
CSB1b_0
ZQ_B1
ZQ_B1
SEN_B1
SEN_B1
DRAM_RST1
DRAM_RST1
MF_B1
MF_B1
VREFC_B1
VREFC_B1
ADBIB1
ADBIB1
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
U2300
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
+MVDD
+MVDD
2
DD
C
BB
A
1
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
INININININININININININININININININININININBIBIBIBI
OUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTINININININININININBIBIBIBIOUT
OUT
OUT
OUTININININ
OUT
OUT
OUT
OUTBIBIBIBI
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
SEN
VSSQ_V14
VSSQ_V12
VSSQ_V3
VSSQ_V1
VSSQ_R14
VSSQ_R12
VSSQ_R11
VSSQ_R4
VSSQ_R3
VSSQ_R1
VSSQ_N1
VSSQ_N14
VSSQ_N12
VSSQ_N3
VSSQ_M10
VSSQ_M5
VSSQ_K13
VSSQ_K2
VSSQ_H13
VSSQ_H2
VSSQ_F10
VSSQ_F5
VSSQ_E14
VSSQ_E12
VSSQ_E3
VSSQ_E1
VSSQ_C14
VSSQ_C12
VSSQ_C11
VSSQ_C4
VSSQ_C3
VSSQ_C1
VSSQ_A14
VSSQ_A12
VSSQ_A3
VSSQ_A1
ZQ
VREFC
VDD_R10
VDD_R5
VDD_P11
VDD_L14
VDDQ_T14
VDDQ_T12
VDDQ_T3
VDDQ_T1
VDDQ_P14
VDDQ_P12
VDDQ_P3
VDDQ_P1
VDDQ_N10
VDDQ_N5
VDDQ_M14
VDDQ_M12
VDDQ_M3
VDDQ_M1
Vpp_NC1
Vpp_NC
WCK23#__WCK01#
WCK23__WCK01
WCK01#__WCK23#
WCK01__WCK23
RFU_A12_NC
VREFD2
VREFD1
MF
VDD_L11
VDD_L4
VDDQ_L13
VDDQ_L2
VDDQ_K12
VDDQ_K3
VDDQ_H12
VDDQ_H3
WE#__CS#
VDD_L1
VDD_G14
VDD_G11
VDD_G4
VDD_G1
VDD_D11
VDD_C10
VDD_C5
VDDQ_G13
VDDQ_G2
VDDQ_F14
VDDQ_F12
VDDQ_E10
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
VDDQ_E5
VDDQ_D14
VDDQ_D12
VDDQ_D3
VDDQ_D1
VDDQ_B14
VDDQ_B12
VDDQ_B3
VDDQ_B1
A5_BA1__A3_BA3
CK#
CK
VDDQ_F1
A1_A9__A6_A11
CKE#
RESET#
A2_BA0__A4_BA2
RAS#__CAS#
A6_A11__A1_A9
A7_A8__A0_A10
A4_BA2__A2_BA0
A0_A10__A7_A8
A3_BA3__A5_BA1
CS#__WE#
CAS#__RAS#
DQ0__DQ24
DQ1__DQ25
DQ2__DQ26
DQ3__DQ27
DQ4__DQ28
DQ5__DQ29
DQ6__DQ30
DQ7__DQ31
DQ8__DQ16
DQ9__DQ17
DQ10__DQ18
DQ11__DQ19
DQ12__DQ20
DQ13__DQ21
DQ14__DQ22
DQ15__DQ23
DQ16__DQ8
DQ17__DQ9
DQ18__DQ10
DQ19__DQ11
DQ20__DQ12
DQ21__DQ13
DQ22__DQ14
DQ23__DQ15
DQ24__DQ0
DQ25__DQ1
DQ26__DQ2
DQ27__DQ3
DQ28__DQ4
DQ29__DQ5
DQ30__DQ6
DQ31__DQ7
ABI#
VDDQ_F3
8
7
6
345
2
1
C
A
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
C2441
C2441
22uF
22uF
4V
4V
2 1
2 1
23CNOPN001
23CNOPN001
U2400
U2400
+MVDD
+MVDD
C2506
C2506
0.1uF
0.1uF
+MVDD +MVDD
+MVDD +MVDD
C2521
C2521
1uF
1uF
7
(6) GDDR5 MEMORY CH C/D
(6) GDDR5 MEMORY CH C/D
DQC0_<31..0>
DQC0_<31..0>
MAC0_<8..0>
MAC0_<8..0>
OUT OUT OUT OUT
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
IN
4
4
IN
1%60.4R
1%60.4R
1%60.4R
1%60.4R
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
IN
R2402
R2402
R2403
C2407
C2407
0.1uF
0.1uF
C2417
C2417
1uF
1uF
R2409
R2409
R2410
R2410
C2405
C2405
C2408
C2408
0.1uF
0.1uF
C2418
C2418
1uF
1uF
R2403
R2404
R2404
C2409
C2409
0.1uF
0.1uF
C2419
C2419
1uF
1uF
1K 5%
1K 5%
4 6
4 6
IN
6.3V
6.3V
1uF
1uF
4
4
IN IN
C2411
C2411
C2410
C2410
0.1uF
0.1uF
0.1uF
0.1uF
C2420
C2420
C2421
C2421
1uF
1uF
1uF
1uF
29
29
31
31
28
28
30
30
27
27
24
24
26
26
25
25
16
16
23
23
17
17
21
21
19
19
22
22
18
18
20
20
5
5
4
4
7
7
6
6
3
3
1
1
0
0
2
2
10
10
9
9
11
11
8
8
12
12
13
13
14
14
15
15
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
5%1K
5%1K
1%2.37K
1%2.37K
1%5.49K
1%5.49K
C2413
C2413
0.1uF
0.1uF
C2422
C2422
1uF
1uF
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
6
6
4
4
MAC0_<8>
MAC0_<8>
MAC0_<7>
MAC0_<7>
MAC0_<6>
MAC0_<6>
MAC0_<5>
MAC0_<5>
MAC0_<4>
MAC0_<4>
MAC0_<3>
MAC0_<3>
MAC0_<2>
MAC0_<2>
MAC0_<1>
MAC0_<1>
MAC0_<0>
MAC0_<0>
WCKC0_0
WCKC0_0
WCKC0b_0
WCKC0b_0
WCKC0_1
WCKC0_1
WCKC0b_1
WCKC0b_1
EDCC0_3
EDCC0_3
EDCC0_2
EDCC0_2
EDCC0_0
EDCC0_0
EDCC0_1
EDCC0_1
DDBIC0_3
DDBIC0_3
DDBIC0_2
DDBIC0_2
DDBIC0_0
DDBIC0_0
DDBIC0_1
DDBIC0_1
RASC0b
RASC0b
CASC0b
CASC0b
CKEC0
CKEC0
CLKC0b
CLKC0b
CLKC0
CLKC0
CSC0b_0
CSC0b_0
WEC0b
WEC0b
ZQ_C0
ZQ_C0
1%120R
1%120R
SEN_C0
SEN_C0
DRAM_RST2
DRAM_RST2
MF_C0
MF_C0
VREFC_C0
VREFC_C0
ADBIC0
ADBIC0
C2414
C2414
C2423
C2423
1uF 0.1uF
1uF 0.1uF
DQC0_<29>
DQC0_<29>
DQC0_<31>
DQC0_<31>
DQC0_<28>
DQC0_<28>
DQC0_<30>
DQC0_<30>
DQC0_<27>
DQC0_<27>
DQC0_<24>
DQC0_<24>
DQC0_<26>
DQC0_<26>
DQC0_<25>
DQC0_<25>
DQC0_<16>
DQC0_<16>
DQC0_<23>
DQC0_<23>
DQC0_<17>
DQC0_<17>
DQC0_<21>
DQC0_<21>
DQC0_<19>
DQC0_<19>
DQC0_<22>
DQC0_<22>
DQC0_<18>
DQC0_<18>
DQC0_<20>
DQC0_<20>
DQC0_<5>
DQC0_<5>
DQC0_<4>
DQC0_<4>
DQC0_<7>
DQC0_<7>
DQC0_<6>
DQC0_<6>
DQC0_<3>
DQC0_<3>
DQC0_<1>
DQC0_<1>
DQC0_<0>
DQC0_<0>
4 6
4 6
DQC0_<2>
DQC0_<2>
DQC0_<10>
DQC0_<10>
DQC0_<9>
DQC0_<9>
DQC0_<11>
DQC0_<11>
DQC0_<8>
DQC0_<8>
DQC0_<12>
DQC0_<12>
DQC0_<13>
DQC0_<13>
DQC0_<14>
DQC0_<14>
DQC0_<15>
DQC0_<15>
C2415
C2415
0.1uF
0.1uF
C2425
C2425
C2440
C2440
22uF
22uF
4V
4V
2 1
2 1
1uF
1uF
4 6 4 6
4 6 4 6
4 6
4 6
+MVDD
+MVDD
R2401
R2401
R2400
R2400
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
+MVDD
8
C2507
C2507
0.1uF
0.1uF
C2522
C2522
1uF
1uF
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
C2509
C2508
C2509
C2508
0.1uF
0.1uF
0.1uF
0.1uF
C2524
C2523
C2524
C2523
1uF
1uF
1uF
1uF
C2512
C2512
0.1uF
0.1uF
C2525
C2525
1uF
1uF
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
C2513
C2513
0.1uF
0.1uF
C2526
C2526
1uF
1uF
+MVDD
+MVDD
+MVDD
+MVDD
C2515
C2515
0.1uF
0.1uF
C2527
C2527
1uF
1uF
C2519
C2519
0.1uF
0.1uF
C2528
C2528
1uF
1uF
22uF
22uF
4V
4V
2 1
2 1
+MVDD
C2711
C2711
0.1uF
0.1uF
C2720
C2720
1uF
1uF
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
C2712
C2712
0.1uF
0.1uF
C2721
C2721
1uF
1uF
+MVDD
+MVDD
+MVDD
C2714
C2714
0.1uF
0.1uF
C2722
C2722
1uF
1uF
C2715
C2715
0.1uF
0.1uF
C2723
C2723
1uF
1uF
23CNOPN001
23CNOPN001
U2500
DQC1_<31..0>
DQC1_<31..0>
MAC1_<8..0> MAD1_<8..0>
4 6 4 6
4 6 4 6
+MVDD
+MVDD
R2501
R2501
R2500
R2500
+MVDD +MVDD
+MVDD +MVDD
C2540
C2541
C2540
C2541
22uF
22uF
4V 4V
4V 4V
2 1
2 1
MAC1_<8..0> MAD1_<8..0>
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1%60.4R
1%60.4R
1%60.4R
1%60.4R
4
4
4
4
4
4
4
4
4
4
R2502
R2502
R2503
R2503
4 6
4 6
R2504
R2504
+MVDD +MVDD
+MVDD +MVDD
R2509
R2509
R2510
R2510
C2505
+MVDD
+MVDD
C2505
C2607
C2607
0.1uF
0.1uF
C2617
C2617
1uF
1uF
C2608
C2608
0.1uF
0.1uF
C2619
C2619
1uF
1uF
4
4
C2609
C2609
0.1uF
0.1uF
C2620
C2620
1uF
1uF
1uF
1uF
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
IN
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
C2610
C2610
0.1uF
0.1uF
C2621
C2621
1uF
1uF
1%2.37K
1%2.37K
1%5.49K
1%5.49K
6.3V
6.3V
C2611
C2611
0.1uF
0.1uF
C2622
C2622
1uF
1uF
12
12
13
13
14
14
15
15
11
11
10
10
9
9
8
8
1
1
2
2
3
3
0
0
5
5
4
4
7
7
6
6
31
31
24
24
30
30
25
25
28
28
26
26
29
29
27
27
18
18
16
16
19
19
17
17
20
20
22
22
21
21
23
23
8
8
0
0
1
1
3
3
2
2
5
5
4
4
6
6
7
7
5%1K
5%1K
5%1K
5%1K
1%120R
1%120R
C2612
C2612
0.1uF
0.1uF
C2623
C2623
1uF
1uF
6
6
4
4
DQC1_<12>
4 6
4 6
DQC1_<12>
DQC1_<13>
4 6
4 6
DQC1_<13>
DQC1_<14>
4 6
DQC1_<14>
4 6
DQC1_<15>
4 6
DQC1_<15>
4 6
DQC1_<11>
4 6
DQC1_<11>
4 6
DQC1_<10>
4 6
4 6
DQC1_<10>
DQC1_<9>
4 6
4 6
DQC1_<9>
DQC1_<8>
4 6
4 6
DQC1_<8>
DQC1_<1>
4 6
4 6
DQC1_<1>
DQC1_<2>
4 6
DQC1_<2>
4 6
DQC1_<3>
4 6
4 6
DQC1_<3>
DQC1_<0>
4 6
4 6
DQC1_<0>
DQC1_<5>
4 6
4 6
DQC1_<5>
DQC1_<4>
4 6
4 6
DQC1_<4>
DQC1_<7>
4 6
4 6
DQC1_<7>
DQC1_<6>
4 6
4 6
DQC1_<6>
DQC1_<31>
DQC1_<31>
DQC1_<24>
DQC1_<24>
DQC1_<30>
DQC1_<30>
DQC1_<25>
DQC1_<25>
DQC1_<28>
DQC1_<28>
DQC1_<26>
DQC1_<26>
DQC1_<29>
DQC1_<29>
DQC1_<27>
DQC1_<27>
DQC1_<18>
DQC1_<18>
DQC1_<16>
DQC1_<16>
DQC1_<19>
DQC1_<19>
DQC1_<17>
DQC1_<17>
DQC1_<20>
DQC1_<20>
DQC1_<22>
DQC1_<22>
DQC1_<21>
DQC1_<21>
DQC1_<23>
DQC1_<23>
MAC1_<8>
MAC1_<8>
MAC1_<0>
MAC1_<0>
MAC1_<1>
MAC1_<1>
MAC1_<3>
MAC1_<3>
MAC1_<2>
MAC1_<2>
MAC1_<5>
MAC1_<5>
MAC1_<4>
MAC1_<4>
MAC1_<6>
MAC1_<6>
MAC1_<7>
MAC1_<7>
WCKC1_1
WCKC1_1
WCKC1b_1
WCKC1b_1
WCKC1_0
WCKC1_0
WCKC1b_0
WCKC1b_0
EDCC1_1
EDCC1_1
EDCC1_0
EDCC1_0
EDCC1_3
EDCC1_3
EDCC1_2
EDCC1_2
DDBIC1_1
DDBIC1_1
DDBIC1_0
DDBIC1_0
DDBIC1_3
DDBIC1_3
DDBIC1_2
DDBIC1_2
CASC1b
CASC1b
RASC1b
RASC1b
CKEC1
CKEC1
CLKC1b
CLKC1b
CLKC1
CLKC1
WEC1b
WEC1b
CSC1b_0
CSC1b_0
ZQ_C1
ZQ_C1
SEN_C1
SEN_C1
DRAM_RST2
DRAM_RST2
MF_C1
MF_C1
VREFC_C1
VREFC_C1
ADBIC1
ADBIC1
C2613
C2614
C2613
C2614
0.1uF
0.1uF
0.1uF
0.1uF
C2624
C2624
C2625
C2625
1uF
1uF
1uF
1uF
22uF
22uF
4V
4V
2 1
2 1
M2
M2
M4
M4
N2
N2
N4
N4
T2
T2
T4
T4
V2
V2
V4
V4
M13
M13
M11
M11
N13
N13
N11
N11
T13
T13
T11
T11
V13
V13
V11
V11
F13
F13
F11
F11
E13
E13
E11
E11
B13
B13
B11
B11
A13
A13
A11
A11
F2
F2
F4
F4
E2
E2
E4
E4
B2
B2
B4
B4
A2
A2
A4
A4
J5
J5
K4
K4
K5
K5
K10
K10
K11
K11
H10
H10
H11
H11
H5
H5
H4
H4
D4
D4
D5
D5
P4
P4
P5
P5
R2
R2
R13
R13
C13
C13
C2
C2
P2
P2
P13
P13
D13
D13
D2
D2
G3
G3
L3
L3
J3
J3
J11
J11
J12
J12
G12
G12
L12
L12
J13
J13
J10
J10
J2
J2
J1
J1
A5
A5
V5
V5
A10
A10
V10
V10
J14
J14
J4
J4
C2640
C2640
2 1
2 1
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
C2641
C2641
22uF
22uF
6
U2500 U2700
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
+MVDD
C2710
C2708
C2710
C2708
C2707
C2707
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
+MVDD
+MVDD
C2718
C2718
C2719
C2719
C2717
C2717
1uF
1uF
1uF
1uF
1uF
1uF
5
23CNOPN001
23CNOPN001
U2600
DQD0_<31..0>
4 6
4 6
DQD0_<31..0>
MAD0_<8..0>
MAD0_<8..0>
R2602
R2602
R2603
R2603
R2604
R2604
R2609
R2609
R2610
R2610
C2605
C2605
C2751
C2751
22uF
22uF
4V
4V
2 1
2 1
C2753C2752
C2753
10uF
10uF
4V
4V
2 1
2 1
C2761
10uF
10uF
2 1
2 1
6
6
4
DQD0_<13>
DQD0_<13>
4
13
13
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
IN
4
4
IN
1%60.4R
1%60.4R
1%60.4R
1%60.4R
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4 6
4 6
IN
1uF
1uF
4
4
IN IN
C2762C2761C2760
C2762
10uF 10uF
10uF 10uF
2 1
2 1
1%2.37K
1%2.37K
1%5.49K
1%5.49K
6.3V
6.3V
2 1
2 1
15
15
12
12
14
14
10
10
8
8
11
11
9
9
0
0
7
7
2
2
6
6
3
3
5
5
1
1
4
4
20
20
23
23
21
21
22
22
19
19
18
18
17
17
16
16
26
26
25
25
27
27
24
24
28
28
29
29
30
30
31
31
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
1%120R
1%120R
5%1K
5%1K
5%1K
5%1K
C2755
C2755
22uF
22uF
4V
4V
DQD0_<15>
DQD0_<15>
DQD0_<12>
DQD0_<12>
DQD0_<14>
DQD0_<14>
DQD0_<10>
DQD0_<10>
DQD0_<8>
DQD0_<8>
DQD0_<11>
DQD0_<11>
DQD0_<9>
DQD0_<9>
DQD0_<0>
DQD0_<0>
DQD0_<7>
DQD0_<7>
DQD0_<2>
DQD0_<2>
DQD0_<6>
DQD0_<6>
DQD0_<3>
DQD0_<3>
DQD0_<5>
DQD0_<5>
DQD0_<1>
DQD0_<1>
DQD0_<4>
DQD0_<4>
DQD0_<20>
DQD0_<20>
DQD0_<23>
DQD0_<23>
DQD0_<21>
DQD0_<21>
DQD0_<22>
DQD0_<22>
DQD0_<19>
DQD0_<19>
DQD0_<18>
DQD0_<18>
DQD0_<17>
DQD0_<17>
DQD0_<16>
DQD0_<16>
DQD0_<26>
DQD0_<26>
DQD0_<25>
DQD0_<25>
DQD0_<27>
DQD0_<27>
DQD0_<24>
DQD0_<24>
DQD0_<28>
DQD0_<28>
DQD0_<29>
DQD0_<29>
DQD0_<30>
DQD0_<30>
DQD0_<31>
DQD0_<31>
6
6
4
4
MAD0_<8>
MAD0_<8>
MAD0_<7>
MAD0_<7>
MAD0_<6>
MAD0_<6>
MAD0_<5>
MAD0_<5>
MAD0_<4>
MAD0_<4>
MAD0_<3>
MAD0_<3>
MAD0_<2>
MAD0_<2>
MAD0_<1>
MAD0_<1>
MAD0_<0>
MAD0_<0>
WCKD0_1
WCKD0_1
WCKD0b_1
WCKD0b_1
WCKD0_0
WCKD0_0
WCKD0b_0
WCKD0b_0
EDCD0_1
EDCD0_1
EDCD0_0
EDCD0_0
EDCD0_2
EDCD0_2
EDCD0_3
EDCD0_3
DDBID0_1
DDBID0_1
DDBID0_0
DDBID0_0
DDBID0_2
DDBID0_2
DDBID0_3
DDBID0_3
RASD0b
RASD0b
CASD0b
CASD0b
CKED0
CKED0
CLKD0b
CLKD0b
CLKD0
CLKD0
CSD0b_0
CSD0b_0
WED0b
WED0b
ZQ_D0
ZQ_D0
SEN_D0
SEN_D0
DRAM_RST2
DRAM_RST2
MF_D0
MF_D0
VREFC_D0
VREFC_D0
ADBID0
ADBID0
C2763
C2763
4V
4V
2 1
2 1
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
4 6
4 6
+MVDD +MVDD
+MVDD +MVDD
R2601
R2601
R2600
R2600
+MVDD
+MVDD
C2750
C2750
22uF
22uF
4V
4V
2 1
2 1
C2752
10uF
10uF
4V
C2716
C2716
0.1uF
0.1uF
2 1
2 1
4V
2 1
2 1
C2764
C2764
C2760
10uF
10uF
10uF
10uF
4V 4V4V
4V
4V 4V4V
4V
2 1
2 1
Reserved. detail please check BOM
Reserved. detail please check BOM
SHEET:
C2740
C2740
22uF
22uF
4V
4V
22uF
22uF
4V
4V
2 1
2 1
C2741
C2741
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
4
C2724
C2724
1uF
1uF
2 1
2 1
U2600
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
GDDR5 MEM CH CD
GDDR5 MEM CH CD
Wed Apr 13 17:02:17 2016 1.0
Wed Apr 13 17:02:17 2016 1.0
6 26
6 26
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
+MVDD
+MVDD
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
OF
105_D009XX_00
105_D009XX_00
3
+MVDD
+MVDD
4 6
4 6
R2701
R2701
R2700
R2700
REV:
BIBIBIBI
DQD1_<31..0>
DQD1_<31..0>
R2702
R2702
R2703
R2703
R2704
R2704
R2709
R2709
R2710
R2710
C2705
C2705
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
23CNOPN001
23CNOPN001
DQD1_<20>
4 6
4 6
DQD1_<20>
20
20
DQD1_<21>
4 6
4 6
DQD1_<21>
21
21
DQD1_<23>
4 6
4 6
DQD1_<23>
23
23
DQD1_<22>
4 6
4 6
DQD1_<22>
22
22
DQD1_<19>
4 6
4 6
DQD1_<19>
19
19
DQD1_<18>
4 6
4 6
DQD1_<18>
18
18
DQD1_<16>
4 6
4 6
DQD1_<16>
16
16
4 6
4 6
DQD1_<17>
DQD1_<17>
17
17
DQD1_<26>
4 6
4 6
DQD1_<26>
26
26
DQD1_<25>
4 6
4 6
DQD1_<25>
25
25
DQD1_<27>
4 6
4 6
DQD1_<27>
27
27
DQD1_<24>
4 6
4 6
DQD1_<24>
24
24
DQD1_<28>
4 6
4 6
DQD1_<28>
28
28
DQD1_<29>
4 6
4 6
DQD1_<29>
29
29
DQD1_<30>
4 6
4 6
DQD1_<30>
30
30
DQD1_<31>
4 6
4 6
DQD1_<31>
31
31
DQD1_<14>
4 6
4 6
DQD1_<14>
14
14
DQD1_<8>
4 6
4 6
DQD1_<8>
8
8
DQD1_<15>
4 6
4 6
DQD1_<15>
15
15
DQD1_<9>
4 6
4 6
DQD1_<9>
9
9
DQD1_<13>
4 6
4 6
DQD1_<13>
13
13
DQD1_<10>
4 6
4 6
DQD1_<10>
10
10
DQD1_<12>
4 6
4 6
DQD1_<12>
12
12
4 6
4 6
DQD1_<11>
DQD1_<11>
11
11
4 6
4 6
DQD1_<3>
DQD1_<3>
3
3
4 6
DQD1_<0>
4 6
DQD1_<0>
0
0
DQD1_<2>
4 6
4 6
DQD1_<2>
2
2
4 6
4 6
DQD1_<1>
DQD1_<1>
1
1
DQD1_<4>
4 6
4 6
DQD1_<4>
4
4
4 6
4 6
DQD1_<5>
DQD1_<5>
5
5
4 6
4 6
DQD1_<7>
DQD1_<7>
7
7
4 6
4 6
DQD1_<6>
DQD1_<6>
6
6
6
6
4
4
MAD1_<8>
MAD1_<8>
8
8
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4 6
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
OUT
4
4
OUT
4
4
OUT
4
4
OUT
4
4
BI
4
4
BI
4
4
BI
4
4
BI
4
4
IN
4
4
IN
1%60.4R
1%60.4R
1%60.4R
1%60.4R
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4
4
IN
4 6
4 6
IN
1uF
1uF
4
4
MAD1_<0>
MAD1_<0>
0
0
MAD1_<1>
MAD1_<1>
1
1
MAD1_<3>
MAD1_<3>
3
3
MAD1_<2>
MAD1_<2>
2
2
MAD1_<5>
MAD1_<5>
5
5
MAD1_<4>
MAD1_<4>
4
4
MAD1_<6>
MAD1_<6>
6
6
MAD1_<7>
MAD1_<7>
7
7
WCKD1_0
WCKD1_0
WCKD1b_0
WCKD1b_0
WCKD1_1
WCKD1_1
WCKD1b_1
WCKD1b_1
EDCD1_2
EDCD1_2
EDCD1_3
EDCD1_3
EDCD1_1
EDCD1_1
EDCD1_0
EDCD1_0
DDBID1_2
DDBID1_2
DDBID1_3
DDBID1_3
DDBID1_1
DDBID1_1
DDBID1_0
DDBID1_0
CASD1b
CASD1b
RASD1b
RASD1b
CKED1
CKED1
CLKD1b
CLKD1b
CLKD1
CLKD1
WED1b
WED1b
CSD1b_0
CSD1b_0
1%120R
1%120R
ZQ_D1
ZQ_D1
SEN_D1
5%1K
5%1K
SEN_D1
DRAM_RST2
DRAM_RST2
MF_D1
5%1K
5%1K
MF_D1
1%2.37K
1%2.37K
1%5.49K
1%5.49K
VREFC_D1
6.3V
6.3V
VREFC_D1
ADBID1
ADBID1
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
M2
M2
DQ31__DQ7
M4
M4
DQ30__DQ6
N2
N2
DQ29__DQ5
N4
N4
DQ28__DQ4
T2
T2
DQ27__DQ3
T4
T4
DQ26__DQ2
V2
V2
DQ25__DQ1
V4
V4
DQ24__DQ0
M13
M13
DQ23__DQ15
M11
M11
DQ22__DQ14
N13
N13
DQ21__DQ13
N11
N11
DQ20__DQ12
T13
T13
DQ19__DQ11
T11
T11
DQ18__DQ10
V13
V13
DQ17__DQ9
V11
V11
DQ16__DQ8
F13
F13
DQ15__DQ23
F11
F11
DQ14__DQ22
E13
E13
DQ13__DQ21
E11
E11
DQ12__DQ20
B13
B13
DQ11__DQ19
B11
B11
DQ10__DQ18
A13
A13
DQ9__DQ17
A11
A11
DQ8__DQ16
F2
F2
DQ7__DQ31
F4
F4
DQ6__DQ30
E2
E2
DQ5__DQ29
E4
E4
DQ4__DQ28
B2
B2
DQ3__DQ27
B4
B4
DQ2__DQ26
A2
A2
DQ1__DQ25
A4
A4
DQ0__DQ24
J5
J5
RFU_A12_NC
K4
K4
A7_A8__A0_A10
K5
K5
A6_A11__A1_A9
K10
K10
A5_BA1__A3_BA3
K11
K11
A4_BA2__A2_BA0
H10
H10
A3_BA3__A5_BA1
H11
H11
A2_BA0__A4_BA2
H5
H5
A1_A9__A6_A11
H4
H4
A0_A10__A7_A8
D4
D4
WCK01__WCK23
D5
D5
WCK01#__WCK23#
P4
P4
WCK23__WCK01
P5
P5
WCK23#__WCK01#
R2
R2
EDC3__EDC0
R13
R13
EDC2__EDC1
C13
C13
EDC1__EDC2
C2
C2
EDC0__EDC3
P2
P2
DBI3#__DBI0#
P13
P13
DBI2#__DBI1#
D13
D13
DBI1#__DBI2#
D2
D2
DBI0#__DBI3#
G3
G3
RAS#__CAS#
L3
L3
CAS#__RAS#
J3
J3
CKE#
J11
J11
CK#
J12
J12
CK
G12
G12
CS#__WE#
L12
L12
WE#__CS#
J13
J13
ZQ
J10
J10
SEN
J2
J2
RESET#
J1
J1
MF
A5
A5
Vpp_NC
V5
V5
Vpp_NC1
A10
A10
VREFD1
V10
V10
VREFD2
J14
J14
VREFC
J4
J4
ABI#
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
U2700
2
B1
B1
B3
B3
B12
B12
B14
B14
D1
D1
D3
D3
D12
D12
D14
D14
E5
E5
E10
E10
F1
F1
F3
F3
F12
F12
F14
F14
G2
G2
G13
G13
H3
H3
H12
H12
K3
K3
K12
K12
L2
L2
L13
L13
M1
M1
M3
M3
M12
M12
M14
M14
N5
N5
N10
N10
P1
P1
P3
P3
P12
P12
P14
P14
T1
T1
T3
T3
T12
T12
T14
T14
C5
C5
C10
C10
D11
D11
G1
G1
G4
G4
G11
G11
G14
G14
L1
L1
L4
L4
L11
L11
L14
L14
P11
P11
R5
R5
R10
R10
A1
A1
A3
A3
A12
A12
A14
A14
C1
C1
C3
C3
C4
C4
C11
C11
C12
C12
C14
C14
E1
E1
E3
E3
E12
E12
E14
E14
F5
F5
F10
F10
H2
H2
H13
H13
K2
K2
K13
K13
M5
M5
M10
M10
N1
N1
N3
N3
N12
N12
N14
N14
R1
R1
R3
R3
R4
R4
R11
R11
R12
R12
R14
R14
V1
V1
V3
V3
V12
V12
V14
V14
B5
B5
B10
B10
D10
D10
G5
G5
G10
G10
H1
H1
H14
H14
K1
K1
K14
K14
L5
L5
L10
L10
P10
P10
T5
T5
T10
T10
1
+MVDD+MVDD
+MVDD+MVDD
+MVDD
+MVDD
DD
C
BB
A
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
IN
OUT
SSON
XIN CLKOUT1
VSSXOUT
VDD
IN
OUTINOUTININ
OUT
IN
SI
SCK
HOLD
VDD
GND
WP
SO
CE
OUT
REV 0.90
L
P
L
L
A
X
S
T
PART 9 OF 18
ANALOGIO
PLLCHARZ_L
PLLCHARZ_H
XTALOUT
XTALIN
REV 0.90
PART 8 OF 18
P
V
D
DBGDATA_15
DBGDATA_14
DBGDATA_13
DBGDATA_12
DBGDATA_11
DBGDATA_10
DBGDATA_9
DBGDATA_8
DBGDATA_5
DBGDATA_4
DBGDATA_3
DBGDATA_2
DBGDATA_1
DBGDATA_0
DBGDATA_7
DBGDATA_6
SWAPLOCKB
GENLK_VSYNC
GENLK_CLK
SWAPLOCKA
REV 0.90
G
P
I
O
PART 7 OF 18
VDD_33
VDD_33
VSYNC
HSYNC
TEST_PG_BACO
DIGON
WAKEB
BL_ENABLE
BL_PWM_DIM
GPIO_15
GPIO_5_REG_HOT_AC_BATT
GPIO_20
GPIO_16_8P_DETECT
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
HPD1
GENERICG_HPD6
GENERICF_HPD5
GENERICE_HPD4
GENERICD
GENERICC
GENERICB
GENERICA
GPIO_30
GPIO_29
CLKREQB
TEST_PG
GPIO_17_THERMAL_INT
GPIO_22_ROMCSB
GPIO_1
GPIO_0
GPIO_2
GPIO_6_TACH
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_18_HPD3
GPIO_19_CTF
GPIO_21
ININININOUT
OUT
IN
8
7
6
345
2
1
(7) ELLESMERE GPIO STRAP CF XTAL
(7) ELLESMERE GPIO STRAP CF XTAL
+VDDC
+VDDC
+0.8V
+0.8V
C
A
SCL/SDA BUS:
SCL/SDA BUS:
I2C ADDRESS
I2C ADDRESS
DDCVGA BUS:
DDCVGA BUS:
I2C ADDRESS
I2C ADDRESS
0x98
0x98
+MVDD
+MVDD
R66
R66
MR66
19 21
19 21
IN
0.8V_PGOOD
0.8V_PGOOD
R67
R67
MR67
MR67
FUNCTION
FUNCTION
EXT TEMP SENSOR LM96063
EXT TEMP SENSOR LM96063
5.1K
5.1K
21
21
21MR66
21
5.1K
5.1K
5%20K
5%20K
5%
5%
21
21
1K
1K
R62
R62
1K
1K
5%
5%
2 1
2 1
8
FUNCTION
FUNCTION
5%
5
5
5%
5%
5%
C69
C69
1uF
1uF
6.3V
6.3V
2 1
2 1
5
5
C68
1uF
1uF
6.3V
6.3V
2 1
2 1
+3.3V_BUS
+3.3V_BUS
R79
R79
10K
10K
5%
5%
2 1
2 14 3
Q31
Q31
MMDT3904-7
MMDT3904-7
4 3
+3.3V_BUS
+3.3V_BUS
R68
R68
10K
10K
5%
5%
2 14 3
2 1
Q30
Q30
MMDT3904-7
MMDT3904-7
4 3
GENLK_VSYNC
GENLK_VSYNC
7
7
DEVICE
DEVICE
DEVICE
DEVICE
+3.3V_BUS
+3.3V_BUS
C18
C1
C18
C1
1uF
1uF
1uF
1uF
6.3V
6.3V
6.3V
2 1
2 1
+1.8V
+1.8V
R89
R89
1K
1K
5%
5%
2 11 6
2 1
PG
PG
2
2
2
2
1 6
+1.8V
+1.8V
2 1
2 1
1 6
1 6
AT25
AT25
AR25
AR25
AM27
AM27
AL27
AL27
Q31
Q31
MMDT3904-7
MMDT3904-7
R69
R69
1K
1K
5%
5%
PG_BACO
PG_BACO
Q30
Q30C68
MMDT3904-7
MMDT3904-7
SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC
MR89
MR89
1K
1K
5%
5%
2 1
MR69
MR69
1K
1K
5%
5%
2 1
2 1 2 1
U1
U1
PART 8 OF 18
D
V
P
ellesmere_l4
ellesmere_l4
DBGDATA_0
DBGDATA_1
DBGDATA_2
DBGDATA_3
DBGDATA_4
DBGDATA_5
DBGDATA_6
DBGDATA_7
DBGDATA_8
DBGDATA_9
DBGDATA_10
DBGDATA_11
DBGDATA_12
DBGDATA_13
DBGDATA_14
DBGDATA_15
REV 0.90
AV18
AV18
AW18
AW18
AT19
AT19
AV19
AV19
AW19
AW19
AR20
AR20
AT20
AT20
AY20
AY20
AW20
AW20
AU20
AU20
AN21
AN21
AP21
AP21
AW21
AW21
AV21
AV21
AU21
AU21
AR21
AR21
6.3V
DVPDATA_0
DVPDATA_0
DVPDATA_1
DVPDATA_1
DVPDATA_2
DVPDATA_2
DVPDATA_3
DVPDATA_3
DVPDATA_4
DVPDATA_4
DVPDATA_5
DVPDATA_5
DVPDATA_6
DVPDATA_6
DVPDATA_7
DVPDATA_7
7
7
DVPDATA_8
DVPDATA_8
DVPDATA_9
DVPDATA_9
DVPDATA_10
DVPDATA_10
DVPDATA_11
DVPDATA_11
DVPDATA_12
DVPDATA_12
DVPDATA_13
DVPDATA_13
DVPDATA_14
DVPDATA_14
DVPDATA_15
DVPDATA_15
REV 0.90
ellesmere_l4
ellesmere_l4
7
U1
U1
PART 7 OF 18
V39
HPD1
HSYNC
VSYNC
WAKEB
DIGON
V39
V38
V38
W37
W37
AJ34
AJ34
AE34
AE34
AN30
AN30
AP32
AP32
AM30
AM30
V43
V43
V42
V42
V41
V41
AR29
AR29
AJ31
AJ31
AJ33
AJ33
AE33
AE33
AT29
AT29
AC31
AC31
AK33
AK33
AK34
AK34
AN32
AN32
AG31
AG31
AG30
AG30
AW40
AW40
AT24
AT24
AT30
AT30
AR30
AR30
AU29
AU29
AU30
AU30
AU32
AU32
AT32
AT32
AR24
AR24
AV41
AV41
AV43
AV43
AK25
AK25
AK26
AK26
AL26
AL26
0R
0R
0R
0R
R33
R33
NR30
NR30
AL24
AL24
VDD_33
AM24
AM24
VDD_33
GPIO_5_REG_HOT_AC_BATT
GPIO_10_ROMSCK
GPIO_16_8P_DETECT
GPIO_17_THERMAL_INT
G
P
I
GPIO_22_ROMCSB
O
AA31 AP24
AA31 AP24
TEST_PG
Y32
Y32
TEST_PG_BACO
GPIO_0
GPIO_1
GPIO_2
GPIO_6_TACH
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20
GPIO_21
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
CLKREQB
BL_ENABLE
BL_PWM_DIM
REV 0.90
ellesmere_l4
ellesmere_l4
7
7
7
7
7
7
7
7
7
7
7
7
7
7
TP60
TP60
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
U1
U1
PART 9 OF 18
XIN_OSC
XIN_OSC
XOUT_OSC
XOUT_OSC
PLL_CHARZ_H
PLL_CHARZ_H
PLL_CHARZ_L
PLL_CHARZ_L
ANALOGIO
ANALOGIO
P
L
L
S
X
T
A
L
XTALIN
XTALOUT
PLLCHARZ_H
PLLCHARZ_L
ANALOGIO
BA43
BA43
AY42
AY42
AM29
AM29
AN29
AN29
AW42
AW42
6
GPIO_0
GPIO_0
GPIO_1
GPIO_1
GPIO_2
GPIO_2
GPIO_5_REG_HOTb
GPIO_5_REG_HOTb
GPIO_6_TACH
GPIO_6_TACH
GPIO_8_ROMSO
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_10_ROMSCK
GPIO_11
GPIO_11
GPIO_12_MVDD_VID
GPIO_12_MVDD_VID
GPIO_13
GPIO_13
GPIO_15
GPIO_15
GPIO_17_THERM_INT
GPIO_17_THERM_INT
HPD3
HPD3
GPIO_19_CTF
GPIO_19_CTF
GPIO_20
GPIO_20
GPIO_21
GPIO_21
GPIO_22_ROMCSB
GPIO_22_ROMCSB
GPIO_29
GPIO_29
GPIO_30
GPIO_30
HPD4
HPD4
HPD5
HPD5
HPD6
HPD6
HPD1
HPD1
HSYNC
HSYNC
VSYNC
VSYNC
G_CLKREQb
G_CLKREQb
G_WAKEb
G_WAKEb
J2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
21
21
5%
5%
R30
R30
21
XIN_OSC_1 50V
XIN_OSC_1
21
5%
5%
21
XOUT_OSC_1
XOUT_OSC_1
21
5%0R
5%0R
TP31
TP31
TP32
TP32
TP30
TP30
5
+1.8V
+1.8V
2 1
2 12 1
2 1
R73
R73
5.1K
5.1K
5%
5%
R72
R72
5.1K
5.1K
5%
5%
7
7
7 22
7 22
7
7
IN
OUT
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
7
7
7
7
DVPDATA_1
DVPDATA_1
DVPDATA_3
DVPDATA_3
DVPDATA_5
DVPDATA_5
DVPDATA_7
DVPDATA_7
DVPDATA_9
DVPDATA_9
DVPDATA_11
DVPDATA_11
DVPDATA_13
DVPDATA_13
DVPDATA_15
DVPDATA_15
1M
1M
R37
R37
+1.8V
+1.8V
14
14
120R
120R
C26
C26
C27
C27
23 24
23 24
7 22
7 22
24
24
9
9
23
23
7 22
7 22
21
21
7
7
11
11
10
10
11
11
10
10
IN
3
3
Y1
Y1
1
1
B35
B35
1%
1%
18pF
18pF
18pF
18pF
RP1
RP1
RP1
RP1
RP1
RP1
7
7
OUT
RP1
RP1
OUT
1
1
+3.3V_BUS
+3.3V_BUS
R36
R36
10K
10K
5%
5%
2 1
2 1
1
1
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
C12
C12
42
42
27.000MHz
27.000MHz
C11
C11
50V
50V
21
21
2 1
2 1
50V
50V
3
42
3
42
Y5
Y5
1
1
50V
50V
7 22
7 22
7
7
0R
0R
R48
R48
J3
J3J2
HEADER_2X8HEADER_2X8
HEADER_2X8HEADER_2X8
18pF
18pF
18pF
18pF
VDD18_U22
VDD18_U22
C65
C65
1uF
1uF
6.3V
6.3V
2
2
27.000MHz
27.000MHz
3
3
24 7
24 7
R49
R49
33R
33R
81
81
33R
33R
63
63
33R
33R
72
72
+3.3V_BUS
+3.3V_BUS
33R
33R
54
54
+3.3V_BUS
+3.3V_BUS
R32
R32
10K
10K
5%
5%
2 1
2 1
5%
5%
2
2
5%
5%
21
21
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
50V
2 1
2 1
SSON
XIN CLKOUT1
C66
C66
0.1uF
0.1uF
6.3V
6.3V
DVPDATA_0
DVPDATA_0
DVPDATA_2
DVPDATA_2
DVPDATA_4
DVPDATA_4
DVPDATA_6
DVPDATA_6
DVPDATA_8
DVPDATA_8
DVPDATA_10
DVPDATA_10
DVPDATA_12
DVPDATA_12
DVPDATA_14
DVPDATA_14
U22
U22
Si51214-A1EAGM
Si51214-A1EAGM
R35
R35
2.2K
2.2K
5%
5%
2 1
2 1
CLKREQb
CLKREQb
VDD
VSSXOUT
4
GPIO_8_R
GPIO_8_R
7
7
GPIO_9_R
GPIO_9_R
7
7
GPIO_10_R
GPIO_10_R
GPIO_22_R
GPIO_22_R
2 1
2 1
MR1
MR1
5% 10K
5% 10K
MR2
MR2
2 1
2 1
10K5%
10K5%
MR3
MR3
2 1
2 1
5%
5%
10K
10K
PCC
PCC
OUT
20R 1%
20R 1%
21
21
15
15
4
4
6
6
R75
R75
IN
1
1
+1.8V
+1.8V
+1.8V
+1.8V
17
17
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
2 1
2 1
MR5
MR5
10K
10K
5%
5%
MR6
MR6
2 1
2 1
10K
5%
5%
10K
2 1
2 1
MR7
MR7
5%
5%
10K
10K
2 1
2 1
MR8
MR8
10K
5%
10K
5%
2 1
2 1
MR10
MR10
5%
10K
10K
5%
2 1
2 1
MR11
MR11
5%
5%
10K
10K
2 1
2 1
MR13
MR13
5% 10K
5% 10K
2 1
2 1MR15
MR15
10K
10K
5%
5%
2 1
2 1
MR16
MR16
10K5%
10K5%
MR18
MR18
2 1
2 1
5%
5%
10K
10K
2 1
2 1
MR19
MR19
DNI
DNI
10K
10K
5%
5%
2 1
2 1
MR20
MR20
5%
10K
10K
5%
MR21
MR21
2 1
2 1
10K
10K
5%
5%
MR22
MR22
2 1
2 1
DNI
DNI
5%
5%
2 1
2 1
MR23
MR23
10K5%
10K5%
2 1
2 1
10K5%
10K5%
MR80
MR80
2 1
2 1
5% 10K
5% 10K
2 1
2 1
MR81
MR81
DNI
DNI
5%
5%
2 1
2 1
10K5%
10K5%
ELLESMERE GPIO STRAP CF XTAL
ELLESMERE GPIO STRAP CF XTAL
Wed Apr 13 17:02:08 2016 1.0
Wed Apr 13 17:02:08 2016 1.0
+3.3V_BUS
+3.3V_BUS
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
10K
10K
DNI
DNI
2 1
2 1 R26
MR26
MR26
5%
5%
DNI
DNI
10K
10K
MR82
MR82
7 26
7 26
VIDEO BIOS
VIDEO BIOS
FIRMWARE
FIRMWARE
U11
U11
3 8
3 8
WP
2
2
SO
5
5
SI
6
6
SCK
CE
PM25LV010A-100SC
PM25LV010A-100SC
R1
R1
2 1
2 1
10K
5%
5%
10K
2 1
2 1
R2
R2
5%
10K
5%
10K
2 1
2 1
R3
R3
DNI
DNI
10K
5%
5%
10K
2 1
2 1
R5
R5
DNI
DNI
10K
10K
5%
5%
2 1
2 1
R6
R6
10K
10K
5%
5%
2 1
2 1
R7
R7
DNI
DNI
10K
10K
5%
5%
2 1
2 1
R8
R8
10K
10K
5%
5%
R10
R10
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1 R18
2 1
2 1 R19
2 1
2 1 R20
2 1
2 1 R21
2 1
2 1 R22
2 1
2 1 R23
2 1
2 1 R80
2 1
2 1 R81
2 1
2 1 R82
DNI
DNI
10K0R
5%
10K0R
5%
R11
R11
DNI
DNI
10K
5%
5%
10K
R13
R13
DNI
DNI
10K5%
10K5%
R15
R15
DNI
DNI
5%
5%
10K
10K
R16
R16
10K
10K
5%
5%
R18
DNI
DNI
10K
10K
5%
5%
R19
10K5%
10K5%
R20
DNI
DNI
5%
5%
10K
10K
R21
DNI
DNI
10K
10K
5%
5%
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
DNI
DNI
DNI
DNI
DNI
DNI
R22
R23
R26
R80
R81
R82
5%
5%
5%
5%
10K
10K
5%
5%
5%
5%
5%
5%
OF
105_D009XX_00
105_D009XX_00
3
+3.3V_BUS+3.3V_BUS
+3.3V_BUS+3.3V_BUS
VDD
7
7
HOLD
41
41
GND
GPIO_0
GPIO_0
GPIO_1
GPIO_1
1
1
GPIO_2
GPIO_2
GPIO_9_R
GPIO_9_R
0
0
GPIO_13
GPIO_13
GPIO_12_MVDD_VID
GPIO_12_MVDD_VID
GPIO_11
GPIO_11
101
101
VSYNC
VSYNC
HSYNC
HSYNC
11
11
GPIO_8_R
GPIO_8_R
0
0
GPIO_28_TS_FDO
GPIO_28_TS_FDO
GENLK_VSYNC
GENLK_VSYNC
DVPDATA_0
DVPDATA_0
DVPDATA_1
DVPDATA_1
DVPDATA_2
DVPDATA_2
GPIO_20
GPIO_20
GPIO_29
GPIO_29
GPIO_30
GPIO_30
GPIO_15
GPIO_15
DVPDATA_3
DVPDATA_3
DVPDATA_4
DVPDATA_4
DVPDATA_5
DVPDATA_5
000
000
C4
C4
0.1uF
0.1uF
6.3V
6.3V
PIN BASED STRAPS
PIN BASED STRAPS
7
7
7 22
7 22
7
7
7
7
7
7
7 22
7 22
7
7
7
7
7
7
7
7
23
23
OUT
7
7
7
7
7
7
7
7
7 22
7 22
7
7
0
0
7 24
7 24
7 22
0
0
7 22
7
7
7
7
7
7
REV:
PINSTRAP_BIF_TX_HALF_SWING
PINSTRAP_BIF_TX_HALF_SWING
PINSTRAP_SMBUS_ADDR
PINSTRAP_SMBUS_ADDR
0: 0x40
0: 0x40
1: 0x41
1: 0x41
GPIO(2) - BIF_GEN3_EN_A
GPIO(2) - BIF_GEN3_EN_A
0 : DRIVER CONTROLLED GEN3
0 : DRIVER CONTROLLED GEN3
1 : STRAP CONTROLLED GEN3
1 : STRAP CONTROLLED GEN3
PINSTRAP_SMS_EN_HARD
PINSTRAP_SMS_EN_HARD
GPIO(13,12,11) - CONFIG[2..0]
GPIO(13,12,11) - CONFIG[2..0]
CONFIG[2]
CONFIG[2]
CONFIG[1]
CONFIG[1]
CONFIG[0]
CONFIG[0]
HSYNC = AUD[1], VSYNC = AUD[0]
HSYNC = AUD[1], VSYNC = AUD[0]
AUD[0]
AUD[0]
AUD[1]
AUD[1]
HDMI MUST ONLY BE ENABLED ON SYSTMES THAT ARE LEGALLY
HDMI MUST ONLY BE ENABLED ON SYSTMES THAT ARE LEGALLY
ENTITLED. IT IS THE RESPONSIBILITY OF THE SYSTEM DESIGNER
ENTITLED. IT IS THE RESPONSIBILITY OF THE SYSTEM DESIGNER
TO SUPPORT THIS FEATURE.
TO SUPPORT THIS FEATURE.
GPIO(8) - BIF_CLK_PM_EN
GPIO(8) - BIF_CLK_PM_EN
0 - DISABLE CLKREQb POWER MANAGEMENT CAPABILITY
0 - DISABLE CLKREQb POWER MANAGEMENT CAPABILITY
1 - ENABLE CLKREQb POWER MANAGEMENT CAPABILITY
1 - ENABLE CLKREQb POWER MANAGEMENT CAPABILITY
ENSURE THAT NO LOGIC CONFLICTS WITH THIS SIGNAL DURING RESET.
ENSURE THAT NO LOGIC CONFLICTS WITH THIS SIGNAL DURING RESET.
PINSTRAP_AUD_PORT_CONN[2:0] -DVPDATA[2:0]
PINSTRAP_AUD_PORT_CONN[2:0] -DVPDATA[2:0]
PINSTRAP_TX_DEEMPH_EN
PINSTRAP_TX_DEEMPH_EN
GPIO(29) - BIF_VGA_DIS
GPIO(29) - BIF_VGA_DIS
0 : VGA CONTROLLER CAPACITIY ENABLED (NORMAL OPERATION)
0 : VGA CONTROLLER CAPACITIY ENABLED (NORMAL OPERATION)
1 : THE DEVICE WILL NOT BE RECOGNIZED AS THE SYSTEM'S VGA CONTROLLER
1 : THE DEVICE WILL NOT BE RECOGNIZED AS THE SYSTEM'S VGA CONTROLLER
PINSTRAP_EFUSE_RD_DISABLE
PINSTRAP_EFUSE_RD_DISABLE
PINSTRAP_BOARD_CONFIG [2:0]
PINSTRAP_BOARD_CONFIG [2:0]
100 - 512KBIT (ST) M25P05A
100 - 512KBIT (ST) M25P05A
101 - 1MBIT (ST) M25P10A
101 - 1MBIT (ST) M25P10A
101 - 2MBIT (ST) M25P20
101 - 2MBIT (ST) M25P20
101 - 4MBIT (ST) M25P40
101 - 4MBIT (ST) M25P40
101 - 8MBIT (ST) M25P80
101 - 8MBIT (ST) M25P80
100 - 512KBIT (CHINGIS) PM25LV512
100 - 512KBIT (CHINGIS) PM25LV512
101 - 1MBIT (CHINGIS) PM25LV010
101 - 1MBIT (CHINGIS) PM25LV010
00 - NO AUDIO FUNCTION
00 - NO AUDIO FUNCTION
01 - AUDIO FOR DP ONLY
01 - AUDIO FOR DP ONLY
10 - AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED
10 - AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED
11 - AUDIO FOR BOTH DP AND HDMI
11 - AUDIO FOR BOTH DP AND HDMI
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
Advanced Micro Devices
TITLE:
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
2
DD
C
BB
A
1
This AMD Board schematic and design is the exclusive property of AMD, and
DATE:
SHEET:
Advanced Micro Devices
2
3
345
6
6
7
7
8
8
C
5
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
C
BB
A
1
DD
C
A
4
REV:
SHEET NUMBER:
DOCUMENT NUMBER:
OF
1
prohibited. Use of this schematic and design for any purpose other than
for evaluation purposes. Further distribution or disclosure is strictly
is provided only to entities under a non-disclosure agreement with AMD
2
schematic and design, including, not limited to, any implied warranty
AMD makes no representations or warranties of any kind regarding this
evaluation requires a Board Technology License Agreement with AMD.
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
BI
OUT
OUTBIBIBIOUT
OUT
BI
REV 0.90
PART 10 OF 18
SVI2&I2C
GPIO_SVD
GPIO_SVC
GPIO_SVT
SMBDAT
SMBCLK
DDCVGADATA
DDCVGACLK
SCL
SDA
8
7
6
345
2
1
(8) ELLESMERE DAC1 LOCK
(8) ELLESMERE DAC1 LOCK
24 1
24 1
OUT
1 24
1 24
BI
8
8
BI
8
8
OUT
G_SMBCLK
G_SMBCLK
G_SMBDAT
G_SMBDAT
SCL_S
SCL_S
SDA_S
SDA_S
AM34
AM34
AM33
AM33
AF34
AF34
AF33
AF33
SMBCLK
SMBDAT
SCL
SDA
U1
U1
PART 10 OF 18
SVI2&I2C
DD
DDCVGACLK
24
24
24
24
OUT
BI
DDCVGACLK
DDCVGADATA
DDCVGADATA
C
SCL_S
SCL_S
8
8
+1.8V
+1.8V
R1111
R1111
10K
10K
2 1
2 1
+1.8V
+1.8V
R1112
R1112
10K
10K
2 1
SDA_S
SDA_S
8
8
2 1
2
2
BSH111BK
BSH111BK
R1113
213
213
1
1
3
3
BSH111BK
BSH111BK
MQ1103
MQ1103
21R1113
21
MQ1105
MQ1105
SCL
SCL
0R
0R
SDA
SDA
AD34
AD34
AD33
AD33
22 24
22 24
DDCVGACLK
DDCVGADATA
REV 0.90
22 24
22 24
ellesmere_l4
ellesmere_l4
GPIO_SVC
GPIO_SVD
GPIO_SVT
AM23
AM23
AP23
AP23
AN23
AN23
PR9
PR9
VDDC_VDDCI_SVC
VDDC_VDDCI_SVC
VDDC_VDDCI_SVD
21
21
0R
0R
VDDC_VDDCI_SVD
VDDC_VDDCI_SVT
5%
5%
VDDC_VDDCI_SVT
OUT
BI
BI
22 14
22 14
22 14
22 14
14
14
C
A
R1114
21R1114
21
0R
0R
BB
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
DATE:
SHEET NUMBER:
DOCUMENT NUMBER:
ELLESMERE SVI2&I2C
ELLESMERE SVI2&I2C
Wed Apr 13 17:07:28 2016 1.0
Wed Apr 13 17:07:28 2016 1.0
8 26
8 26
OF
105_D009XX_00
105_D009XX_00
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2016
2016
C
This AMD Board schematic and design is the exclusive property of AMD, and
is provided only to entities under a non-disclosure agreement with AMD
for evaluation purposes. Further distribution or disclosure is strictly
prohibited. Use of this schematic and design for any purpose other than
evaluation requires a Board Technology License Agreement with AMD.
AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty
of merchantability or fitness for a particular purpose, and disclaims
responsibility for any consequences resulting from use of the
information included herein.
TITLE:
Advanced Micro Devices
Ellesmere XT/PRO GD5 8L
Ellesmere XT/PRO GD5 8L
A
8
7
6
5
4
3
2
1
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