<Variant Name>
5
Title
4
3
2
1
Date:Schematic No.
PCI-E RV370 128M TSOP VO-SV/DI
105-A260xx-00C
REVISION HISTORY
D D
Sch
Rev
0
C C
00B1
B B
00C2
Date
2003-09-10
2003-09-22 - (pg5) Add RC snubber circuit on switching regulator
2003-10-16
2003/11/14
2004/03/05
PRELIMINARY BASED ON 105-A181xx-00A and 105-A200xx-0000A
- Use 402 R and C footprints as preferred
- (pg1) Add 0R bypass for PERST#, and use XOR spared gate for buffer
- (pg1) Keep only 1 100uF decoupling for +12V_BUS
- (pg1) Connect B3 of edge connector directly to +12V_BUS
- (pg2) Remove oscillator and change crystal to surface mount
- (pg2) Hard pull-down on TEST_Y/MCLK
- (pg2) Remove thermal interrupt, no provision for speed controlled fan
- (pg2) Remove redundant TPs
- (pg2) Pull-up on DVPCNTL_[3:0], remove RageTheater capture ports (VID/DVO[7:0])
- (pg2) DVOMode pull-up to 1.8V, set to 12-bit DVO (1.8V DVO I/O signalling)
- (pg3) Memory interface based on A198, remove Channel B
- (pg4) Remove power-up diodes
- (pg5, 6, 7) Redesigned power regulators
- (pg8, 9) Channel A only Series-Terminated TSOP interface (based on A200)
- (pg11, 12, 13) Front-end based on Low-Profile VGA/DVI + VO design (based on A200)
- (pg7) Add R124 for power dissipation
- (pg14) Add MT2, second mounting hole
- (pg6 and 7) Remove R817, option for sharing REG8 and REG9, due to layout concerns
- (pg4) Add C979..C985 On request of EMI team. These are for decoupling ajacent planes.
- (pg6) Make RP2 dual footprint with 0402 Caps C986..C989. Created a similar circuit using RP195 and C990..C993. The RP can be used to short +MVDDQ and +MVDDC, and the
caps can be used to decouple the planes.
- (pg6) Add C973..C978 Decoupling caps. These are placed accross +MVDDQ/+MVDDC plane splits
- (pg11) Remove R994..R996 stitching GND to Chassis GND.
- (Layout) Change to 6-layer PCB
- (Layout) Change PCIE test points
- (pg1) Change PCIE test points, add 3.3V_BUS polymer cap, add R1244
- (pg2) Add R23 for DVO pull-down
- (pg4) Add B15 for +3.3V_BUS VDDR4 alternate, change PCIE regulators filter from 100nF to 1uF
- (pg5) Add stand-alone +PCIE_VDDR, +PCIE_PVDD12 and +PCIE_PVDD18 regulators, improve power sequence circuit
- (pg5) Add R315 and R316 to select +12V_BUS or +5V for boot circuit, change R368 footprint to 603
- (pg6) Add C314 and C315 for MVDDC and MVDDQ, 1.8V from PCIE_PVDD18
- (pg7) Remove R124, add polymer cap for PCIE_PVDD18, add +PCIE_VDDR and +PCIE_PVDD12 tied option and single package FET for +PCIE_VDDR
- (pg14) Add fan connector
- (pg02, 10) Fix pull-up +VDD_DVO to +VDDR4
- (Layout) TVO filters move close to connector
- (pg04) Remove CP2, 3, 4, 5, 6 and 8 for dual footprint manufacturing issues (Capacitor packs sharing with 402 footprints)
- (Layout) Components using the same foot print. (remove MC2)
- (pg06) Remove C986, C987, C988, C989, C990, C991, C992 and C993
- (pg06) Add C800 for options
- (pg11) +5V supply with current limiting for VESA DDC spec, remove F1, B21
- (pg05) Remove dual-packaged MOSFET
- (Layout/EMI) C507, C508, C509, R513, R514, R515 (added), L60, L61 and L62 connect to digital Gnd instead of chassis Gnd.
REVISION DESCRIPTION
Wednesday, March 24, 2004
Rev
2
A A
5
4
3
2
1
8
7
6
5
4
3
2
1
+12V_BUS
C5
100uF_16V
DNI DNI DNI
D D
C C
B B
PETp0_GFXRp0(2)
PETn0_GFXRn0(2)
PETp1_GFXRp1(2)
PETn1_GFXRn1(2)
PETp2_GFXRp2(2)
PETn2_GFXRn2(2)
PETp3_GFXRp3(2)
PETn3_GFXRn3(2)
PETp4_GFXRp4(2)
PETn4_GFXRn4(2)
PETp5_GFXRp5(2)
PETn5_GFXRn5(2)
PETp6_GFXRp6(2)
PETn6_GFXRn6(2)
PETp7_GFXRp7(2)
PETn7_GFXRn7(2)
PETp8_GFXRp8(2)
PETn8_GFXRn8(2)
PETp9_GFXRp9(2)
PETn9_GFXRn9(2)
PETp10_GFXRp10(2)
PETn10_GFXRn10(2)
PETp11_GFXRp11(2)
PETn11_GFXRn11(2)
PETp12_GFXRp12(2)
PETn12_GFXRn12(2)
PETp13_GFXRp13(2)
PETn13_GFXRn13(2)
PETp14_GFXRp14(2)
PETn14_GFXRn14(2)
PETp15_GFXRp15(2)
PETn15_GFXRn15(2)
+3.3V_BUS +3.3V_BUS
C8
100uF_16V
A_HSYNC_DAC1(2,11)
USE 47uF TANTALUM
C2
CAPACITOR OR HIGHER
47uF_16V
>=6.3V>=6.3V
R1008 0R
DNI
TP28
TP30
TP29
TP32
TP31
TP34
TP33
TP36
TP35
TP38
TP37
TP40
TP39
TP42
TP41
TP44
TP43
TP46
TP45
TP48
TP47
TP50
TP49
TP52
TP51
TP54
TP53
TP56
TP55
TP58
TP57
PRESENCE
TP59
402
JTAG_TRST#
PCI-EXPRESS EDGE CONNECTOR
+3.3V_BUS
PRESENT_NULL
PRESENT_NULL
PRESENT_NULL
+12V_BUS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
MPCIE1
+12V#B1
+12V#B2
RSVD#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
x16 PCIe
Mechanical Key
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLK-
GND#A15
GND#A18
RSVD#A19
GND#A20
GND#A23
GND#A24
GND#A27
GND#A28
GND#A31
RSVD#A32
RSVD#A33
GND#A34
GND#A37
GND#A38
GND#A41
GND#A42
GND#A45
GND#A46
GND#A49
RSVD#A50
GND#A51
GND#A54
GND#A55
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
JTAG2
JTAG3
JTAG4
JTAG5
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
+12V_BUS
+3.3V_BUS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PRESENCE
R12440R
DNI
402
RP194A 0R
8 1
RP194B 0R
7 2
RP194C 0R
6 3
RP194D 0R
5 4
TP26
TP27
C607
100nF
C608
100nF
C617
C618
100nF
100nF
C626
100nF
C627
100nF
C631
100nF
C632
100nF
C611
100nF
C612
100nF
C622
100nF
C623
100nF
C621
100nF
C630
100nF
C605
100nF
C606
100nF
C615
100nF
C616
100nF
C624
100nF
C625
100nF
C633
100nF
C634
100nF
C609
100nF
C610
100nF
C619
100nF
C620
100nF
C628
100nF
C629
100nF
C603
100nF
C604
100nF
C613
100nF
C614
100nF
DNI
A_VSYNC_DAC1 (2,11)
DNI
CRT1DDCDATA (2,11)
DNI
SCL (2)
DNI
CRT1DDCCLK (2,11)
PCIE_REFCLKP (2)
PCIE_REFCLKN (2)
GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)
GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)
GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)
GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)
GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)
GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)
GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)
GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)
GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)
GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)
GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)
GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)
GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)
GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)
GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)
GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)
PERST#
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
+5V
147
1
2
R64 0R
DNI
GND_PVSS GND_TXVSSR
C972
100nF
402
SN74ACT86D
U6A
R3 100R
3
402
GND_TPVSSGND_MPVSS
GND_A2VSSN
GND_AVSSQ GND_RSET
GND_R2SETGND_AVSSN
PERST#_buf (2)
R4
180R
402
GND_A2VSSQ
SYMBOL LEGEND
DO NOT
DNI
INSTALL
#
ACTIVE
LOW
A A
<Variant Name>
8
7
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
C
Date: Sheet
2
105-A260xx-00C
DIGITAL
GROUND
ANALOG
GROUND
115Wednesday, March 24, 2004
1
2
of
5
4
3
2
1
U1A
PETp0_GFXRp0(1)
PETn0_GFXRn0(1)
PETp1_GFXRp1(1)
PETn1_GFXRn1(1)
PETp2_GFXRp2(1)
PETn2_GFXRn2(1)
PETp3_GFXRp3(1)
D D
C C
SCL(1)
C71 15PF
C72 15PF
+3.3V_BUS
R45
R46
4.7K
4.7K
402 402
402
Y1
27_MHZ
5023270000
2 1
402
OPTION 1: Crystal Circuit
+3.3V_BUS
4
C18
2
100nF
402
5015270000
B B
A A
MY1
VCC
GND
27.000MHz
A_R/C_DAC2(13)
A_G/Y_DAC2(13)
A_B/COMP_DAC2(13)
R27
220R
3
OUT
1
E/D
+3.3V_BUS
PETn3_GFXRn3(1)
PETp4_GFXRp4(1)
PETn4_GFXRn4(1)
PETp5_GFXRp5(1)
PETn5_GFXRn5(1)
PETp6_GFXRp6(1)
PETn6_GFXRn6(1)
PETp7_GFXRp7(1)
PETn7_GFXRn7(1)
PETp8_GFXRp8(1)
PETn8_GFXRn8(1)
PETp9_GFXRp9(1)
PETn9_GFXRn9(1)
PETp10_GFXRp10(1)
PETn10_GFXRn10(1)
PETp11_GFXRp11(1)
PETn11_GFXRn11(1)
PETp12_GFXRp12(1)
PETn12_GFXRn12(1)
PETp13_GFXRp13(1)
PETn13_GFXRn13(1)
PETp14_GFXRp14(1)
PETn14_GFXRn14(1)
PETp15_GFXRp15(1)
PETn15_GFXRn15(1)
GFXTp0_PERp0(1)
GFXTn0_PERn0(1)
GFXTp1_PERp1(1)
GFXTn1_PERn1(1)
GFXTp2_PERp2(1)
GFXTn2_PERn2(1)
GFXTp3_PERp3(1)
GFXTn3_PERn3(1)
GFXTp4_PERp4(1)
GFXTn4_PERn4(1)
GFXTp5_PERp5(1)
GFXTn5_PERn5(1)
GFXTp6_PERp6(1)
GFXTn6_PERn6(1)
GFXTp7_PERp7(1)
GFXTn7_PERn7(1)
GFXTp8_PERp8(1)
GFXTn8_PERn8(1)
GFXTp9_PERp9(1)
GFXTn9_PERn9(1)
GFXTp10_PERp10(1)
GFXTn10_PERn10(1)
GFXTp11_PERp11(1)
GFXTn11_PERn11(1)
GFXTp12_PERp12(1)
GFXTn12_PERn12(1)
GFXTp13_PERp13(1)
GFXTn13_PERn13(1)
GFXTp14_PERp14(1)
GFXTn14_PERn14(1)
GFXTp15_PERp15(1)
GFXTn15_PERn15(1)
PCIE_REFCLKP(1)
PCIE_REFCLKN(1)
+PCIE_VDDR
TP6
R32
1.0M
402
R28
130R
R1009 150R
R1010 100R
R1011 10K
R1089 10K
PERST#_buf(1)
R29
0R
402
GND_R2SET
R40 715R
R33
1K
402
+3.3V_BUS
R44
10K
402
OPTION 2: Oscillator Circuit
5
AH30
PCIE_RX0P
AG30
PCIE_RX0N
AG29
PCIE_RX1P
AF29
PCIE_RX1N
AE29
PCIE_RX2P
AE30
PCIE_RX2N
AD30
PCIE_RX3P
AD29
PCIE_RX3N
AC29
PCIE_RX4P
AB29
PCIE_RX4N
AB30
PCIE_RX5P
AA30
PCIE_RX5N
AA29
PCIE_RX6P
Y29
PCIE_RX6N
W29
PCIE_RX7P
W30
PCIE_RX7N
V30
PCIE_RX8P
V29
PCIE_RX8N
U29
PCIE_RX9P
T29
PCIE_RX9N
T30
PCIE_RX10P
R30
PCIE_RX10N
R29
PCIE_RX11P
P29
PCIE_RX11N
N29
PCIE_RX12P
N30
PCIE_RX12N
M30
PCIE_RX13P
M29
PCIE_RX13N
L29
PCIE_RX14P
K29
PCIE_RX14N
K30
PCIE_RX15P
J30
PCIE_RX15N
AF26
PCIE_TX0P
AE26
PCIE_TX0N
AC25
PCIE_TX1P
AB25
PCIE_TX1N
AC27
PCIE_TX2P
AB27
PCIE_TX2N
AC26
PCIE_TX3P
AB26
PCIE_TX3N
Y25
PCIE_TX4P
W25
PCIE_TX4N
Y27
PCIE_TX5P
W27
PCIE_TX5N
Y26
PCIE_TX6P
W26
PCIE_TX6N
U25
PCIE_TX7P
T25
PCIE_TX7N
U27
PCIE_TX8P
T27
PCIE_TX8N
U26
PCIE_TX9P
T26
PCIE_TX9N
P25
PCIE_TX10P
N25
PCIE_TX10N
P27
PCIE_TX11P
N27
PCIE_TX11N
P26
PCIE_TX12P
N26
PCIE_TX12N
L25
PCIE_TX13P
K25
PCIE_TX13N
L27
PCIE_TX14P
K27
PCIE_TX14N
L26
PCIE_TX15P
K26
PCIE_TX15N
AF27
PCIE_REFCLKP
AE27
PCIE_REFCLKN
402
AC23
PCIE_CALRP
402
AB24
PCIE_CALRN
402
AB23
PCIE_CALI
402
AE25
PCIE_TEST
AD24
PWRGD_MASK
AD25
PWRGD
AH21
R2SET
402
AJ22
C_R_PR
AK21
Y_G
AK22
COMP_B_PB
AJ24
H2SYNC
AK24
V2SYNC
AG22
DDC3CLK
AG23
DDC3DATA
AJ23
NC#AJ23
AH24
NC#AH24
AH28
XTALIN
AJ29
XTALOUT
TESTEN
AH27
TESTEN
E8
TEST_YCLK
B6
TEST_MCLK
AF25
PLLTEST
AH25
STEREOSYNC
RV370GL
IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS
TO ADDRESS ANY LAYOUT NOISE RELATED
SIGNAL DAMPING REQUIREMENTS
4
Part 1 of 6
GPIO_PWRCNTL
GPIO_MEMSSIN
DVO / EXT TMDS / GPIOTMDSDAC1
PCI Express
DAC2CLK
GPIO__AUXWIN
THERM
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
DVOVMODE
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
VREFG
NC#AH15
NC#AH16
NC#AJ16
NC#AJ17
NC#AJ18
NC#AK18
NC#AJ20
NC#AJ21
NC#AK19
NC#AJ19
NC#AG16
NC#AG17
NC#AF16
NC#AF17
NC#AE18
NC#AE19
NC#AF19
NC#AF20
NC#AG19
NC#AG20
NC#AE12
NC#AG12
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
DPLUS
DMINUS
R
G
B
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20
AE12
AG12
AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12
AE13
AE14
AF12
AK27
AJ27
AJ26
AJ25
AK25
AH26
AG25
AF24
AG24
AF11
AE11
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
DVOMODE
VID/DVO14
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
R43 10K
R39 499R
AUXWIN
+3.3V_BUS
402
402
TP11
TP12
3
GPIO[6..0]
GPIO[13..8]
Mem_Strap1 (10)
Mem_Strap0 (10)
R22 10K
R23 10K
Pull-up to 1.8V
12bit-DVO mode for SDR
Ext. TMDS 1.8V DVO I/O
SVHS/YPrPbb (13)
LCDDATA16 (10)
LCDDATA17 (10)
VHAD0 (10)
+3.3V_BUS
C16
100nF
402
A_HSYNC_DAC1
GND_RSET
GPIO[6..0] (10)
GPIO[13..8] (10)
+VDDR4
402
402
R35
1K
402
Both resistors and
capacitor close to ASIC
R34
1K
402
TMDS_TX0N (12)
TMDS_TX0P (12)
TMDS_TX1N (12)
TMDS_TX1P (12)
TMDS_TX2N (12)
TMDS_TX2P (12)
TMDS_TXCN (12)
TMDS_TXCP (12)
HPD (12)
A_R_DAC1 (11)
A_G_DAC1 (11)
A_B_DAC1 (11)
A_HSYNC_DAC1 (1,11)
A_VSYNC_DAC1 (1,11)
TP7
CRT1DDCDATA (1,11)
CRT1DDCCLK (1,11)
BOUNDARY SCAN TEST ACCESS
A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1
TESTEN
DEBUG BUS ACCESS
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
GPIO10
GPIO11
GPIO12
GPIO13
OPT
JU2
Header_3_Pin_1X3
+3.3V_BUS
R65
4.7K
402
2
P1
PLUG
1
2
3
<Variant Name>
+VDDR4
TRST/
TP1
TDO
TP2
TDI
TP3
TMS
TP4
TCK
TP5
TP8
TESTOUT(0)
TESTOUT(1)
TESTOUT(2)
TESTOUT(3)
TP17
TESTOUT(4)
TESTOUT(5)
TP19
TESTOUT(6)
TP20
TESTOUT(7)
TP21
TESTOUT(8)
TESTOUT(9)
TESTOUT(10)
TESTOUT(11)
R584
10K
402
R585
10K
ALT
402
41
SW1A
DIP_SWX2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
105-A260xx-00C
1
215Wednesday, March 24, 2004
2
of
1
2
3
4
5
6
7
8
QSA[7..0](8)
DQMA#[7..0](8)
MAA[14..0](9)
MDA[63..0](8)
A A
B B
C C
QSA[7..0]
DQMA#[7..0]
MAA[14..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
U1B
H28
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
Part 2 of 6
MEMORY INTERFACE
H29
J28
J29
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
RV370GL
MEMORY CHANNEL A
U1C
D7
MAA0
E22
MAA_0
MAA1
B22
MAA_1
MAA2
B23
MAA_2
MAA3
B24
MAA_3
MAA4
C23
MAA_4
MAA5
C22
MAA_5
MAA6
F22
MAA_6
MAA7
F21
MAA_7
MAA8
C21
MAA_8
MAA9
A24
MAA_9
MAA10
C24
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
CSAb_0
CSAb_1
CLKA0b
CLKA1b
MVREFD
MVREFS
DIMA_0
DIMA_1
A
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
RASAb
CASAb
WEAb
CKEA
CLKA0
CLKA1
MAA11
A25
MAA12
E21
MAA13
B20
MAA14
C19
DQMA#0
J25
DQMA#1
F29
DQMA#2
E25
DQMA#3
A27
DQMA#4
F15
DQMA#5
C15
DQMA#6
C11
DQMA#7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
E18
WEA#
E19
CSA#0
E20
F20
CKEA
B19
CLKA0
B21
CLKA#0
C20
CLKA1
C18
CLKA#1
A18
B7
B8
D30
B13
RASA# (9)
CASA# (9)
WEA# (9)
CSA#0 (9)
CKEA (9)
CLKA0 (8,9)
CLKA#0 (8,9)
CLKA1 (8,9)
CLKA#1 (8,9)
C153
100nF
402
+MVDDQ
R58
100R
402
C154
R59
100nF
100R
402
402
PLACE C351/152 VERY CLOSE TO ASIC
R56/57/58/59 CLOSE TO ASIC AS WELL
+MVDDQ
R56
100R
402
R57
100R
402
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
Part 3 of 6
MEMORY INTERFACE
B
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
RV370GL
MEMORY CHANNEL B
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
RASBb
CASBb
WEBb
CSBb_0
CSBb_1
CKEB
CLKB0
CLKB0b
CLKB1
CLKB1b
DIMB_0
DIMB_1
ROMCSb
MEMVMODE_0
MEMVMODE_1
MEMTEST
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
E6
B2
J5
G3
W6
W2
AC6
AD2
F6
B3
K6
G1
V5
W1
AC5
AD1
R2
T5
T6
R5
R6
R3
N1
N2
T2
T3
E3
AA3
AF5
C6
C7
C8
R53
4.7K
R55
402 402
47R
402
LAYOUT NOTE: SOME OF THE RESISTORS R51-54 MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING
R51 4.7K
R52 4.7K
R54
4.7K
DNI
ROMCS# (10)
402
402
DNI
+VDDC_CT
VDDR1 MEMVMODE_0 MEMVMODE_1
1.8V
2.5V
2.8V
GND
+VDDC_CT GND
+VDDC_CT +VDDC_CT
+VDDC_CT
D D
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
1
2
3
4
5
6
Date: Sheet
7
105-A260xx-00C
2
of
315Wednesday, March 24, 2004
8
5
+MVDDQ
D D
+MVDDQ
C38
10uf
+MVDDQ
C32
100nF
100nF
402 402 402
C C
+1.8V
B11
200R
ALT: 0R
+1.8V
B14
200R
ALT: 0R
B B
A A
+1.8V
B13
200R
ALT: 0R
C31
100nF
100nF
402 402402
+TPVDD
C50
10uf
OPT
GND_TPVSS
+TXVDDR_PINS
C59
4.7uF
GND_TXVSSR
+A2VDDQ
C63
4.7uF
GND_A2VSSQ
AVDD/A2VDDQ (1st & 2nd
DAC Band Gap) - 200mA
+AVDD
C67
4.7uF
GND_AVSSN
C35
C33
C75
C74
100nF
100nF
C43
C58
2.2uF
2.2uF
ALT:
ALT:
100nF
100nF
C60
C81
100nF
100nF
402
402
C64
100nF
402
C68
100nF
402
5
C73
100nF
402
+1.8V
C94
100nF
B12
200R
ALT: 0R
C95
100nF
402402 402402
C96
100nF
GND_A2VSSN
+VDDOI_PINS
C66
4.7uF
+PVDD
GND_PVSS
+MPVDD
GND_MPVSS
C97
100nF
+A2VDD
C54
4.7uF
C52
4.7uF
C65
100nF
402
C62
100nF
402
C53
100nF
402
C51
100nF
402
+MVDDQ
AE15
AE16
AE17
AF15
AH19
AH13
AF13
AF14
AE20
AF21
AF23
AH23
AE23
AE22
AK28
K23
K24
L23
H10
H13
H15
H17
AA1
AA4
AA7
AA8
A15
A21
A28
B30
D26
D23
D20
D17
D14
D11
E27
G10
G13
G15
G19
G22
G27
H22
H19
AD4
F18
T7
R4
R1
N8
N7
M4
L8
J8
J7
J4
J1
T8
V4
V7
V8
A3
A9
B1
D8
D5
F4
G7
N4
N6
A7
U1D
RV370GL
4
VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L8
VDDR1#K23
VDDR1#K24
VDDR1#L23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1#A9
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#N4
NC#AE15
NC#AE16
NC#AE17
NC#AF15
NC#AH19
TPVDD
TXVDDR#AF13
TXVDDR#AF14
VDDRH0
VDDRH1
A2VDD#AE20
A2VDD#AF21
A2VDDQ
AVDD
VDD1DI
VDD2DI
PVDD
MPVDD
4
Part 4 of 6
PCIE_VDDR_12#AG26
PCIE_VDDR_12#AG27
PCIE_VDDR_12#AG28
PCIE_VDDR_12#AJ30
PCIE_VDDR_12#AK29
PCIE_PVDD_12#N23
PCIE_PVDD_12#N24
PCIE_PVDD_12#P23
PCIE_PVDD_18#T23
PCIE_PVDD_18#U23
PCIE_PVDD_18#V23
PCIE_PVDD_18#W23
I/O POWER
VDDC#AC13
VDDC#AC15
VDDC#AC17
VDDC#AD13
VDDC#AD15
VDD15#H11
VDD15#H20
VDD15#M23
VDD15#P8
VDD15#Y23
VDD15#Y8
VDD15#AC11
VDD15#AC20
VDDR3#AC8
VDDR3#AC19
VDDR3#AC21
VDDR3#AC22
VDDR3#AD7
VDDR3#AD19
VDDR3#AD21
VDDR4#AC9
VDDR4#AC10
VDDR4#AD9
VDDR4#AD10
VDDR4#AG7
NC#D9
NC#D13
NC#D19
NC#D25
NC#E4
NC#T4
NC#AB4
NC#AF18
NC#AG15
NC#AG18
NC#AH17
NC#AH18
TPVSS
TXVSSR#AH14
TXVSSR#AG13
TXVSSR#AG14
VSSRH0
VSSRH1
A2VSSN#AH20
A2VSSN#AG21
A2VSSQ
AVSSN
AVSSQ
VSS1DI
VSS2DI
PVSS
MPVSS
AC13
AC15
AC17
AD13
AD15
H11
H20
M23
P8
Y23
Y8
AC11
AC20
AC8
AC19
AC21
AC22
AD7
AD19
AD21
AC9
AC10
AD9
AD10
AG7
D9
D13
D19
D25
E4
T4
AB4
AG26
AG27
AG28
AJ30
AK29
N23
N24
P23
T23
U23
V23
W23
AF18
AG15
AG18
AH17
AH18
AH12
AH14
AG13
AG14
F19
M6
AH20
AG21
AF22
AH22
AD22
AE24
AE21
AJ28
A6
+VDDC
+VDDC_CT
+3.3V_BUS
GND_TPVSS
GND_TXVSSR
GND_A2VSSN
GND_A2VSSQ
GND_AVSSN
GND_PVSS
GND_MPVSS
+VDDR4
C70
4.7uF
+PCIE_VDDR
+PCIE_PVDD_12
+PCIE_PVDD_18
GND_AVSSQ
+VDDC
C69
100nF
402
C20
100nF
3
C21
C22
100nF
100nF
402 402402
+3.3V_BUS
B15
200R
ALT: 0R
C99
C98
1.0uF
1.0uF
TP9
3
C82
C23
100nF
100nF
402 402 402 402 402 402 402 402402 402 402 402 402
C37
1.0uF
C968
C969
1.0uF
1.0uF
C970
C971
1.0uF
1.0uF
C83
100nF
C44
100nF
+3.3V_BUS
+MVDDQ
C84
100nF
+3.3V_BUS
CP9A
10nF
8 1
CP10A
10nF
8 1
CP11A
10nF
8 1
C983
100nF
C984
100nF
C985
100nF
C46
100nF
C979
100nF
C980
100nF
C981
100nF
C982
100nF
C85
100nF
+VDDC_CT
CP9B
10nF
7 2
CP10B
10nF
7 2
CP11B
10nF
7 2
+VDDC
+Vout_Switcher
+MVDDQ
+12V_BUS_F1
+VDDC
+MVDDC
C86
100nF
C45
100nF
402 402 402 402402 402
CP9C
10nF
6 3
CP10C
10nF
6 3
CP11C
10nF
6 3
CAPS C979..C985 are
accross Plane Splits
They are not required
They should be populated
only if EMI issues are
found.
C87
100nF
C47
100nF
+VDDC
5 4
5 4
5 4
+VDDC
CP9D
10nF
CP10D
10nF
CP11D
10nF
C26
100nF
C88
100nF
C48
100nF
C24
10uf
2
C28
100nF
C90
100nF
C39
100nF
402 402
C41
100nF
402 402
C55
100nF
402 402
C40
100nF
C42
100nF
C56
100nF
C29
100nF
C91
100nF
C76
100nF
402 402
C78
100nF
402 402
C57
100nF
402 402
<Variant Name>
C27
100nF
402 402 402 402402
C89
100nF
C49
100nF
These caps are footprint-shared alternate
of capacitor array
2
C30
100nF
C92
100nF
C77
100nF
C79
100nF
C61
100nF
1
+VDDC
U1F
Part 6 of 6
P17
VDDC#P17
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
V17
VDDC#V17
V14
VDDC#V14
V13
VDDC#V13
V12
VDDC#V12
N18
C93
100nF
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13
VDDC#P13
RV370GL
U1E
A2
A10
A16
A22
A29
C1
C3
C28
C30
D27
D24
D21
D18
D15
D12
D6
D4
D10
F27
G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
H9
H8
H4
J23
J24
AD12
AG5
AG9
AG11
R7
P4
M7
M8
L4
K1
K7
K8
R8
T1
W8
W7
U8
U4
Y4
RV370GL
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
PLACED CLOSE TO THE POWER/GND PINS
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
C
Date: Sheet
VSS#A2
VSS#A10
VSS#A16
VSS#A22
VSS#A29
VSS#C1
VSS#C3
VSS#C28
VSS#C30
VSS#D27
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D6
VSS#D4
VSS#D10
VSS#F27
VSS#G9
VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#J23
VSS#J24
VSS#AD12
VSS#AG5
VSS#AG9
VSS#AG11
VSS#R7
VSS#P4
VSS#M7
VSS#M8
VSS#L4
VSS#K1
VSS#K7
VSS#K8
VSS#R8
VSS#T1
VSS#W8
VSS#W7
VSS#U8
VSS#U4
VSS#Y4
Part 5 of 6
CORE GND
105-A260xx-00C
VSS#M16
VSS#N16
VSS#N15
VSS#P15
VSS#P16
VSS#R18
VSS#R17
VSS#R16
VSS#R15
VSS#R14
VSS#R13
VSS#R12
VSS#T13
VSS#T14
VSS#T15
VSS#W15
VSS#V16
VSS#V15
VSS#U15
VSS#U16
VSS#T19
VSS#T18
VSS#T17
VSS#T16
CENTER ARRAY
VDDCI#W16
VDDCI#M15
VDDCI#R19
VDDCI#T12
VDDC#W19
VDDC#M17
VDDC#P14
PCIE_VSS#W24
PCIE_VSS#W28
PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA28
PCIE_VSS#AB28
PCIE_VSS#AC28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AD28
PCIE_VSS#AE28
PCIE_VSS#AF28
PCIE_VSS#AH29
1
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
W19
M17
P14
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD18
VSS#AK2
VSS#AJ1
PCIE_VSS#K28
PCIE_VSS#L28
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M26
PCIE_VSS#M27
PCIE_VSS#M28
PCIE_VSS#N28
PCIE_VSS#P28
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R25
PCIE_VSS#R26
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#T24
PCIE_VSS#T28
PCIE_VSS#U28
PCIE_VSS#V24
PCIE_VSS#V25
PCIE_VSS#V26
PCIE_VSS#V27
PCIE_VSS#V28
PCIE_VSS#Y28
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1
K28
L28
M24
M25
M26
M27
M28
N28
P28
R23
R24
R25
R26
R27
R28
T24
T28
U28
V24
V25
V26
V27
V28
W24
W28
Y28
AA23
AA24
AA25
AA26
AA27
AA28
AB28
AC28
AD26
AD27
AD28
AE28
AF28
AH29
415Wednesday, March 24, 2004
2
of
8
7
6
5
4
3
2
***
Indicate number of power via required for the connection
1
Regulator for VDDC (ASIC Core)
Vout = 1.2V ~ 1.3V
81
72
63
54
+12V_BUS
+Vout_Switcher
C323
22uF_16V
******
OPT OPT
**
C324
22uF_16V
ALT. 1: MAXIM REGULATOR
D D
+5V +12V_BUS
R315
R316
0R
0R
C151
1.0uF
+VDDC_S
21
D1
RB501V-40
+VDDC_B
C147
100nF
603
X7R
5%
C C
R314
510K
C148
C149
470pF
27pF
402
ALT. 2: INTERSIL REGULATOR
+VDDC_S
C104
22nf
C312
10nF
402
R358 51K
R359 3K
C111
33pF
R368
15K_1%
402
U41
1
2
3
9
10
1
2
3
4
5
6
7
HSD
ILIM
COMP
FB
LX
BST
MAX1954EUB
R357 10K
MU31
RT
OCSET
SS
COMP
FB
EN
GND
ISL6522CB
GND
PGND
DH
DL
IN
LGATE
UGATE
PHASE
PVCC
PGND
BOOT
8
6
5
4
7
14
VCC
13
12
11
10
9
8
ISL6522CB : SOIC
+PW_VDDC_HGD
+PW_VDDC_LGD
+12V_BUS_F1
C143
0.22uF
+VDDC_B
R351 0R
402
must be low impedance
must be low impedance
VDDC_FB
+12V_BUS
R99
2.2R
C115
100nF
603
X7R
5%
Alt. 1: Separate MOSFETs
Q24
4 5
3
2
1
+PW_VDDC_M
4 5
3
2
1
IRF7413A
Q22
IRF7413A
6
7
8
6
7
8
L21 2.2uH
R15
1R
C152
2.2nF
C150
10uF
+VDDC_S
***
***
C325
10nF
Cc1
R254
1.5K
Rc1
C301
470UF
0.019R @ 100kHz
3.5mm LS
High current path
R1
R353
1.00K
1%
0.8V Ref
R2
R356
2K
1%
B17
60R
***
***
***
C321
470uF_10V
***
+Vout_Switcher +VDDC +VDDC
RP1A 0R
RP1B 0R
RP1C 0R
RP1D 0R
Part NOTES
MAX1954
ISL6522
Do not install Cc1, Rc1
Install Cc1, Rc1
Part Vout R1 R2
MAX1954
ISL6522
0.8V Ref
***
C322
470uF_10V
***
1.2V
1.3V
1.00K 1%
ATI P/N 3240100100 ATI P/N 3240200100
1.00K 1%
ATI P/N 3240100100
2.00K 1%
1.6K 1%
ATI P/N 3240162100
+Vout_Switcher
L6 1.8uH
+Vout_Switcher
L7 1.8uH
B B
ALT: 0R
ALT: 0R
+PCIE_VDDR
+PCIE_PVDD_12
Circuit to hold PCI-E voltage low and wait for +VDDC for proper power sequence
+3.3V_BUS
R153
100K
402
1
R396
2 3
100R
CMPT3904
Rq3
Rq4
+VDDC
R393
1.50K
R394
3.01K
+VDDC
+1.3V
A A
+1.2V 1.5K 3K
8
Rq3
1.5K
Rq4
2.4K
7
6
CMPT3904
Q28
1
+12V_BUS
2 3
R395
20K
402
402
R397
100R
402
Q29
1
2 3
CMPT3904
Q27
5
VDDC_GOOD_PU (7)
VDDC_GOOD (7)
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
4
3
Date: Sheet
2
105-A260xx-00C
2
of
515Wednesday, March 24, 2004
1
5
4
3
2
1
Place caps very
+12V_BUS
close to power pin
C13
+3.3V_BUS
R811
33R
C800
REG9
D D
TL431CDBVR
5 3
0.8V
1.25V
1.5V
1.8V
1.84V
C C
1.5
1.6V
1.7V
1.8175V
Voltage Req.
3.3V
2.7V
2.65V 301R
2.5V 0R
B B
+MVDDQ +MVDDC
RP2A 0R
RP2B 0R
RP2C 0R
RP2D 0R
+MVDDQ +MVDDC
RP195A 0R
RP195B 0R
RP195C 0R
RP195D 0R
10uF_6.3V
4
NC
1
NC
2
R1 R2Voltage Req.
150R
P/N 3240150000
75R
P/N 3240075000
P/N 316075R000
49.9R
P/N 3240049900
54.9R
P/N 3240054900
49.9R 140R
P/N 3240049900
Rx1 for 1.25V Ref Rx2 for 1.25V RefVoltage Req.
432R
P/N 3240432000
432R
P/N 3240432000
432R
P/N 3240432000
681R
P/N 3240681000
P/N 3160681000 402
Ry1 for 2.5V Ref
1.07K
301R (402, 1%)
P/N 3160301000
(402, 1%) (402, 1%)
P/N 3160301000
P/N 3230000000
P/N 3150000000 402
81
72
63
54
81
72
63
54
2.5V_REF2
R812
100R
1%
R1
402
1.25V_REF2
R813
100R
1%
R2
402
71.5R
P/N 324075R500
75R
603
P/N 3240075000
402 P/N 316075R000 402
75R
P/N 3240075000
P/N 316075R000
140R
P/N 3240140000
603
603
402
P/N 3240140000
2.15K
P/N 3240215100
1.5K
P/N 3240150100
1.21K
P/N 3240121100
1.5K
603
P/N 3240015200
Ry2 for 2.5V Ref
3.32K
P/N 3240332100P/N 3240107100
3.32K
P/N 3240332100
4.99K
P/N 3160499100
DNI
603
1.25V_REF2
1.25V_REF2
2.5V_REF2
2.5V_REF2
R101 1K
R105 1K
R109 1K
DNI
R113 1K
3
402
2
R102 432R
R103
2.15K
Rx2
5
402
6
R107
0R
Rx2
10
402
9
R111
4.99K
402
3160499100
Ry2
12
402
13
R115
0R
402
Ry2
1.61V 432R
1.69V
1.718V
1.75V
Alt. regulator for +PVDD
Vout = 1.8V
Iout = 30mA MAX
A A
+PVDD
R284
33R
R287
Rt1
681R
REG40
AS432S
1
3 2
1%
R290
1.5K
1%
402
Rt2
4
1
2
5
NC
NC
GND_PVSS
5 3
MREG40
SC431LC5SK-1
Alt regulator for +MPVDD
Vout = 1.8V
Iout = 10mA MAX
+MPVDD
+3.3V_BUS +3.3V_BUS+3.3V_BUS
R285
75R
R288
Rt1
681R
402
1%
R291
1.5K
1%
4
NC
1
NC
2
Rt2
402
GND_MPVSS
1
3 2
REG32
AS432S
5 3
MREG32
SC431LC5SK-1
4
Alt. regulator for +TPVDD
Vout = 1.65V ~ 1.85V
Iout = 20mA MAX
100nF
603
X7R
5%
411
U81A
+
1
-
LM324M
U81B
+
7
-
LM324M
R106 681R
DNI
U81C
+
8
-
LM324M
R110 0R
U81D
+
14
-
LM324M
R114 301R
DNI
Rx1
402
3160681000
Rx1
402
Ry1
402
3160301000
Ry1
R286
56R
REG39
AS432S
3 2
C12
100nF
603
X7R
5%
G_MVDDC
G_MVDDQ
Rt1
+MVDDC +3.3V_BUS
Q31
1
CMPT3904
2 3
150mW MAX 350mW MAX
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
+3.3V_BUS
1
1A SOT-223
3 2
350mW MAX
<ATIPartNumbers>
+3.3V_BUS
71
2
8A continuous @ 25'C
6.4A continuous @ 70'C
32A pulse drain current @ 25'C
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
275mW MAX
+3.3V_BUS
53
4
8A continuous @ 25'C
6.4A continuous @ 70'C
32A pulse drain current @ 25'C
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
275mW MAX
32404320001.52V 432R
3160432000 3160215100
3240432000
3240432000432R
562R
3240562000
3160604000604R
3160604000 604R1.8V
+TPVDD
R289
Rt1
604R
402
1%
1
R292
1.37K
1%
4
NC
1
NC
2
Rt2
402402
GND_TPVSS
1
Q32
4
BCP68
1.8V
175mA MAX
8
Q33A
BSO4804
6
Q33B
BSO4804
<ATIPartNumbers>
Rt2
2.15K
1.5K
3230015200
1.5K 3160150100
3240121100
1.21K
32300152001.5K
1.5K 3160150100
32300152001.5K
1.5K 3160150100
31601371001.37K
MREG39
SC431LC5SK-1
5 3
MQ31
4
BCP68
1A SOT-223200mA, SOT-23
3 2
ALT
+VDDC_CT
C302
10uF_6.3V
ALT
+PCIE_PVDD_18
4 5
3
2
1
+1.8V +VDDR4 +PVDD +TPVDD
L4
1.8uH
ALT: 0R
ALT
5260002100
C303
10uF_6.3V
+3.3V_BUS
MQ33
6
7
8
IRF7201
ALT
5.8A continuous @ 70'C
58A pulse drain current @ 25'C
RDS(on) MAX = 50mR@Vgs=4.5V,Id=3.7A
550mW MAX
+MVDDQ
***
C305
C315
470uF_10V
10uF_6.3V
***
3
+Vout_Switcher
L12
1.8uH
ALT: 0R
5260002100
1.5V
150mA MAX
+MPVDD
L9
L8
1.8uH
1.8uH
ALT: 0R ALT: 0R ALT: 0R ALT: 0R
5260002100
5260002100
+VDDR4: 90mA MAX TOTAL
C314
10uF_6.3V
2.5V ~ 2.6V
200mA MAX
+MPVDD: 10mA MAX
+PVDD: 25mA MAX
+MVDDC
***
C304
470uF_10V
***
+MVDDQ +MVDDC
C973
100nF
C974
100nF
C975
100nF
C976
100nF
C977
100nF
C978
100nF
Rails derived from +VDDR4
L10
1.8uH
5260002100
L11
1.8uH
5260002100
+AVDD: 10mA MAX
+A2VDDQ: 20mA MAX
+VDDOI_PINS: 20mA MAX
+TXVDDR_PINS: 20mA MAX
+TPVDD: 50mA MAX
2.5V ~ 2.6V
+MVDDC: 500mA MAX
+MVDDC and +MVDDQ: 700mA MAX
CONSIDER HEATSINK ON FET
Place caps across
+MVDDQ and +MVDDC
Plane Splits
If +MVDDQ and +MVDDC
are shorted, then these
caps should be populated
with 0R Resistors.
2
Alt. regulator for +MVDDC
Vout = 2.5V ~ 2.6V
Iout = 500mA MAX
Voltage Req.
3.34V
[-0.04V/+0.04V]
3.45V 2.43K4.32K
[-0.04V/+0.04V]
[-0.03V/+0.03V]
G_MVDDC
Alt regulator for +MVDDQ
Vout = 2.5V ~ 2.6V
Iout = 200mA MAX
Voltage Req.
1.8V
[-0.09V/+0.18V]
2.5V
2.6V
G_MVDDQ
Alt regulator for +VDDC_CT
Vout = 1.5V
Iout = 150mA MAX
+3.3V_BUS
Rm1
4.32K
1K2.5V 3240100100 1K 3240100100
+12V_BUS
C138
100nF
603
X7R
5%
REG33
AS432S
1
3 2
Rq1
681R
3240681000
3240100100
1K
3240475100
4.75K
+12V_BUS
C136
100nF
603
X7R
5%
REG34
AS432S
1
3 2
REG31
LT1117CST
IN3OUT
CASE
ADJ
1
R293
200R
1%
Need at least a 4.7uF
5 3
NC
NC
5 3
2
4
Rm2
2.55K
R949
750R
/.25W
MREG33
SC431LC5SK-1
4
NC
1
NC
2
Rq2
1.5K
1K
4.32K 3240432100
R277
750R
/.25W
MREG34
SC431LC5SK-1
4
1
2
R294
1.0K
1%
402
+MVDDQ
+VDDC_CT
output cap for stability
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
105-A260xx-00C
1
+MVDDC
R958
1.0K
1%
402
R960
1.0K
1%
402
3230015200
3240100100
R279
Rq1
1.0K
1%
402
R283
1.0K
Rq2
1%
402
of
615Wednesday, March 24, 2004
Rm1
Rm2
2
8
7
6
5
4
3
2
1
DNI
DNI
DNI
+12V_BUS
+Vout_Switcher
411
U82A
3
+
402
402
R119
10K
Rx2
R123
1.50K
Rx2
2
12
13
-
LM324M
R118 0R
U82D
+
-
LM324M
R122 681R
1
402
Rx1
14
Rx1
Q35
4 5
3
6
2
7
1
8
IRF7413A
ALT
9.6A continuous @ 70'C
96A pulse drain current @ 25'C
RDS(on) MAX=18mR@Vgs=4.5V,Id =6.0A
+3.3V_BUS
1
4
1A SOT-223
3 2
350mW MAX
<ATIPartNumbers>
Q36
BCP68
+VDDC
C306
10uF_6.3V
ALTALT
+PCIE_PVDD_18
C308
10uF_6.3V
1.3V 2.5V
8A MAX
MIGHT NEED HEATSINK ON FET
MC308
470uF
+PCIE_PVDD_18: 1.8V 500mA MAX
120mA
+A2VDD
+MVDDC
L5
1.8uH
ALT: 0R
Optional when +Vout_Switcher is above 1.2V
+Vout_Switcher
53
402
402
R127
10K
402
Rx2
R131
10K
402
Rx2
6
10
9
-
LM324M
R126 0R
U82C
+
-
LM324M
R130 0R
7
402
Rx1
ALT
MR128
8
0R
402
DNI
402
Rx1
ALT
U82B
5
+
6
Q37B
4
BSO4804
ALT
6.4A continuous @ 70'C
32A pulse drain current @ 25'C
2W power dissipation @ 25'C
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
+Vout_Switcher
Q37_PIN2
2
R128
0R
71
8
Q37A
BSO4804
ALT
8A continuous @ 25'C
6.4A continuous @ 70'C
32A pulse drain current @ 25'C
2W power dissipation @ 25'C
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
8A continuous @ 25'C
MQ37
4 5
3
402
Q37_PIN2
RP111A 0R
RP111B 0R
RP111C 0R
RP111D 0R
2
1
IRF7413A
6
7
+PCIE_VDDR
8
C309
10uF_6.3V
81
72
63
54
+PCIE_PVDD_12
C310
33uF
ALT
C160
100uF_16V
Multi footprint
+PCIE_VDDR: 1.2V 1300mA MAX
C161
MC160
470uF
C162
22uF
22uF
+PCIE_PVDD_12: 1.2V 250mA MAX
Alt. regulator for +A2VDD
Vout = 2.5V
Iout = 120mA MAX
+A2VDD+3.3V_BUS
REG35
1
VIN
3
SHDN
C139
100nF
402
+A2VDD and GND_A2VSSN routed with at least 15 mil
trace and not longer than 1.5 inch.
Alt. regulator for PCIE_PVDD_18
Vout = 1.85V
Iout = 500mA MAX
+3.3V_BUS
MREG36
LT1117CST
IN3OUT
ADJ
1
BYPASS
GND
2.5V
2
GND_A2VSSN
CASE
R295
681R
402
1%
VOUT
2
4
5
4
+PCIE_PVDD_18
R296
1.50K
1%
Need at least a 4.7uF
output cap for stability
Regulator for +5V
Vout = 5V
Iout = 20mA MAX
REG29
TL431CDBVR
+12V_BUS
5 3
R1042
220R
1206, 1/4W
R1
4
NC
1
NC
2
R2
R1040
1.0K
1%
402
R1041
1.0K
1%
402
+5V
Multi-footprint
C917
10uF_6.3V
MC917
10uf
Place caps very
close to power pin
C14
C15
100nF
100nF
603
603
X7R
X7R
D D
C C
B B
REG8
TL431CDBVR
+3.3V_BUS
5 3
R814
33R
2.5V_REF
4
NC
1
NC
R815
2
324R
R1
1%
402
1.2V_REF
R816
301R
R2
1%
402
5% 5%
1.2V_REF
1.2V_REF
1.2V_REF
1.2V_REF
R117 1K
R121 1K
R125 1K
R129 1K
4
+3.3V_BUS
C166
1.0uF
REG37
MAX1935ETA
1
IN
2
IN2
4
SHDN
3
POK
OUT7
TH_GND9
TH_GND10
TH_GND11
8
OUT
7
6
SET
5
GND
9
10
11
3
+3.3V_BUS
MREG37
R141
1
IN
VDDC_GOOD(5)
A A
R145 0R
8
2.15K
R142
1.24K
REFEN4GND
RT9173ACL5
C157
1.0uF
402
+PCIE_VDDR
3
6
5
VOUT
TAB
VCNTL
2
R143
1K
402
VDDC_GOOD_PU(5)
7
R144 0R
+3.3V_BUS
402
C163
1.0uF
REG38
MAX1935ETA
1
IN
2
IN2
4
SHDN
3
POK
6
OUT7
TH_GND9
TH_GND10
TH_GND11
8
OUT
7
6
SET
5
GND
9
10
11
+PCIE_PVDD_12
R151
1.0K
402
C165
R1
10uf
R152
2K
402
R2 R2
5
+PCIE_PVDD_18
R154
6.81K
402
R1
R155
5.49K
402
Part Vout R1 R2
C167
10uf
MAX1935
0.8V Ref
1.2V
1.79V
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
2
402 402
1.00K 1%
ATI P/N 3160100100 ATI P/N 3160200100
6.81K 1%
ATI P/N 3160681100
105-A260xx-00C
2.00K 1%
402
5.49K 1%
ATI P/N 3160549100
of
715Wednesday, March 24, 2004
1
2
5
4
3
2
1
MDA[63..0](3)
D D
C C
MDA[63..0]
MDA0
RP122A 56R
MDA1
RP122B 56R
MDA2
RP122C 56R
MDA3
RP122D 56R
MDA4
RP118B 56R
MDA5
RP118C 56R
MDA6
RP118A 56R
MDA7
RP118D 56R
MDA8
RP120B 56R
MDA9
RP119B 56R
MDA10
RP119A 56R
MDA11
RP119C 56R
MDA12
RP120D 56R
MDA13
RP120A 56R
MDA14
RP120C 56R
MDA15
RP119D 56R
MDA16
RP121D 56R
MDA17
RP121C 56R
MDA18
RP121B 56R
MDA19
RP121A 56R
MDA20
RP117A 56R
MDA21
RP117B 56R
MDA22
RP117C 56R
MDA23
RP117D 56R
MDA24
RP123B 56R
MDA25
RP123A 56R
MDA26
RP124B 56R
MDA27
RP123D 56R
MDA28
RP123C 56R
MDA29
RP124A 56R
MDA30 M_MDA30
RP124D 56R
MDA31
RP124C 56R
MDA32
RP127C 56R
MDA33
RP127B 56R
RP127A 56R
MDA35
RP127D 56R
MDA36
RP128D 56R
MDA37
RP128C 56R
MDA38
RP128A 56R
MDA39
RP128B 56R
MDA40
RP125B 56R
MDA41
RP125A 56R
MDA42
RP125C 56R
RP126A 56R
MDA44
RP126D 56R
RP126C 56R
MDA46
RP126B 56R
MDA47 M_MDA47
RP125D 56R
MDA48
RP131A 56R
MDA49
RP131C 56R
MDA50
RP131B 56R
MDA51
RP131D 56R
MDA52
RP132B 56R
MDA53
RP132D 56R
MDA54
RP132C 56R
MDA55
RP132A 56R
MDA56
RP129B 56R
MDA57
RP129C 56R
MDA58
RP130D 56R
MDA59
RP129A 56R
MDA60
RP129D 56R
MDA61
RP130B 56R
MDA62
RP130C 56R
MDA63
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RP130A 56R
R759 0R
R760 0R
R761 0R
R762 0R
R764 0R
R763 0R
R765 0R
R766 0R
QSA[7..0]
QSA[7..0](3)
8 1
7 2
6 3
5 4
7 2
5 4
8 1
6 3
5 4
6 3
7 2
8 1
7 2
8 1
5 4
6 3
6 3
7 2
8 1
5 4
5 4
6 3
8 1
7 2
7 2
8 1
6 3
8 1
5 4
6 3
7 2
5 4
8 1
6 3
7 2
5 4
7 2
5 4
6 3
8 1
5 4
7 2
6 3
8 1
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
72
M_MDA5
63
M_MDA6
81
M_MDA7
54
M_MDA8
M_MDA9
72
M_MDA10
81
M_MDA11
63
M_MDA12
M_MDA13
M_MDA14
M_MDA15
54
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
81
M_MDA21
72
M_MDA22
63
M_MDA23
54
M_MDA24
M_MDA25
M_MDA26
72
M_MDA27
M_MDA28
M_MDA29
81
54
M_MDA31
63
M_MDA32
M_MDA33
M_MDA34MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43MDA43
M_MDA44
M_MDA45MDA45
M_MDA46
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
72
M_MDA57
63
M_MDA58
M_MDA59
81
M_MDA60
54
M_MDA61
M_MDA62
M_MDA63
M_MDA[63..0]
SERIES Resistors
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_MDA[63..0] (9)
For Bi-Directional signals,
Series resistors should be
placed close to the memory
M_QSA[7..0]
M_QSA[7..0] (9)
CLOCK
terminations
CLKA0(3,9)
CLKA#0(3,9)
CLKA1(3,9)
CLKA#1(3,9)
M_CLKA0 (3,9)
M_CLKA#0 (3,9)
M_CLKA1
M_CLKA1 (3,9)
M_CLKA#1 (3,9)
M_CLKA0
M_CLKA#0
M_CLKA#1
R797
56R
R798
56R
R799
56R
R800
56R
C778
10nF
C779
10nF
B B
A A
M_DQMA#[7..0](9)
M_MAA[14..0](3,9)
M_RASA#(3,9)
M_CASA#(3,9)
M_WEA#(3,9)
M_CSA#0(3,9)
M_CKEA(3,9)
5
M_DQMA#[7..0]
M_MAA[14..0]
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_MAA1 MAA1
M_MAA3 MAA3
M_MAA4 MAA4
M_MAA6 MAA6
M_MAA8 MAA8
M_MAA9 MAA9
M_MAA10 MAA10
M_MAA11 MAA11
M_MAA14 MAA14
M_RASA#
M_CASA#
M_WEA#
M_CSA#0
M_CKEA
R775 56R
R776 56R
R777 56R
R778 56R
R780 56R
R779 56R
R781 56R
R782 56R
4
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
MAA0M_MAA0
MAA2M_MAA2
MAA5M_MAA5
MAA7M_MAA7
MAA12M_MAA12
MAA13M_MAA13
RASA# (3,9)
CASA# (3,9)
WEA# (3,9)
CSA#0 (3,9)
CKEA (3,9)
DQMA#[7..0]
MAA[14..0]
DQMA#[7..0] (3)
MAA[14..0] (3,9)
For Uni-Directional
signals, Series
resistors should be
placed close to the
ASIC
3
<Variant Name>
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
105-A260xx-00C
1
of
815Wednesday, March 24, 2004
2
8
M_DQMA#[7..0](8)
D D
M_QSA[7..0](8)
C C
M_MAA[14..0](3)
B B
M_DQMA#[7..0]
M_QSA[7..0]
M_CLKA#0(3,8)
M_CLKA#1(3,8)
M_CLKA0(3,8)
M_CLKA1(3,8)
M_CKEA(3)
M_WEA#(3)
M_CASA#(3)
M_RASA#(3)
M_CSA#0(3)
M_MAA[14..0]
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_CLKA0#
M_CLKA1#
M_CLKA0
M_CLKA1
M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
7
C206
402
100nF
C287
100nF
402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA#0
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA1
M_QSA3
M_DQMA#1
M_DQMA#3
M_MAA13
M_MAA12
+MVDDQ
C226
100nF
+VREF_U33 +VREF_U34
C288
100nF
402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA0#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA2
M_QSA0
M_DQMA#2
M_DQMA#0
M_MAA13
M_MAA12
M_MDA[63..0](8)
6
Channel A Bottom Down
U29
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
4MX16X4
<3RD PART FIELD>
402 402
U33
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
4MX16X4
<3RD PART FIELD>
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
M_MDA13
2
DQ0
M_MDA8
4
DQ1
M_MDA14
5
DQ2
M_MDA12
7
DQ3
M_MDA15
8
DQ4
M_MDA11
10
DQ5
M_MDA9
11
DQ6
M_MDA10
13
DQ7
M_MDA25
54
DQ8
M_MDA24
56
DQ9
M_MDA28
57
M_MDA27
59
M_MDA30
60
M_MDA31
62
M_MDA26
63
M_MDA29
65
14
NC
17
19
25
M_MAA14 M_MAA14
42
43
+MVDDC +MVDDC
50
53
1
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
M_MDA23
2
M_MDA22
4
M_MDA21
5
M_MDA20
7
M_MDA19
8
M_MDA18
10
M_MDA17
11
M_MDA16
13
54
M_MDA5
56
M_MDA4
57
M_MDA6
59
M_MDA0
60
M_MDA1
62
M_MDA2
63
M_MDA3
65
14
NC
17
19
25
42
43
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
5
+MVDDQ+MVDDQ
C216
100nF
+VREF_U30+VREF_U29
C289
100nF
402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA5
M_QSA6
M_DQMA#5
M_DQMA#6
M_MAA13
M_MAA12
+MVDDQ
C236
100nF
C290
100nF
402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA7
M_QSA4
M_DQMA#7
M_DQMA#4
M_MAA13
M_MAA12
Channel A Bottom Up
402
U30
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
CK
CK
CKE
CS
RAS
CAS
WE
VDDQ#9
LDQS
UDQS
VDDQ#15
VDDQ#55
VDDQ#61
LDM
UDM
BA0
VSSQ#6
BA1
VSSQ#12
VSSQ#58
VSSQ#64
4MX16X4
<3RD PART FIELD>
U34
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
VDDQ#9
LDQS
UDQS
VDDQ#15
VDDQ#55
VDDQ#61
LDM
UDM
BA0
VSSQ#6
BA1
VSSQ#12
VSSQ#58
VSSQ#64
4MX16X4
<3RD PART FIELD>
Channel A Top UpChannel A Top Down
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VSS#48
VSS#66
VSSQ
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VSS#48
VSS#66
VSSQ
45
46
44
24
23
22
21
16
51
20
47
26
27
49
29
30
31
32
35
36
37
38
39
40
28
41
45
46
44
24
23
22
21
16
51
20
47
26
27
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
4
M_MDA41
2
DQ0
M_MDA40
4
DQ1
M_MDA42
5
DQ2
M_MDA47
7
DQ3
M_MDA43
8
DQ4
M_MDA46
10
DQ5
M_MDA45
11
DQ6
M_MDA44
13
DQ7
M_MDA48
54
DQ8
M_MDA50
56
DQ9
M_MDA49
57
M_MDA51
59
M_MDA55
60
M_MDA52
62
M_MDA54
63
M_MDA53
65
14
NC
17
19
25
42
43
50
53
1
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
M_MDA63
2
M_MDA61
4
M_MDA62
5
M_MDA58
7
M_MDA60
8
M_MDA57
10
M_MDA56
11
M_MDA59
13
M_MDA38M_MDA7
54
M_MDA39
56
M_MDA37
57
M_MDA36
59
M_MDA34
60
M_MDA33
62
M_MDA32
63
M_MDA35
65
14
NC
17
19
25
M_MAA14M_MAA14
42
43
+MVDDC+MVDDC
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
3
R60
4.7K
402 402
+VREF_U29
R61
4.7K
402
+MVDDQ
R68
4.7K
402 402
+VREF_U33
R69
4.7K
+MVDDQ+MVDDQ
+MVDDQ
R62
4.7K
+VREF_U30
R63
4.7K
402
R70
4.7K
+VREF_U34
R71
4.7K
402402
2
1
Put 1 1uF cap per power pin of memory
+MVDDQ
C572
100nF
402 402 402 402 402
+MVDDQ
C592
100nF
A A
C229
100nF
8
7
C231
100nF
C232
100nF
+MVDDC
C574
C573
100nF
C593
100nF
C575
100nF
100nF
+MVDDC
C594
C595
100nF
100nF
402 402402 402 402
+MVDDQ+MVDDC
C235
100nF
402 402402 402 402 402 402402 402 402 402 402
6
C221
100nF
C576
100nF
C596
100nF
C222
100nF
+MVDDQ
+MVDDQ
C577
100nF
C597
100nF
C223
100nF
C578
100nF
C598
100nF
C224
100nF
C579
100nF
C599
100nF
C237
100nF
+MVDDC
C581
C580
100nF
100nF
402 402402 402 402
+MVDDC
C600
C601
100nF
100nF
402 402402 402 402
C243
C239
C238
100nF
5
100nF
100nF
4
3
DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AND DQM ACCORDINGLY
AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS
All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed
per memory chip. As close to the pin as possible.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
2
105-A260xx-00C
2
of
915Wednesday, March 24, 2004
1
8
7
6
5
4
3
2
1
GPIO0
OPTION STRAPS
+3.3V_BUS
D D
C C
Mem_Strap0(2)
Mem_Strap1(2)
B B
LCDDATA16(2)
LCDDATA17(2)
32
SW1B
DIP_SWX2
R250 10K
VHAD0(2)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO11
GPIO12
GPIO13
GPIO9
GPIO8
DNI
R201 10K
R202 10K
R203 10K
R204 10K
R205 10K
R206 10K
R207 10K
R208 10K
R219 10K
R220 10K
R221 10K
R222 10K
R223 10K
R224 10K
R209 10K
R210 10K
R211 10K
R212 10K
R213 10K
R214 10K
R215 10K
R216 10K
R217 10K
R218 10K
R235 10K
R236 10K
R237 10K
R238 10K
R227 10K
R228 10K
R229 10K
R230 10K
R231 10K
R232 10K
DESKTOP
MOBO
DESKTOP
MOBO
DNI
Tumwater
Grantsdale
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
+VDDR4
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
STRAPS
STRAP_B_PTX_PWRS_ENB
STRAP_B_PTX_DEEMPH_EN
PCIE_MODE(1:0)
STRAP_FORCE_COMPLIANCE
STRAP_B_PPLL_BW GPIO6
STRAP_DEBUG_ACCESS Strap to set the debug muxes to bring out DEBUG signals
ROMIDCFG(3:0)
STRAP P
INTERRUPT
LOW
ENABLED (DEFAULT)
DISABLED
HIGH
MEMORY TYPE STRAPS
Mem_Strap0 Mem_Strap1
SAM
00
INF
1
HYN
0
ELPIDA
11
GPIO[6..0]
GPIO[13..8]
0
1
GPIO[6..0] (2)
GPIO[13..8] (2)
DESCRIPTIONPIN
GPIO0
GPIO1
GPIO(3:2)
GPIO4
GPIO5
GPIO8
GPIO(9,13:11)
DVPDATA_20VIP_DEVICE Indicates if any slave VIP host devices drove this in low during reset.
(VHAD0 net)
Tansmitter Power Savings Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing
Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled
00: PCI Express 1.0A mode (Grantsdale)
01: Kyrene-compatible mode
10: PCI Express 1.0 mode (Tumwater)
11: PCI Express 1.0A mode and short-circuit internal loopback mode
(Rx connected directly to Tx of PHY)
Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage - potential power savings for mobile mode
Force chip to go to Compliance state quickly for Tester purposes
0: normal operational mode
1: compliance mode
PLL Bandwidth
0: full PLL Bandwidth
1: reduced PLL bandwidth
even if registers are inaccessible.
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
GPIO8(2)
GPIO9(2)
GPIO10(2)
ROMCS#(3)
R91
10K
+3.3V_BUS
ASIC DEFAULT
0
0
00
0STRAP_B_PTX_IEXT
0
0
0
SERIAL EEPROM 512K
ROM_SO
SI/A16
SCK/WEb
CSb
HOLD1
+3.3V_BUS
C80
100nF
U11
5
D
6
C
1
S
7
HOLD
3
W
8
VCC
M25P05-AVMN6T
2
Q
4
VSS
A A
<Variant Name>
8
7
6
5
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
Date: Sheet
2
105-A260xx-00C
of
10 15Wednesday, March 24, 2004
1
2
8
D D
7
6
5
4
3
2
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
PRIMARY CRT
A_R_DVI-I (12)
A_G_DVI-I (12)
L51 82nH
L52 82nH
L53 82nH
C403
3.3pF
402 402 402
+5V
1
1
5
4
10
9
13
12
32
BSN20
Q51
32
BSN20
Q52
6
U6B
SN74ACT86D
8
U6C
SN74ACT86D
11
U6D
SN74ACT86D
R405
6.8K
402
+5V
R407
6.8K
402
DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
R401 75.0R
R402 75.0R
R403 75.0R
CRT1DDCDATA(1,2)
CRT1DDCCLK(1,2)
A_HSYNC_DAC1(1,2)
A_VSYNC_DAC1(1,2)
Pr
Y
Pb
C402
C401
3.3pF
3.3pF
402 402
402
+3.3V_BUS
R404
4.7K
402
+3.3V_BUS
R406
4.7K
402 402
A_R_DAC1(2)
A_G_DAC1(2)
A_B_DAC1(2)
C C
B B
L54 68nH
L55 68nH
L56 68nH
C405
C406
C404
3.3pF
3.3pF
3.3pF
402
Place close to ASIC
R415 33R
R416 33R
R413
R414
402
51R
51R
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
A_B_DVI-I (12)
BAT54SLT1
D55
3
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
BAT54SLT1
2
1
BAT54SLT1
2
D56
3
1
DDCDATA_DVI-I_R (12)
DDCCLK_DVI-I_R (12)
A_HSYNC_DVI-I_R (12)
A_VSYNC_DVI-I_R (12)
2
D57
3
1
C407
5pF
L60
82nH
+5V +5V+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V+5V
BAT54SLT1
2
D51
3
1
C409
C408
5pF
5pF
L62
L61
82nH
82nH
BAT54SLT1
2
D52
3
1
BAT54SLT1
BAT54SLT1
2
D53
3
1
Place close to CONNECTOR
2
D54
3
1
DB15 pin
11
12
4
15
9
Hardware
Support
Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997
+5V_VESA
C441
68pF
Close to
Connector
GND_CHASSIS
Standard VGA
DDC1 Host
Monitor ID bit 0
Monitor ID bit 0
Monitor ID bit 1
Data from display
Monitor ID bit 2
Monitor ID bit 2
Monitor ID bit 3
Open
+5V
N/C
50mA min
Mechanical Key
1A max
No Yes Yes No Yes
MJ2
1
R
2
G
3
B
11
MS0
DDC2_MONID0
12
MS1
DDC2_MONID1(SDA)
4
MS2
DDC2_MONID2
15
MS3
DDC2_MONID3(SCL)
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
DB15F_slim_RA
6050003000 Old Slim-VGA connector
6052003000 New horizontally aligned Slim-VGA connector
DDC2AB Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
300mA min
1A max
DDC1/2 Display
Optional
SDA
Optional
SCL
Optional
DDC2B or
DDC2B+ Host
Monitor ID bit 0
SDA
Monitor ID bit 2
SCL
+5V
50mA min
1A max
R991 0R
805
R992 0R
805
805
805
805
805
805
GND_CHASSIS
Three on top side, three at
the bottom, spreaded high,
middle and low vertically
7
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
6
5
4
3
Date: Sheet of
2
105-A260xx-00C
11 15Wednesday, March 24, 2004
1
2
R993 0R
R997 0R
R998 0R
A A
8
R999 0R
5
4
3
2
1
PRIMARY DVI-I CONNECTOR
INSTALL TERMINATION RESISTORS CLOSE TO ASIC
R601 330R
D D
C C
TMDS_TX2N(2)
TMDS_TX2P(2)
TMDS_TX1N(2)
TMDS_TX1P(2)
TMDS_TX0N(2)
TMDS_TX0P(2)
TMDS_TXCP(2)
TMDS_TXCN(2)
DDCCLK_DVI-I_R(11)
DDCDATA_DVI-I_R(11)
HPD(2)
402
R602 330R
402
R603 330R
402
R604 330R
402
A_VSYNC_DVI-I_R(11)
LAYOUT NOTE: MAY REMOVE R605-R608 IF THERE'S NO SPACE!
+3.3V_BUS
R606
R605
20K
20K
402 402
Q25
D121
2.5V
DNI
CMPT3904
R609
100K
2 1
2 3
CMPT3904
1
Q26
2 3
A_HSYNC_DVI-I_R(11)
1
A_R_DVI-I(11)
A_G_DVI-I(11)
A_B_DVI-I(11)
R608 20K
R607 20K
DDCCLK_DVI-I
DDCDATA_DVI-I
402
402402
+5V_VESA
Pr
Y
Pb
C510
68pF
DNI
GND_CHASSIS GND_CHASSIS
J2
M1
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
M2
CASE#M2
DVI_A/D
B B
Req = 120.8R
Use 604R, 1206, 1/4W
A A
5
+12V_BUS
R911
220R
R912
220R
R913
220R
REG19
TL431CDBVR
+5V_VESA
R915
R914
220R
220R
4
NC
1
NC
2
5 3
4
R901
1.0K
1%
402
R902
1.0K
1%
402
Multi-footprint
C901
10uF_6.3V
MC901
4.7uF
Normal +5V regulated operation
This circuit provide upto 58mA
If Iload > 58mA, +5V will drop
If Vout is shorted
Current across each Rx is 12V/604R = 20mA
Power dissipated by each Rx is 20mA x 12V = 238mW
Each Rx are rated 250mW (1/4W)
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
2
Date: Sheet of
105-A260xx-00C
1
12 15Wednesday, March 24, 2004
2
8
D D
7
6
5
4
3
2
1
Place Resistors close to ASIC.
A_G/Y_DAC2(2)
A_R/C_DAC2(2)
C C
A_B/COMP_DAC2(2)
B B
A_Y_DAC2
A_C_DAC2
A_COMP_DAC2
R504
75.0R
402
R505
75.0R
402
R506
75.0R
402
L91
1.8uH
C501
82pF
402 402
L92
1.8uH
C503
82pF
L93
1.8uH
C505
82pF
C502
82pF
C504
82pF
402402
C506
82pF
402402
A_Y_DAC2_F
A_C_DAC2_F
A_COMP_DAC2_F
Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EMI
R519 0R
R520 0R
R521 0R
402
402
402
A_Y_DAC2_DIN
A_C_DAC2_DIN
A_COMP_DAC2_DIN
C507
82pF
C508
82pF
C509
82pF
402402 402
SVHS/YPrPbb(2)
R515
0R
R513
220R
+3.3V_BUS
R578
10K
402
R377 0R
PIN1
PIN2
R514
220R
PIN7
TV Out (SVHS)
PIN6
PIN7
PIN5
GND_CHASSIS
1
3
2
GND_CHASSIS
6
3
4
7
5
1
2
8
9
10
MJ6
Jack_Phono_RCA
402
J6
+12V
Y-OUT
C-OUT
Comp_out
SYNC
GND
GND#2
CASE
CASE#9
CASE#10
Connector_DIN_Miniature_Circular_7_Pin
The 7-pin MiniDIN footprint allows one of the two MiniDINs:
- 7-pin Svideo/Composite MiniDIN P/N 6071001500
- 4-pin Svideo MiniDIN P/N 6070001000
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
105-A260xx-00C
2
of
13 15Wednesday, March 24, 2004
1
5
DVI/VGA SCREWS MISC. BOARD PARTS
ASSY1
SCREW
JACKSCREW
D D
C C
B B
ASSY2
SCREW
JACKSCREW
MT1
MT_Hole_0.136_in.
GND_CHASSIS
MT2
MT_Hole_0.136_in.
ASSY7
ANTISTATIC
BAG
6_X_11
ASSY8
BLANK
LABEL
9050005900;9050005900;9050005900;9050005900
4
REF5
ATI LOGO
LABEL
ATI_LOGO_LABEL
ATX Brackets
ASSY10
BRACKET
NO TABS, DVI
ASSY11
BRACKET
TOP TAB (LP), DIN, DVI
8020033000
80200329D0 is removed due to missing symbol
6052003000 New horizontally aligned Slim-VGA connector
ASSY13
BRACKET
Vid Out Slim VGA
6052003000 New horizontally aligned Slim-VGA connector
DVI ATX
DVI+MiniDIN ATX
Slim-VGA ATX
Slim-VGA+MiniDIN ATX
3
LP Brackets
ASSY14
BRACKET
LP, NO TABS, DVI
8020032600
ASSY15
BRACKET
LP, TOP TAB, DIN, DVI
ASSY16
BRACKET
LP VGA
80200328F0
6052003000 New horizontally aligned Slim-VGA connector
ASSY17
BRACKET
LP VID OUT VGA
6052003000 New horizontally aligned Slim-VGA connector
DVI LP
DVI+MiniDIN LP
Slim-VGA LP
Slim-VGA+MiniDIN LP
MASSY16
BRACKET
LP, DUAL TABS, Slim VGA
6050003000 Old Slim-VGA connector
MASSY17
BRACKET
LP, DUAL TABS, DIN, Slim VGA
6050003000 Old Slim-VGA connector
Slim-VGA LP
Slim-VGA+MiniDIN LP
2
+12V_BUS
H100
H101
1
2
JU1
heatsink
7120005800
MH101
HEATSINK
7120002700
HEATSINK
7120005100
Spring push-pin
MH100
HEATSINK
7120008000
ITW push-pin
1
GND_CHASSIS
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
105-A260xx-00C
1
2
of
14 15Wednesday, March 24, 2004
5
4
3
2
1
MEMORY CHANNEL A
D D
TSOP 16Mx16 Memory
MEMORY TERMINATIONS A
CLOCK
MEM A
C C
DAC1
PRIMARY CRT
LOGIC
STRAPS
DVI Connector
BIOS
B B
POWER
REGULATION
ROM
RV370
DAC2
TVOUT Filters
TMDS
TMDS Terminations
Slim-VGA DB15
CONN
TVOUT
CONN
AGP
A A
PCI-Express
5
4
<Variant Name>
REFERENCE
DESIGN
THESE SCHEMATICS ARE
SUBJECT TO MODIFICATION
AND DESIGN IMPROVEMENTS.
PLEASE CONTACT ATI FIELD
APPLICATION ENGINEERING
BEFORE USING THE INFORMATION CONTAINED HEREIN.
3
RESTRICTION
NOTICE
THESE SCHEMATICS CONTAIN
INFORMATION WHICH IS PROPRIETARY
TO AND IS THE PROPERTY OF ATI, AND
MAY NOT BE USED, REPRODUCED OR
DISCLOSED IN ANY MANNER WITHOUT
EXPRESSED WRITTEN PERMISSION
FROM ATI.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
B
2
Date: Sheet
105-A260xx-00C
1
of
15 15Wednesday, March 24, 2004
2
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