AMD PALCE29MA16H-25 Service Manual

查询PALCE29MA16供应商

FINAL

COM’L: H-25

PALCE29MA16H-25

24-Pin EE CMOS Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

■ High-performance semicustom logic

replacement; Electrically Erasable (EE)
technology allows reprogrammability

■ 16 bidirectional user-programmable I/O logic

macrocells for Combinatorial/Registered/
Latched operation

■ Output Enable controlled by a pin or product

terms

■ Varied product term distribution for increased

design flexibility

■ Programmable clock selection with common

pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE polarity

GENERAL DESCRIPTION

The PALCE29MA16 is a high-speed, EE CMOS Pro­grammable Array Logic (PAL) device designed for gen­eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high

■ Register/Latch Preload permits full logic

verification

■ High speed (t

internal = 50 MHz)

■ Full-function AC and DC testing at the factory

for high programming and functional yields
and high reliability

■ 24-pin 300 mil SKINNYDIP and 28-pin plastic

leaded chip carrier packages

■ Extensive third-party software and programmer

support through FusionPLD partners

programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other

= 25 ns, f

PD

= 33 MHz and f

MAX

MAX

BLOCK DIAGRAM

I/OF

CLK/LE

4

I -I

I/OE

0 3

Publication# 08811 Rev. G Amendment/0
Issue Date: June 1993

7

I/O

Logic

V

Macrocell

4 4

4

4

I/O

V

Logic

Macrocell

I/OF

0

4

I/OF

Logic

V

Macrocell

V

Logic

Macrocell

I/OF

6

I/O

4

I/O

1

I/O

7

I/O

Logic

V

Macrocell

4

4

4

V

Logic

Macrocell

I/O

8

4

I/O

0

I/O

I/O

Logic

V

Macrocell

4

Programmable

AND Array

8

4

I/O

V

Logic

Macrocell

I/O

12

12

58x178

12

I/O

Logic

V

Macrocell

V

Logic

Macrocell

I/O

I/O

4

4

I/O

I/O

I/O

V

Logic

Macrocell

4

12

12

4

I/O

V

Logic

Macrocell

I/O

323

I/OF

5456

I/O

V

Logic

Macrocell

4

8

8

4

I/O

V

Logic

Macrocell

I/OF

I/OF

4

I/O

V

Logic

Macrocell

4

4

4

V

Logic

Macrocell

I/OF

4

4

4

I/O

08811G-1

2-349

AMD

GENERAL DESCRIPTION (continued)

semicustom solutions such as gate arrays and standard
cells, including reduced development time and low up­front development cost.

The PALCE29MA16 uses the familiar sum-of-products
(AND-OR) structure, allowing users to customize logic
functions by programming the device for specific appli­cations. It provides up to 29 array inputs and 16 outputs.
It incorporates AMD’s unique input/output logic macro­cell which provides flexible input/output structure and
polarity, flexible feedback selection, multiple Output En­able choices, and a programmable clocking scheme.
The macrocells can be individually programmed as
combinatorial, registered, or latched with active-HIGH
or active-LOW polarity. The flexibility of the logic macro­cells permits the system designer to tailor the device to
particular application requirements.

Increased logic power has been built into the
PALCE29MA16 by providing a varied number of logic

CONNECTION DIAGRAMS
Top View

SKINNYDIP

product terms per output. Of the 16 outputs, 8 outputs
have 4 product terms each, 4 outputs have 8 product
terms each, and the other 4 outputs have 12 product
terms each. This varied product-term distribution allows
complex functions to be implemented in a single PAL
device. Each output can be dynamically controlled by a
common Output Enable pin or Output Enable product
term. Each output can also be permanently enabled or
disabled.

System operation has been enhanced by the addition of
common asynchronous-Preset and Reset product
terms and a power-up Reset feature. The
PALCE29MA16 also incorporates Preload and Obser­vability functions which permit full logic verification of
the design.

The PALCE29MA16 is offered in the space-saving
300-mil SKINNYDIP package as well as the plastic
leaded chip carrier package.

PLCC

Note:

CLK/LE

I/OF
I/OF

I/O
I/O
I/O

I/O
I/OF
I/OF

I/OE

GND

1
2

I

0

3

0

4

1
0

5
6

1

7

2

8

3

9

2

10

3

11
12

24
23
22
21
20

19
18

17
16
15
14
13

V

CC

I

3

I/OF

7

I/OF

6

I/O

7

I/O

6

I/O

5

I/O

4

I/OF

5

I/OF

4

I

2

I

1

08811G-2

Pin 1 is marked for orientation.

PIN DESIGNATIONS

CLK/LE = Clock or Latch Enable
GND = Ground
I = Input
I/O = Input/Output
I/OF = Input/Output with Dual Feedback
V

CC

NC = No Connection

= Supply Voltage

I/OF

I/O
I/O

NC
I/O
I/O

I/OF

7

CC

NC

I/OF0I0CLK/LE

5

1

6

0

7

1

8
9

2

10

3

11

2

12

131715 1614 18

3

I/OE

I/OF

V

I3I/OF

1324282726

I/OF

25
24

I/O
I/O

23
22

NC
I/O

21

I/O

20

I/OF

19

2

4

I1I

NC

GND

I/OF

08811G-3

6

7
6

5
4

5

2-350 PALCE29MA16H-25

AMD

ORDERING INFORMATION
Commercial Products

AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of these elements:

PAL CE 29 MA 16 H -25 C /4

FAMILY TYPE

PAL = Programmable Array Logic

TECHNOLOGY

CE = CMOS Electrically Erasable

NUMBER OF ARRAY INPUTS
OUTPUT TYPE

MA = Advanced Asynchronous Macrocell

NUMBER OF FLIP-FLOPS

POWER

H = Half Power (100 mA)

SPEED

-25 = 25 ns

Valid Combinations

PALCE29MA16H-25 PC, JC

/4

P

OPTIONAL PROCESSING

Blank = Standard Processing

PROGRAMMING REVISION

/4 = First Revision

(Requires current
programming Algorithm)

TEMPERATURE RANGE

C = Commercial (0

PACKAGE TYPE

P = 24-Pin Plastic SKINNYDIP

(PD3024)

J = 28-Pin Plastic Leaded Chip

Carrier (PL 028)

Valid Combinations

Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.

°C to +75°C)

2-351PALCE29MA16H-25 (Com’l)

AMD

FUNCTIONAL DESCRIPTION
Inputs

The PALCE29MA16 has 29 inputs to drive each product
term (up to 58 inputs with both TRUE and complement
versions available to the AND array) as shown in the
block diagram in Figure 1. Of these 29 inputs, 4 are
dedicated inputs, 16 are from eight I/O logic macrocells
with two feedbacks, 8 are from other I/O logic macro­cells with single feedback and one is the I/OE input.

Initially the AND-array gates are disconnected from all
the inputs. This condition represents a logical TRUE for
the AND array. By selectively programming the EE cells,
the AND array may be connected to either the TRUE in­put or the complement input. When both the TRUE and
complement inputs are connected, a logical FALSE re­sults at the output of the AND gate.

Product Terms

The degree of programmability and complexity of a PAL
device is determined by the number of connections that
form the programmable-AND and OR gates. Each pro­grammable-AND gate is called a product term. The
PALCE29MA16 has 178 product terms; 112 of these
product terms provide logic capability and others are ar­chitectural product terms. Among the control product
terms, one is for Observability, and one is for Preload.
The Output Enable of each macrocell can be pro­grammed to be controlled by a common Output Enable
pin or an individual product term. It may also be perma­nently disabled. In addition, independent product terms
for each macrocell control Preset, Reset and CLK/LE.

Each product term on the PALCE29MA16 consists of a
58-input AND gate. The outputs of these AND gates are
connected to a fixed-OR plane. Product terms are allo­cated to OR gates in a varied distribution across the

device ranging from 4 to 12 wide, with an average of 7
logic product terms per output. An increased number of
product terms per output allows more complex functions
to be implemented in a single PAL device. This flexibility
aids in implementing functions such as counters, exclu­sive-OR functions, or complex state machines, where
different states require different numbers of product
terms.

Individual asynchronous-Preset and Reset product
terms are connected to all Registered or Latched I/Os.

When the asynchronous-Preset product term is as­serted (HIGH) the register or latch will immediately be
loaded with a HIGH, independent of the clock. When the
asynchronous-Reset product term is asserted (HIGH)
the register or latch will be immediately loaded with a
LOW, independent of the clock. The actual output state
will depend on the macrocell polarity selection. The
latches must be in latched mode (not transparent mode)
for the Reset, Preset, Preload, and power-up Reset
modes to be meaningful.

Input/Output Logic Macrocells

The I/O logic macrocell allows the user the flexibility of
defining the architecture of each input or output on an in­dividual basis. It also provides the capability of using the
associated pin either as an input or an output.

The PALCE29MA16 has 16 macrocells, one for each
I/O pin. Each I/O macrocell can be programmed for
combinatorial, registered or latched operation (see Fig­ure 2). Combinatorial output is desired when the PAL
device is used to replace combinatorial glue logic. Reg­isters and Latches are used in synchronous logic
applications. Registers and Latches with product term
controlled clocks can also be used in asychronous
application.

Common I/OE (Pin)

Individual OE

Individual Asynchronous Preset

P0

P7 or P11

Common CLK/LE (PIN)

Individual CLK/LE

Individual Asynchronous Reset

To AND Array

S4

1
0

S3
1 1
1 0
0 1
0 0

S5

1
0

S8

S2

Preset

D

CLK/LE

V

Reset

Figure 2a. PALCE29MA16 Macrocell (Single Feedback)

2-352 PALCE29MA16H-25

V

CC

1 1
0 1

S0

R

1 0
0 0

X

Q

Q

S1

S6

0 1
1 1
1 0
0 0

S7

I/O

X

08811G-4

AMD

The output polarity for each macrocell in each of the
three modes of operation is user-selectable, allowing
complete flexibility of the macrocell configuration.

Eight of the macrocells (I/OF

–I/OF7) have two inde-

0

pendent feedback paths to the AND array (see Figure
2b). The first is a dedicated I/O pin feedback to the AND
array for combinatorial input. The second path consists
of a direct register/latch feedback to the array. If the pin
is used as a dedicated input using the first feedback
path, the register/latch feedback path is still available to
the AND array. This path provides the capability of using
the register/latch as a buried state register/latch. The
other eight macrocells have a single feedback path to
the AND array. This feedback is user-selectable as
either an I/O pin or a register/latch feedback (see
Figure2a).

Each macrocell can provide true input/output capability.
The user can select each macrocell register/latch to be
driven by either the signal generated by the AND-OR ar­ray or the corresponding I/O pin. When the I/O pin is se­lected as the input, the feedback path provides the
register/latch input to the array. When used as an input,
each macrocell is also user-programmable for regis­tered, latched, or combinatorial input.

The PALCE29MA16 has a dedicated CLK/LE pin and
one individual CLK/LE product term or macrocell. All
macrocells have a programmable switch to choose be­tween the CLK/LE pin and the CLK/LE product term as
the clock or latch enable signal. These signals are clock
signals for macrocells configured as registers and latch
enable signals for macrocells configured as latches.
The polarity of these CLK/LE signals is also individually
programmable. Thus different registers or latches can
be driven by different clocks and clock phases.

The Output-Enable mode of each of the macrocells can
be selected by the user. The I/O pin can be configured
as an output pin (permanently enabled) or as an input
pin (permanently disabled). It can also be configured as

a dynamic I/O controlled by the Output Enable pin or by
a product term.

I/O Logic Macrocell Configuration

AMD’s unique I/O macrocell offers major benefits
through its versatile, programmable input/output cell
structure, multiple clock choices, flexible Output Enable
and feedback selection. Eight I/O macrocells with single
feedback contain 9 EE
crocells contain 8 EE cells for programming the input/
output functions (see Table 1).

EE cell S

controls whether the macrocell will be combi-

1

natorial or registered/latched. S
larity (active-HIGH or active-LOW). S
whether the storage element is a register or a latch. S
allows the use of the macrocell as an input register/latch
or as an output register/latch. It selects the direction of
the data path through the register/latch. If connected to
the usual AND-OR array output, the register/latch is an
output connected to the I/O pin. If connected to the I/O
pin, the register/latch becomes an input register/latch to
the AND array using the feedback data path.

Programmable EE cells S
lect one of the four CLK/LE signals for each macrocell.

and S7 are used to control Output Enable as pin con-

S

6

trolled, product-term controlled, permanently enabled or
permanently disabled. S
plexer for the macrocells with a single feedback path
only.

Using the programmable EE cells S
and output configurations can be selected. Some of the
possible configuration options are shown in Figure 3.

In the erased state (charged, disconnected), an archi­tectural cell is said to have a value of “1”; in the pro­grammed state (discharged, connected to GND), an
architectural cell is said to have a value of “0.”

cells, while the other eight ma-

controls the output po-

0

determines

2

and S5 allow the user to se-

4

controls a feedback multi-

8

various input

0–S8

3

Common I/OE (Pin)

Individual OE

Individual Asynchronous Preset

P0

P3

Common CLK/LE (PIN)

Individual CLK/LE

Individual Asynchronous Reset

To AND Array
To AND Array

Figure 2b. PALCE29MA16 Macrocell (Dual Feedback)

S4

1 1
1 0
0 1
0 0

S5

S3

V

CC

1 1

S0

RF

0 1
1 0
0 0

X

S2

Preset

D

CLK/LE

V

Reset

Q

Q

1
0

S1

S6

0 1
1 1
1 0
0 0

S7

I/OF

08811G-5

X

2-353PALCE29MA16H-25

AMD

Table 1a. PALCE29MA16 I/O Logic Macrocell Architecture Selections

S

3

I/O Cell

1 Output Cell
0 Input Cell

S

1

Output Type

1 Combinatorial
0 Register/Latch

S

8

Feedback*

S

2

Storage Element

1 Register
0 Latch

S

0

Output Polarity

1 Active LOW
0 Active HIGH

1 Register/Latch
0 I/O

*Applies to macrocells with single feedback only.

Table 1b. PALCE29MA16 I/O Logic Macrocell Clock Polarity and Output Enable Selections

S

S5Clock Edge/Latch Enable Level

4

1 1 CLK/LE pin positive-going edge, active-LOW LE*
1 0 CLK/LE pin negative-going edge, active-HIGH LE*
0 1 CLK/LE PT positive-going edge, active-LOW LE*
0 0 CLK/LE PT negative-going edge, active-HIGH LE*

S

S7Output Buffer Control

6

1 1 Pin-Controlled Three-State Enable
1 0 PT-Controlled Three-State Enable
0 1 Permanently Enabled (Output only)
0 0 Permanently Disabled (Input only)

Notes:

1 = Erased State (Charged or disconnected).
0 = Programmed State (Discharged or connected).
*Active-LOW LE means that data is stored when the

LE

is transparent when the

pin is LOW. Active-HIGH LE means the opposite.

LE

pin is HIGH, and the latch

2-354 PALCE29MA16H-25

AMD

SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL

(For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are
independently programmable).

DQ

Q

V

08811G-6

Output Registered/Active Low

S = 1

0

S = 0

1

S = 1

3

S = 1

2

Output Combinatorial/Active Low

DQ

Q

V

S = 1

0

S = 1

1

S = 1

3

08811G-7

DQ

Q

V

S = 0

0

S = 0

1

S = 1

3

S = 1

2

08811G-8

Output Registered/Active High

Figure 3a. Dual Feedback Macrocells

DQ

V

Q

S = 1

0

S = 0

1

S = 1

3

S = 0

8

S = 1

2

08811G-10

Output Registered/Active Low, I/O Feedback

DQ

Q

V

S = 0

0

S = 1

1

S = 1

3

08811G-9

Output Combinatorial/Active High

S = 1

0

S = 1

1

S = 1

3

S = 0

8

08811G-11

Output Combinatorial/Active Low, I/O Feedback

DQ

LE

Q

S = 0

0

S = 0

1

S = 1

3

S = 0

8

S = 0

2

08811G-12

Output Latched/Active High, I/O Feedback

Figure 3b. Single Feedback Macrocells

S = 0

0

S = 1

1

S = 1

3

S = 0

8

08811G-13

Output Combinatorial/Active High, I/O Feedback

2-355PALCE29MA16H-25

AMD

SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL

DQ

Q

V

S = 1
S = 0
S = 1
S = 1
S = 1

08811G-14

Output Registered/Active Low,

Register Feedback

DQ

LE

Q

S = 1

0

S = 0

1

S = 1

3

S = 1

8

S = 0

2

08811G-16

Output Latched/Active Low,

Latched Feedback

0
1
3
8
2

DQ

V

Q

Output Combinatorial/Active Low,

Latched Feedback

DQ
LE

Q

Output Combinatorial/Active Low,

Latched Feedback

S = 1

0

S = 1

1

S = 1

3

S = 1

8

S = 1

2

08811G-15

S = 1

0

S = 1

1

S = 1

3

S = 1

8

S = 0

2

08811G-17

Figure 3b. Single Feedback Macrocells (Continued)

D

Q

V

PROGRAMMABLE-AND ARRAY

S = 0

3

S = 1 (FOR SINGLE FEEDBACK ONLY)

8

S = 1 REGISTER

2

= 0 LATCH

Programmable-AND Array

Figure 3c. All Macrocells

08811G-18

2-356 PALCE29MA16H-25