AMD PALCE20V8 Service Manual

查询PALCE20V8H-20JC供应商

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25

PALCE20V8 Family

EE CMOS 24-Pin Universal Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

■ Pin and function compatible with all GAL

20V8/As

■ Electrically erasable CMOS technology pro-

vides reconfigurable logic and full testability

■ High-speed CMOS technology

— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version

■ Direct plug-in replacement for a wide range of

24-pin PAL devices

■ Programmable enable/disable control

■ Outputs individually programmable as

registered or combinatorial

GENERAL DESCRIPTION

The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.

Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack­ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.

The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement

■ Peripheral Component Interconnect (PCI)

compliant

■ Preloadable output registers for testability

■ Automatic register reset on power-up

■ Cost-effective 24-pin plastic SKINNYDIP and

28-pin PLCC packages

■ Extensive third-party software and programmer

support through FusionPLD partners

■ Fully tested for 100% programming and func-

tional yields and high reliability

■ Programmable output polarity

■ 5-ns version utilizes a split leadframe for

improved performance

complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa­tions are programmed into the device through floating­gate cells in the AND logic array that can be erased
electrically.

The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura­tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.

Advanced

Micro

Devices

BLOCK DIAGRAM

Input

MACRO

Mux.

OE/I11I

Publication# 16491 Rev. D Amendment/0
Issue Date: February 1996

MC

12

I1 – I

10

10

Programmable AND Array

40 x 64

MACRO MACRO MACRO MACRO MACRO MACRO MACRO

MC

0

I/O

0

I/O

MC

1

1

I/O

MC

2

2

I/O

MC

3

4

I/O

MC

4

5

4

I/O

5

MC

I/O

CLK/I

0

Input

I/O

Mux.

7

I

7

13

16491D-1

MC

6

6

2-155

AMD

CONNECTION DIAGRAMS
(Top View)

SKINNYDIP PLCC/LCC

CLK/I

GND

1

0

2

I

1

3

I

2

4

I

3

I

4

5
6

I

5

7

I

6

8

I

7

9

I

8

10

I

9

11

I

10

12

24
23
22
21
20

19
18

17
16
15
14
13

V

CC

I

13

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

I

12

OE/I

11

16491D-2

NC

0

7

CLK/I

NC

CC

V

I13I/O

I2I

1

1324282726

I

5

3

I

6

4

I

7

5

8

I

9

6

10

I

7

I

11

8

12

131715 1614 18

9

I

10

I

GND

NC

11

12

I

OE/I

25
24

23
22

21
20
19

0

I/O

16491D-3

I/O
I/O

I/O
NC
I/O
I/O
I/O

6
5

4

3
2
1

Note:
Pin 1 is marked for orientation.

PIN DESIGNATIONS

CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
NC = No Connect
OE = Output Enable

= Supply Voltage

V

CC

2-156 PALCE20V8 Family

AMD

ORDERING INFORMATION
Commercial and Industrial Products

AMD programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:

FAMILY TYPE

PAL = Programmable Array Logic

TECHNOLOGY

CE = CMOS Electrically Erasable

NUMBER OF ARRAY INPUTS

OUTPUT TYPE

V = Versatile

NUMBER OF FLIP-FLOPS

POWER

CC

CC

)

)

H = Half Power (90-125 mA I
Q = Quarter Power (55 mA I

SPEED

-5 = 5 ns t

-7 = 7.5 ns t

-10 = 10 ns t

-15 = 15 ns t

-20 = 20 ns t

-25 = 25 ns t

PD

PD
PD
PD
PD

PD

PAL CE 20 V 8 H -5 P C

/5

PROGRAMMING DESIGNATOR

Blank = Initial Algorithm
/4 = First Revision
/5 Second Revision

(Same algorithm as /4)

OPERATING CONDITIONS

C = Commercial (0
I = Industrial (–40

°C to +75°C)

°C to +85°C)

PACKAGE TYPE

P = 24-Pin 300 mil Plastic

SKINNYDIP (PD3024)

J = 28-Pin Plastic Leaded Chip

Carrier (PL 028)

Valid Combinations

PALCE20V8H-5 JC

PALCE20V8H-7
PALCE20V8H-10

PC, JC
PALCE20V8Q-10
PALCE20V8H-15
PALCE20V8Q-15
PALCE20V8Q-20
PALCE20V8H-25
PALCE20V8Q-25

PC, JC, PI, JI

PC, JC

PI, JI

PC, JC, PI, JI

/5

Blank, /4

/5

Blank,

/4

Valid Combinations

Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of spe­cific valid combinations and to check on newly re­leased combinations.

PALCE20V8H-15/25, Q-20/25 (Ind)

2-157PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com’l)

AMD

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC
Each macrocell can be configured as a registered out­put, combinatorial output, combinatorial I/O, or dedi­cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen­tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (OE) for all flip-flops.

Unused input pins should be tied directly to V
Product terms with all bits unprogrammed (discon­nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are
automatically configured from the user’s design specifi­cation, which can be in a number of formats. The design

11
0X

10

..MC7).

0

or GND.

CC

specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.

The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu­lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec­ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili­zation of the macrocells, allowing non-standard archi­tectures to be built.

To

Adjacent

11

OE

V

CC

10
00
01

Macrocell

SL0

SG1

SL1

X

* In Macrocells MC0 and MC7, SG1 is replaced by

Figure 1. PALCE20V8 Macrocell

X

DQ

CLK

SG0

on the feedback multiplexer.

Q

*SG1

11
0X

10

10
11
0X

SL0

X

16491D-4

From
Adjacent
Pin

I/O

X

2-158 PALCE20V8 Family

AMD

Configuration Options

Each macrocell can be configured as one of the follow­ing: registered output, combinatorial output, combinato­rial I/O or dedicated input. In the registered output
configuration, the output buffer is enabled by the OE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always dis­abled. A macrocell configured as a dedicated input de­rives the input signal from an adjacent I/O.

The macrocell configurations are controlled by the con­figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL0
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE20V8
will emulate a PAL20R8 family or a combinatorial de­vice. Within each macrocell, SL0
SG1, selects the configuration of the macrocell and
SL1

sets the output as either active low or active high.

x

The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul­tiplexers: a product term input, an enable select, an out­put select, and a feedback select multiplexer. SG1 and

are the control signals for all four multiplexers. In

SL0

x

MC

and MC

0

, SG0 replaces SG1 on the feedback

7

multiplexer.
These configurations are summarized in table 1 and il-

lustrated in figure 2.

through SL07 and SL1

0

, in conjunction with

x

Dedicated Output in a Non-Registered
Device

The control settings are SG0 = 1, SG1 = 0, and SL0x = 0.
All eight product terms are available to the OR gate. Al­though the macrocell is a dedicated output, the feed­back is used, with the exception of pins 18(21) and
19(23). Pins 18(21) and 19(23) do not use feedback in
this mode.

Dedicated Input in a Non-Registered
Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0

1. The output buffer is disabled. The feedback signal is

0

an adjacent I/O pin.

Combinatorial I/O in a Non-Registered
Device

The control settings are SG0 = 1, SG1 = 1, and SL0x = 1.
Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the I/O pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.

Combinatorial I/O in a Registered Device

The control bit settings are SG0=0,SG1=1 and SL0x =1.
Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.

=

x

If the PALCE20V8 is configured as a combinatorial de­vice, the CLK and OE pins may be available as inputs to
the array. If the device is configured with registers, the
CLK and OE pins cannot be used as data inputs.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0

0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1

. SL1x is an input to

x

the exclusive-OR gate which is the D input to the flip­flop. SL1

is programmed as 1 for inverted output or 0

x

for non-inverted output. The flip-flop is loaded on the
LOW-to-HIGH transition of CLK. The feedback path is
from Q on the register. The output buffer is enabled by
OE.

x

Combinatorial Configurations

The PALCE20V8 has three combinatorial output con­figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.

Table 1. Macrocell Configurations

SG0 SG1 SL0xCell Configuration Devices Emulated

Device has registers

=

0 1 0 Registered PAL20R8, 20R6,

Output 20R4

0 1 1 Combinatorial I/O PAL20R6, 20R4

Device has no registers

1 0 0 Combinatorial PAL20L2,

Output 18L4,16L6,14L8

1 0 1 Dedicated Input PAL20L2,18L4,

16L6

1 1 1 Combinatorial I/O PAL20L8

Programmable Output Polarity

The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.

Selection is made through a programmable bit SL1
which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1
and active low if SL1

is a 1.

x

is a 0

x

x

2-159PALCE20V8 Family

AMD

OE

CLK

Registered Active Low

DQQ

OE

DQQ

CLK

Registered Active High

Combinatorial I/O Active Low Combinatorial I/O Active High

V

CC

Note 1 Note 1

Combinatorial Output Active Low

Notes:

1. Feedback is not available on pins 18 (21)
and 19 (23) in the combinatorial output mode.

2. This macrocell configuration is not available on
pins 18 (21) and 19 (23).

V

CC

Combinatorial Output Active High

Note 2

Adjacent I/O pin

Figure 2. Macrocell Configurations

2-160 PALCE20V8 Family

Dedicated Input

16491D-5

AMD

Power-Up Reset

All flip-flops power up to a logic LOW for predictable sys­tem initialization. Outputs of the PALCE20V8 depend on
whether they are selected as registered or combinato­rial. If registered is selected, the output will be HIGH. If
combinatorial is selected, the output will be a function of
the logic.

Register Preload

The register on the PALCE20V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load­ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.

Security Bit

A security bit is provided on the PALCE20V8 as a deter­rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com­petitors. The bit can only be erased in conjunction with
the array during an erase cycle.

Electronic Signature Word

An electronic signature word is provided in the
PALCE20V8. It consists of 64 bits of programmable
memory that can contain any user-defined data. The
signature data is always available to the user independ­ent of the security bit.

Programming and Erasing

The PALCE20V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ­ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard­ware. No special erase operation is required.

Quality and Testability

The PALCE20V8 offers a very high level of built-in qual­ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro­gramming and post-programming functional yields in
the industry.

Technology

The high-speed PALCE20V8H is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.

PCI Compliance

The PALCE20V8H-7/10 is fully compliant with the

Local Bus Specification

terest Group. The PALCE20V8H-7/10’s predictable tim­ing ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD
and FPGA architectures without predictable timing, PCI
compliance is dependent upon routing and product term
distribution.

published by the PCI Special In-

PCI

2-161PALCE20V8 Family

AMD

LOGIC DIAGRAM
SKINNYDIP (PLCC and LCC) Pinouts

CLK/I

0

I

1

I

2

I

3

I

4

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 39

1

(2)

2

(3)

0

7

3

(4)

8

15

4

(5)

16

23

5

(6)

SG0

1
0

1 1

Q

Q

Q

1 0

0 0

V

CC

0 1

1 1

0 X
1 0

1 0
1 1
0 X

SG0

SL0

7

1 1
1 0

0 0

V

CC

0 1

1 1
0 X

1 0

1 0
1 1
0 X

SG1

SL0

6

1 1
1 0
0 0

V

CC

0 1

1 1

0 X

1 0

1 0

1 1

0 X

SG1

SL0

5

1 1
0 X

1 0

SL0

7

SG1

DQ

1 1
0 X

1 0

SL0

6

SG1

DQ

1 1

0 X
1 0

SL0

5

SG1

DQ

(28)

23

(27)

24

V

CC

I

13

I/O

22

7

(26)

I/O

21

6

(25)

I/O

20

5

(24)

24

31

I

6

5

(7)

03478111215161920 2427283132353639

23

2-162 PALCE20V8 Family

1 1

Q

1 0
0 0

V

CC

0 1

1 1

SG1

0 X

1 0

1 0
1 1
0 X

SL0

4

19

(23)

I/O

4

1 1
0 X

1 0

SL0

4

SG1

DQ

CLK OE

16491D-6

LOGIC DIAGRAM (continued)
SKINNYDIP (PLCC and LCC) Pinouts

AMD

0 3 4 7 8 111215161920232427283132353639

1 1
0 X

1 0

32

39

7

I

6

(9)

1 1

0 X
1 0

40

47

I

8

7

(10)

1 1
0 X

1 0

48

55

9

I

8

(11)

SG1

SG1

SG1

SL0

SL0

SL0

CLK OE

3

2

1

DQ

Q

DQ

Q

DQ

Q

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

1 0
1 1

0 X

SG1

SL0

3

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

1 0
1 1
0 X

SG1

SL0

2

1 1
1 0
0 0

V

CC

0 1

1 1
0 X

1 0

1 0
1 1
0 X

SL0

SG1

1

18

(21)

17

(20)

16

(19)

I/O

3

I/O

2

I/O

1

1 1

Q

1 0
0 0

V

CC

0 1

1 1

SG0

0 X
1 0

1 0
1 1

0 X

SL0

0

(18)

14

(17)

13

(16)

I/O

15

0

I

12

OE/I

11

1 1
0 X

1 0

SL0

56

SG1

0

DQ

63

I

10

9

(12)

11

10

(13)

0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536

39

SG0

0
1

16491D-6

(concluded)

2-163PALCE20V8 Family

AMD

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

CC

CC

+ 0.5 V. . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +75°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

with Respect to Ground +4.75 V to +5.25 V. . . . . . . .

Operating ranges define those limits between which the func­tionality of the device is guaranteed.

) Operating

A

)

CC

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0°C to +75°C) 100 mA. . . . . . . . . . . . . . . . . . . .

A

Stresses above those listed under Absolute Maximum Rat­ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi­mum Ratings for extended periods may affect device reliabil­ity. Programming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

I

OZH

I

OZL

I

SC

I

CC

Notes:

1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included.

2. I/O pin leakage is the worst case of I

3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V

OUT

= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

Output HIGH Voltage IOH = –3.2 mA VIN = V

= Min

V

CC

Output LOW Voltage IOL = 24 mA V

= Min

V

CC

IN

= V

IH

or V

IH

or V

IL

IL

2.4 V

0.5 V

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 1)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 1)
Input HIGH Leakage Current VIN = 5.25 V, V
Input LOW Leakage Current V
Off-State Output Leakage V

Current HIGH V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V

= 0 V, V

IN

= 5.25 V, V

OUT

= V

IN
OUT

IN
OUT

or VIL (Note 2)

IH

= 0 V, V

= V

or VIL (Note 2)

IH

= 0.5 V, VCC = Max (Note 3) –30 –150 mA

Supply Current Outputs Open (I

= Max, f = 15 MHz 55

V

CC

IL

and I

OZL

(or IIH and I

OZH

= Max (Note 2) 10 µA

CC

= Max (Note 2) –100 µA

CC

= Max 10 µA

CC

= Max –100 µA

CC

= 0 mA) 90

OUT

H
Q

).

mA

2-172 PALCE20V8H-15/25 Q-15/25 (Com’l)

AMD

CAPACITANCE (Note 1)

Parameter

Symbol Parameter Description Test Conditions Typ Unit

C

C

OUT

IN

Input Capacitance V
Output Capacitance V

= 2.0 V VCC = 5.0 V, TA = 25°C, 5 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)

Parameter

Symbol Parameter Description Min Max Min Max Unit

t

PD

t

S

t

H

t

CO

t

WL

t

WH

fMAX Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) 50 40 MHz

t

PZX

t

PXZ

t

EA

t

ER

Input or Feedback to Combinatorial Output 15 25 ns
Setup Time from Input or Feedback to Clock 12 15 ns
Hold Time 0 0 ns
Clock to Output 10 12 ns

LOW 8 12 ns

Clock Width

Maximum

HIGH 8 12 ns
External Feedback 1/(tS + tCO) 45.5 37 MHz

Frequency
(Note 3)

No Feedback 1/(tWH + tWL) 62.5 41.6 MHz

OE to Output Enable 15 20 ns
OE to Output Disable 15 20 ns

Input to Output Enable Using Product Term Control 15 25 ns
Input to Output Disable Using Product Term Control 15 25 ns

-15 -25

Notes:

2. See Switching Test Circuit for test conditions.

3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.

4. t

CF

is a calculated value and is not guaranteed. tCF can be found using the following equation:

CF

= 1/f

MAX

t

(internal feedback) – tS.

PALCE20V8H-15/25 Q-15/25 (Com’l)

2-173

AMD

SWITCHING WAVEFORMS

Input or

Feedback

Combinatorial

Output

Clock

V

T

t

PD

V

Combinatorial Output

t

WH

t

WL

Clock Width

T

16491D-7

16491D-9

Input or

Feedback

Clock

Registered

Output

t

S

V

T

t

H

V

T

t

CO

V

T

16491D-8

Registered Output

Input

V

T

Output

t

ER

V

- 0.5V

OH

V

+ 0.5V

OL

V

T

t

16491D-10

EA

V

T

Input to Output Disable/Enable

OE

Output

Notes:

1. V

= 1.5 V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns – 5 ns typical.

V

T

t

PXZ

- 0.5V

V

OH

V

+ 0.5V

OL

16491D-11

OE to Output Disable/Enable

t

PZX

V

T

2-176 PALCE20V8 Family

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

AMD

SWITCHING TEST CIRCUIT

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

Specification S

t

, t

PD

CO

t

, t

PZX

EA

t

, t

PXZ

ER

5 V

S

1

R

1

Output

R

C

L

Switching Test Circuit

Commercial

1

C

L

R

1

2

16491D-12

R

2

Measured

Output Value

Closed 1.5 V
Z → H: Open 50 pF 200 Ω 390 Ω 1.5 V

Z → L: Closed
H →Z: Open 5 pF H-5: H →Z: VOH – 0.5 V

L →Z: Closed 200 Ω L → Z: V

+ 0.5 V

OL

2-177PALCE20V8 Family

AMD

TYPICAL ICC CHARACTERISTICS
V

= 5.0 V, TA = 25°C

CC

150

I

CC

(mA)

125

100

75

50

25

0

01020304050

20V8H-5

20V8H-7
20V8H-10

20V8H-15/25

20V8Q-10

20V8Q-15/25

Frequency (MHz)

16491D-13

ICC vs. Frequency

The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.

CC

By utilizing 50% of the device, a midpoint is defined for I

CC

estimate the I

requirements for a particular design.

. From this midpoint, a designer may scale the ICC graphs up or down to

2-178 PALCE20V8 Family

AMD

ENDURANCE CHARACTERISTICS

The PALCE20V8 is manufactured using AMD’s ad­vanced electrically erasable process. This technology

uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.

Endurance Characteristics

Symbol Parameter Test Conditions Min Unit

t

DR

N Min Reprogramming Cycles Normal Programming Conditions 100 Cycles

Min Pattern Data Retention Time Max Storage Temperature 10 Years

Max Operating Temperature 20 Years

2-179PALCE20V8 Family

AMD

POWER-UP RESET

The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro­vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.

Parameter

Symbol Parameter Description Min Max Unit

t

PR

t

S

t

WL

Registered

Power-Up Reset Time 1000 ns
Input or Feedback Setup Time
Clock Width LOW

4 V

Power

t

Output

Due to the synchronous operation of the power-up reset
and the wide range of ways V

can rise to its steady

CC

state, two conditions are required to insure a valid
power-up reset. These conditions are:

■ The V

■ Following reset, the clock input must not be driven

rise must be monotonic.

CC

from LOW to HIGH until all applicable input and
feedback setup times are met.

See Switching

Characteristics

PR

t

S

V

CC

Clock

t

WL

Power-Up Reset Waveforms

16491D-16

2-182 PALCE20V8 Family