AMD HYPERTRANSPORT 8151 User Manual
24888 Rev 3.03 - July 12, 2004 AMD-8151
Cover page
TM
AGP Tunnel Data Sheet
AMD-8151TM HyperTransportTM AGP3.0 Graphics Tunnel
Data Sheet
1Overview
The AMD-8151
HyperTransport™ technology (referred to as link in this document) tunnel developed by AMD that provides an
AGP 3.0 compliant (8x transfer rate) bridge.
1.1 Device Features
• HyperTransport technology tunnel with side A
and side B.
• Side A is 16 bits (input and output); side B is
8 bits.
• Either side may connect to the host or to a
downstream HyperTransport technology
compliant device.
• Each side supports HyperTransport technol-
ogy-defined reduced bit widths: 8-bit, 4-bit,
and 2-bit.
• Side A supports transfer rates of 1600, 1200,
800, and 400 mega-transfers per second.
Side B supports transfer rates of 800 and
400 mega-transfers per second.
• Maximum bandwidth is 6.4 gigabytes per
second across side A (half upstream and half
downstream) and 1.6 gigabytes per second
across side B.
• Independent transfer rate and bit width
selection for each side.
• Link disconnect protocol supported.
TM
HyperTransportTM AGP3.0 Graphics Tunnel (referred to as the IC in this document) is a
• AGP 8x bridge.
• Compliance with AGP 3.0 specification signaling, supporting 4x and 8x transfer rates.
• Compliance with AGP 2.0 specification 1.5volt signaling, supporting 1x, 2x, and 4x
data-transfer modes.
• Supports up to 32 outstanding requests.
• 31 x 31 millimeter, 564-ball BGA package.
• 1.5 volt AGP signaling; some 3.3 volt IO; 1.2
volt link signaling; 1.8 volt core.
TM
Host
HyperTransport
Link
16 bits upstream,
16 bits downstream
Figure 1: System block diagram.
AMD-8151TM Device
Side A Side B
tunnel
AGP
Bridge
HyperTransport
Link
8 bits upstream,
8 bits downstream
AGP Graphics
Controller
Downstream
Device
1
24888 Rev 3.03 - July 12, 2004 AMD-8151
© 2004 Advanced Micro Devices, Inc.
All rights reserved.The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes
no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without
notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication.
Except as set forth in AMD's Standard Terms and Conditions of Sale,
AMD assumes no liability whatsoever, and disclaims any express or
implied warranty, relating to its products including, but not limited to, the
implied warranty of merchantability, fitness for a particular purpose, or
infringement of any intellectual property right. AMD's products are not
designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the
failure of AMD's product could create a situation where personal injury,
death, or severe property or environmental damage may occur. AMD
reserves the right to discontinue or make changes to its products at any
time without notice.
TM
AGP Tunnel Data Sheet
Trademarks
AMD, the AMD Arrow logo, and combinations thereof, and AMD-8151 are trademarks of Advanced Micro
Devices, Inc.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
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TM
AGP Tunnel Data Sheet
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Device Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Tunnel Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 AGP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Test and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5.1 Power Plane Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Reset And Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Tunnel Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.1 Link PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 AGP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5.1 Tags, UnitIDs, And Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5.2 Various Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.2.1 AGP Compensation And Calibration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2 Register Naming and Description Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 AGP Device Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 AGP Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7 Ball Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1 High Impedance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 NAND Tree Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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TM
AGP Tunnel Data Sheet
List of Figures
Figure 1: System block diagram................................................................................................................... 1
Figure 2: Configuration space. ................................................................................................................... 14
Figure 3: Ball designations......................................................................................................................... 39
Figure 4: Package mechanical drawing...................................................................................................... 42
Figure 5: NAND tree. ................................................................................................................................. 43
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AGP Tunnel Data Sheet
List of Tables
Table 1: IO signal types. ............................................................................................................................. 6
Table 2: Translation from AGP requests to link requests. ........................................................................ 13
Table 3: Configuration spaces................................................................................................................... 15
Table 4: Memory mapped address spaces................................................................................................. 15
Table 5: Register attributes. ...................................................................................................................... 15
Table 6: Absolute maximum ratings......................................................................................................... 34
Table 7: Operating ranges. ........................................................................................................................ 34
Table 8: Current and power consumption................................................................................................. 35
Table 9: DC characteristics for signals on the VDD33 power plane. ....................................................... 35
Table 10: DC characteristics for signals on the VDD15 power plane, AGP 2.0 signaling......................... 36
Table 11: DC characteristics for signals on the VDD15 power plane, AGP 3.0 signaling......................... 36
Table 12: AC data for clocks....................................................................................................................... 37
Table 13: AC data for common clock operation of AGP signals................................................................ 37
Table 14: AC data for clock-forwarded operation of AGP signals............................................................. 38
Table 15: Signal BGA positions.................................................................................................................. 40
Table 16: Power and ground BGA positions. ............................................................................................. 41
Table 17: Test modes................................................................................................................................... 43
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2 Ordering Information
AMD-8151
3 Signal Descriptions
3.1 Terminology
See section 5.1.2 for a description of the register naming convention used in this document. See the
AMD-8151
TM
HyperTransportTM AGP3.0 Graphics Tunnel Design Guide for additional information.
BL C
Case Temperature
C = Commercial temperature range
Package Type
BL = Organic Ball Grid Array with lid
Family/Core
AMD-8151
TM
AGP Tunnel Data Sheet
Signals with a # suffix are active low.
Signals described in this chapter utilize the following IO cell types:
Name Notes
Input Input signal only.
Output Output signal only. This includes outputs that are capable of being in the high-impedance state.
OD Open drain output. These signals are driven low and expected to be pulled high by external cir-
cuitry.
IO Input or output signal.
IOD Input or open-drain output.
Analog Analog signal.
w/PU With pullup. The signal includes a pullup resistor to the signal’s power plane. The resistor value is
nominally 8K ohms.
Table 1: IO signal types.
The following provides definitions and reference data about each of the IC’s pins. “During Reset” provides the
state of the pin while RESET# is asserted. “After Reset” provides the state of the pin immediately after
RESET# is deasserted. “Func.” means that the pin is functional and operating per its defined function.
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TM
AGP Tunnel Data Sheet
3.2 Tunnel Link Signals
TM
The following are signals associated with the HyperTransport
links. [B, A] in the signal names below refer
to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.
Pin name and description IO cell
type
LDTCOMP[3:0].
designed to be connected through resistors as follows:
Bit
[0] Positive receive compensation Resistor to VDD12B
[1] Negative receive compensationResistor to VSS
[3, 2] Transmit compensation Resistor from bit [2] to bit [3]
These resistors are used by the compensation circuit. The output of this circuit is
combined with DevA:0x[E8, E4, E0] to determine compensation values that are
passed to the link PHYs.
LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0]. Receive link command-address-
data bus.
LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N]. Receive link clock. Link
LR[B, A]CTL_[P, N]. Receive link control signal. Link
LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0]. Transmit link command-address-
data bus.
LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N]. Transmit link clock. Link
LT[B, A]CTL_[P, N]. Transmit link control signal. Link
Function External Connection
Link compensation pins for both sides of the tunnel. These are
Analog VDD-
Link
input
input
input
Link
output
output
output
Power
plane*
VDD12
VDD12
VDD12
VDD12 Diff
VDD12 Func. Func.
VDD12 Diff
12B
During
reset
High**
Low**
After
reset
Func.
Func.
* The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the
B side of the tunnel are powered by VDD12B.
** Diff High and Diff Low for these link pins specifies differential high and low; e.g., Diff High specifies that
the _P signal is high and the _N signal is low.
If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as follows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to
VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential outputs unconnected. If there are unused link signals on an active link (because the IC is connected to a device
with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.
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AGP Tunnel Data Sheet
3.3 AGP Signals
In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU”
indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor.
Pin name and description IO cell
type
A_ADSTB0_[P, N].
A_CBE_L[1:0]. When AGP 3.0 signaling is enabled,
A_ADSTB0_P is the first strobe and A_ADSTB0_N is the second
strobe.
A_ADSTB1_[P, N]. AGP differential strobe for AD[31:16],
A_CBE_L[3:2], and A_DBI[H,L]. When AGP 3.0 signaling is
enabled, A_ADSTB1_P is the first strobe and A_ADSTB1_N is
the second strobe.
A_AD[31:0]. AGP address-data bus. IO VDD15 Term Term PU Low
A_CBE_L[3:0]. AGP command-byte enable bus. IO VDD15 Term Term PU Low
A_CAL[D, S] and A_CAL[D, S]#. Compensation pins for
matching impedance of system board AGP traces. See
DevA:0x[54, 50] for more information. These are designed to be
connected through resistors as follows:
AGP differential strobe for A_AD[15:0] and
Analog VDD15
Power
plane
IO V DD15 Te rm Te rm _P : PU
IO V DD15 Te rm Te rm _P : PU
AGP 3.0
Signaling
During
reset
After
reset
AGP 2.0
Signaling
During
reset
_N: PD
_N: PD
After
reset
_P: PU
_N: PD
_P: PU
_N: PD
Signal
A_CALD Rising edge of data signals Resistor to VSS
A_CALD# Falling edge of data signals Resistor to VDD15
A_CALS Rising edge of strobe signals Resistor to VSS
A_CALS# Falling edge of strobe signals Resistor to VDD15
These resistors are used by the compensation circuit. The output of
this circuit is combined with DevA:0x[54, 50] to determine compensation values that are passed to the link PHYs.
A_DBI[H, L]. Data bus inversion [high, low]. When
DevA:0xA4[AGP3MD]=1, A_DBIL applies to AD[15:0];
A_DBIH applies to AD[31:16]. 1=AD signals are inverted.
0=A_AD signals are not inverted. The IC uses these signals in
determining the polarity of the A_AD signals when they are
inputs. These may also be enabled to support the DBI function of
the IC output signals by DevA:0x40[DBIEN]. Both A_DBIH and
A_DBIL are strobed with A_ADSTB1_[P, N].
When DevA:0xA4[AGP3MD]=0: A_DBIL is pulled low with the
AGP termination value and not used by the IC; A_DBIH is pulled
up to VDD15 through a weak resistor and becomes the AGP 2.0
PIPE# input signal.
A_DEVSEL#. AGP device select. IO VDD15 Term Term PU PU
A_FRAME#. AGP frame signal. IO VDD15 Term Term PU PU
A_GC8XDET#. 0=Specifies that the graphics device supports
AGP 3.0 signaling. The state of this signal is latched on the rising
edge of A_RESET# before being passed to internal logic.
Compensation Function External Connection
IO V DD15 Te rm Te rm PU PU
Input
w/PU
VDD15 PU PU PU PU
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24888 Rev 3.03 - July 12, 2004 AMD-8151
Pin name and description IO cell
type
A_GNT#. AGP master grant signal. Output VDD15 Term Low PU High
A_IRDY#. AGP master ready signal. IO VDD15 Term Term PU PU
A_MB8XDET#. This pin is controlled by DevA:0x40[8XDIS]. It
is designed to be connected to the AGP connector to indicate
support for AGP 3.0 signaling.
A_PAR. AGP parity signal. IO VDD15 Term Term PU Low
A_PCLK. 66 MHz AGP clock. Output VDD33 Func. Func. Func. Func.
A_PLLCLKO. PLL clock output. See section 4.3 for details. Output VDD33 Func. Func. Func. Func.
A_PLLCLKI. PLL clock input. See section 4.3 for details. Input VDD33
A_REFCG. AGP signal reference output. Analog
A_REFGC. AGP signal reference input. Analog
A_REQ#. AGP master request signal. Input VDD15 Term Term PU PU
A_RESET#. AGP bus reset signal. This is asserted whenever
RESET# is asserted or when programmed by
DevB:0x3C[SBRST]. Assertion of this pin does not reset any logic
internal to the IC.
A_RBF#. AGP read buffer full signal. Input VDD15 Term Term PU PU
A_SBSTB_[P, N]. AGP differential side band address strobe. In
AGP 3.0 signaling mode, A_SBSTB_P is the first strobe and
A_SBSTB_N is the second strobe.
A_SBA[7:0]. AGP side band address signals. Input VDD15 Term Term PU PU
A_ST[2:0]. AGP status signals. Output VDD15 Term Low PU Low
A_STOP#. AGP target abort signal. IO VDD15 Term Term PU PU
A_TRDY#. AGP target ready signal. IO VDD15 Term Term PU PU
A_TYPEDET#. AGP IO voltage level type detect. 0=1.5 volts;
1=3.3 volts (not supported by the IC). The state of this pin is
provided in DevA:0x40[TYPEDET]. This pin is also used for testmode selection; see section 9. This signal requires an external
pullup resistor to VDD33 on the systemboard.
A_WBF#. AGP write buffer full signal. Input VDD15 Term Term PU PU
Output VDD15 Low Low Low Low
output
input
Output VDD33 Low High Low High
Inp ut V DD15 Te rm Te rm _P : PU
Input VDD33
Power
plane
VDD15
VDD15
TM
AGP 3.0
Signaling
During
reset
AGP Tunnel Data Sheet
AGP 2.0
Signaling
After
reset
During
reset
_N: PD
After
reset
_P: PU
_N: PD
The SERR# and PERR# signals are not supported on the AGP bridge.
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AGP Tunnel Data Sheet
3.4 Test and Miscellaneous Signals
Pin name and description IO cell
type
CMPOVR.
is enabled. 1=The compensation values stored in DevA:0x[E0, E4, E8] control the
compensation circuit. The state of this signal determines the default value for
DevA:0x[E0, E4, E8][ACTL and BCTL] at the rising edge of PWROK.
FREE[7:1]. These should be left unconnected.
LDTSTOP#. Link disconnect control signal. This pin is also used for test-mode
selection; see section 9.
NC[1:0]. These should be left unconnected.
PWROK. Power OK. 1=All power planes are valid. The rising edge of this signal is
deglitched; it is not observed internally until it is high for more than 6 consecutive
REFCLK cycles. See section 4.2 for more details about this signal.
REFCLK. 66 MHz reference clock. This is required to be operational and valid for a
minimum of 200 microseconds prior to the rising edge of PWROK and always while
PWROK is high.
RESET#. Reset input. See section 4.2 for details. Input VDD33
STRAPL[19:13, 11:0]. Strapping option to be tied low. These pins should be tied to
ground. STRAPL0 is used for test-mode selection; see section 9.
STRAPL[22:20]. Strapping option to be tied low. These pins should be tied to
ground.
TEST. This is required to be tied low for functional operation. See section 9 for
details.
Link automatic compensation override. 0=Link automatic compensation
Input VDD33
Input VDD33
Input VDD33
Input VDD33
Input VDD33
Power
plane
IO VDD15 3-State 3-State
IO VDD33 3-State 3-State
During
reset
After
reset
3.5 Power and Ground
VDD12[B, A]. 1.2 volt power plane for the HyperTransport
TM
technology pins. VDD12A provides power to
the A side of the tunnel. VDD12B provides power to the B side of the tunnel.
VDD15. 1.5 volt power plane for AGP.
VDD18. 1.8-volt power plane for the core of the IC.
VDDA18. Analog 1.8-volt power plane for the PLLs in the core of the IC. This power plane is required to be
filtered from digital noise.
VDD33. 3.3-volt power plane for IO.
VSS. Ground.
3.5.1 Power Plane Sequencing
The following are power plane requirements that may imply power supply sequencing requirements.
• VDD33 is required to always be higher than VDD18, VDDA18, VDD15, and VDD12[B, A].
• VDD18 and VDDA18 are required to always be higher than VDD15 and VDD12[B, A].
• VDD15 is required to always be higher than VDD12[B, A].
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AGP Tunnel Data Sheet
4 Functional Operation
4.1 Overview
TM
The IC connects to the host through either the side A or side B HyperTransport
link interface. The other side
of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the
IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are
passed to internal registers or to the AGP bridge.
See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register
naming convention. See the AMD-8151
TM
HyperTransportTM AGP3.0 Graphics Tunnel Design Guide for addi-
tional information.
4.2 Reset And Initialization
RESET# and PWROK are both required to be low while the power planes to the IC are invalid and for at least
1 millisecond after the power planes are valid. Deassertion of PWROK is referred to as a cold reset. After
PWROK is brought high, RESET# is required to stay low for at least 1 additional millisecond. After RESET#
is brought high, the links go through the initialization sequence.
After a cold reset, the IC may be reset by asserting RESET# while PWROK remains high. This is referred to as
a warm reset. RESET# must be asserted for no less than 1 millisecond during a warm reset.
4.3 Clocking
It is required that REFCLK be valid in order for the IC to operate. Also, the LR[B, A]CLK inputs from the
operation links must also be valid at the frequency defined DevA:0xCC[FREQA] and DevA:0xD0[FREQB].
The IC provides A_PCLK as the clock to the AGP device.
The systemboard is required to include a connection from A_PLLCLKO to A_PLLCLKI. The length of this
connection is required to be approximately the same as length of the A_PCLK trace from the IC to the external
AGP devices (including approximately 2.5 inches of etch on the AGP card). The IC uses this loopback to help
match the external trace delay.
4.3.1 Clock Gating
Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required
that all upstream requests initiated by the IC be suspended while in this state.
To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating will be
enabled. Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the
IC is enabled for clock gating during LDTSTOP# assertions. The system is placed into power managed states
by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management
Action Field (SMAF) followed by the assertion of LDTSTOP#. When the IC detects the Stop Grant broadcast
which is enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP#. While exiting
the power-managed state, the system is required to broadcast a STPCLK deassertion message. The IC uses this
message to disable clock gating during LDTSTOP# assertions. This is important because an LDTSTOP# assertion is not guaranteed to occur after the Stop Grant broadcast is received. The clock gating window must be
closed to insure that clock gating does not occur during Stop Grant for LDTSTOP# assertions that are not associated with the power states specified by DevA:0xF0[ICGSMAF].
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AGP Tunnel Data Sheet
In summary, Stop Grant broadcasts with SMAF fields specified by DevA:0xF0[ICGSMAF] enable the clock
gating window and STPCLK deassertion broadcasts disable the window. If LDTSTOP# is asserted while the
clock gating window is enabled, then clock gating occurs.
Also, DevA:0xF0[ECGSMAF] may be used in a similar way to disable A_PCLK and the internal clock grids
associated with the AGP bridge. The same rules for the clock gating window that apply to DevA:0xF0[ICGSMAF] also apply to DevA:0xF0[ECGSMAF]. If clock gating is enabled, then A_PCLK is forced low within
two clock periods after LDTSTOP# is asserted. It becomes active again within two clock periods after LDTSTOP# is deasserted. It is required that there be no AGP-card-initiated upstream or downstream traffic while
A_PCLK is gated. In addition, it is required that there be no host accesses to the bridge or internal registers in
progress from the time that LDTSTOP# is asserted for clock gating until the link reconnects after LDTSTOP#
is deasserted.
4.4 Tunnel Links
HyperTransport link A supports CLK receive and transmit frequencies of 200, 400, 600, and 800 MHz. Link B
supports frequencies of 200 and 400 MHz. The side A and side B frequencies are independent of each other.
4.4.1 Link PHY
The PHY includes automatic compensation circuitry and a software override mechanism, as specified by
DevA:0x[E8, E4, E0]. The IC only implements synchronous mode clock forwarding FIFOs. So only the link
receive and transmit frequencies specified in DevA:0x[D0, CC][FREQB, FREQA] are allowed.
4.5 AGP
The AGP bridge supports AGP 3.0 signaling at 8x and 4x data rates and 1.5-volt AGP 2.0 signaling at 4x, 2x,
and 1x data rates. 64-bit upstream and 32-bit downstream addressing is supported. AGP 3.0 dynamic bus inversion is supported on output signals in 8X mode only, not in 4X mode; dynamic bus inversion on input signals is
supported in both 4X and 8X modes.
4.5.1 Tags, UnitIDs, And Ordering
The IC requires three HyperTransport
TM
technology-defined UnitIDs. They are allocated as follows:
• First UnitID is not used. This is to avoid a potential conflict with the host (because it may be zero; see
DevA:0xC0[BUID]).
• Second UnitID is used for PCI-mode upstream requests and responses to host requests.
• Third UnitID is used for AGP (high priority and low priority) upstream requests.
The SrcTag value that is assigned to upstream non-posted AGP requests increments with each request from 0
to 27 and then rolls over to 0 again; the first SrcTag assigned after reset is 0. Up to 28 non-posted link requests
may be outstanding at a time. The SrcTag value that is assigned to non-posted PCI requests is always 28.
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All AGP transactions are compliant to AGP ordering rules. APG transactions are translated into link transactions as follows:
AGP transaction Link transaction
High priority write WrSized, posted channel, PassPW = 1
High priority read RdSized, PassPW = 1, response PassPW = 1
Low priority write WrSized, posted channel, PassPW = 0
Low priority read RdSized, PassPW = 0, response PassPW = 1
Low priority flush Flush, PassPW = 0
Low priority fence None (wait for all outstanding read responses)
TM
AGP Tunnel Data Sheet
Table 2: Translation from AGP requests to link requests.
4.5.2 Various Behaviors
• The AGP bridge does not claim link special cycles. However, special cycles that are encoded in configura-
tion cycles to device 31 of the AGP secondary bus number (per the PCI-to-PCI bridge specification) are
translated to AGP bus special cycles.
• AGP and PCI read transactions that receive NXA responses from the host complete onto the AGP bus with
the data provided by the host (which is required to be all 1’s, per the link specification).
• In the translation from type 1 link configuration cycles to secondary bus type 0 configuration cycles, the IC
converts the device number to IDSEL AD signal as follows: device 0 maps to AD[16]; device 1 maps to
AD[17]; and so forth. Device numbers 16 through 31 are not valid.
• The compensation values for drive strength and input impedance that are assigned to non-clock forwarded
AGP signals are automatically determined and set by the IC during the first compensation cycle after
RESET#. Once set, they do not change until the next RESET# assertion.
• Per the link protocol, when the COMPAT bit is set in the transaction, the IC does not ever claim the transac-
tion. Such transactions are automatically passed to the other side of the tunnel (or master aborted if the IC is
at the end of the chain). This is true of all transactions within address space that is otherwise claimed by the
IC, including the space defined by DevB:0x3C[VGAEN].
4.5.2.1 AGP Compensation And Calibration Cycles
The AGP PHY includes one compensation circuit for the clock forwarded data signals, A_AD[31:0],
A_CBE_L[3:0], and A_DBI[H, L], and one compensation circuit for the strobes, A_ADSTB[1:0]. Each compensation circuit calculates the required rising-edge (P) and falling-edge (N) signal drive strength through a
free-running state machine that generates a new value approximately every four microseconds. These values
are provided in DevA:0x[50, 54][NCOMP, PCOMP].
Programmable skew values between data signals and strobes are also provided in DevA:0x58.
The compensation values provided to the AGP PHY are software selectable between the calculated compensation values, fixed programmable bypass values, or fixed programmable offsets from the calculated values.
Regardless of which value is selected, the value presented to the PHY is never updated until there is a calibration cycle.
Calibration cycles consist of taking control of the AGP bus, updating the AGP PHY compensation values, and
then releasing (see DevA:0xA8[PCALCYC]). If enabled by DevA:0xB0[CALDIS], they occur periodically
with the period specified by DevA:0xA8[PCALCYC].
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AGP Tunnel Data Sheet
The first calibration cycle occurs approximately 4 milliseconds after the deassertion of RESET# (whether AGP
2.0 or 3.0 signaling is enabled).
5 Registers
5.1 Register Overview
The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers
to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration
space is typically accessed by the host through IO cycles to CF8h and CFCh. There is also memory space and
indexed address space in the IC.
5.1.1 Configuration Space
The address space for the IC configuration registers is broken up into busses, devices, functions, and, offsets, as
defined by the link specification. It is accessed by HyperTransport™ technology-defined type 0 configuration
cycles. The device number is mapped into bits[15:11] of the configuration address. The function number is
mapped into bits[10:8] of the configuration address. The offset is mapped to bits[7:2] of the configuration
address.
The following diagram shows the devices in configuration space as viewed by software.
Primary bus
AGP Device
DevA:0xXX
Device header
First device
Function 0
AGP Bridge
DevB:0xXX
Bridge header
Second device
Function 0
Secondary bus
AGP Slot
Figure 2: Configuration space.
Device A, above, is programmed to be the link base UnitID and device B is the link base UnitID plus 1.
5.1.2 Register Naming and Description Conventions
Configuration register locations are referenced with mnemonics that take the form of Dev[A|B]:[7:0]x[FF:0],
where the first set of brackets contain the device number, the second set of brackets contain the function number, and the last set of brackets contain the offset.
Other register locations (e.g. memory mapped registers) are referenced with an assigned mnemonic that specifies the address space and offset. These mnemonics start with two or three characters that identify the space
followed by characters that identify the offset within the space.
Register fields within register locations are also identified with a name or bit group in brackets following the
register location mnemonic.
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