AMD HYPERTRANSPORT 8151 User Manual

AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision
Guide
25912Publication # 3.06Revision:
March 2006Issue Date:
© 2003–2006 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The informa­tion contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and dis­claims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as compo­nents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks
AMD, the AMD Arrow logo, and combinations thereof, and AMD-8151 are trademarks of Advanced Micro Devices, Inc.
PCI-X and PCI Express are registered trademarks of PCI-SIG.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
25912 Rev. 3.06 March 2006
AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel

Revision History

Date Revision Description
March 2006 3.06 Added erratum #28.
August 2004 3.04 Added erratum #27.
June 2003 3.00 Initial public release.
Revision Guide
Revision History 3
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4 Revision History
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AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel
Revision Guide
AMD-8151™
HyperTransport™ AGP3.0
Graphics Tunnel
Revision Guide
The purpose of the AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision Guide is to
communicate updated product information on the AMD-8151™ HyperTransport™ AGP3.0 graphics tunnel to designers of computer systems and software developers. This guide consists of three major sections:
Revision Determination: This section, which starts on page 6, describes the mechanism by
which the current revision of the part is identified.
Product Errata: This section, which starts on page 7, provides a detailed description of product
errata, including potential effects on system operation and suggested workarounds. An erratum is defined as a deviation from product specifications, and as such may cause the behavior of the AMD-8151 HyperTransport AGP3.0 graphics tunnel to deviate from the published specifications.
Documentation Support: This section, which starts on page 15, provides a listing of available
technical support resources.

Revision Guide Policy

Occasionally, AMD identifies product errata that cause the AMD-8151 HyperTransport AGP3.0 graphics tunnel to deviate from published specifications. Descriptions of identified product errata are designed to assist system and software designers in using the AMD-8151 HyperTransport AGP3.0 graphics tunnel. Furthermore, this revision guide may be updated periodically.
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Revision Determination

The BIOS checks the PCI revision ID register at DevA:0x08 to determine the version of silicon as shown in Table 1.

Table 1. AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Revision IDs

Sequence Revision
5B2 13h
DevA:0x08 DevB:0x08
6 Revision Determination
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Product Errata

This section documents AMD-8151™ HyperTransport™ AGP3.0 graphics tunnel product errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 2 cross-references the revisions of the part to each erratum. An “X” indicates that the erratum applies to the revision. The absence of an “X” indicates that the erratum does not apply to the revision.
Note: There may be missing errata numbers. Errata that have been resolved from early revisions of
the device have been deleted, and errata that have been reconsidered may have been deleted or renumbered.

Table 2. Cross-Reference of Product Revision to Errata

Revision Number
Errata Numbers and Description
B2
22 Incorrect Value For DevA:0xA4[Host translation#] X
23 Link Electrical Issue When Operating At 800 MHz X
24 Deadlock Scenario With Peer-To-Peer Traffic X
25 Input Leakage Parameter Out Of Spec X
26 DevB:0x00[DevID] Is Read Only X
27 Failure When B-Side Link Is Directed Toward The Host X
28 The AMD-8151™ Tunnel Lacks Extended Configuration Space Memory-Mapped I/
O Base Address Register
X
Product Errata 7
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22 Incorrect Value For DevA:0xA4[Host translation#]

Description
DevA:0xA4[Host translation#] is a read-only bit, fixed in the high state in the graphics tunnel. Per the AGP specification, this indicates that core logic does not translate host transactions addressed to the Graphics Aperature through the GART. However, on AMD platforms that use the graphics tunnel, such host transactions can be translated through the GART.
Potential Effect on System
None.
Suggested Workaround
Software should presume that this bit is low for the graphics tunnel.
Fix Planned
Ye s
8 Product Errata
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23 Link Electrical Issue When Operating At 800 MHz

Description
The graphics tunnel A-side link may not operate properly at 800 MHz.
Potential Effect on System
Transfer of erroneous data and system deadlocks are possible.
Suggested Workaround
The A-side link should be configured to operate at 600 MHz instead of 800 MHz.
Alternatively, more restrictive system board layout rules for the A-side link may be employed. See the
AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Motherboard Design Guide,
order# 25617 for details.
Fix Planned
No
Product Errata 9
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24 Deadlock Scenario With Peer-To-Peer Traffic

Description
Some PCI cards generate peer-to-peer posted-write traffic targeting the AGP bridge (from the PCI bus, through the graphics tunnel, to the host, back to the graphics tunnel to the AGP bus). The combination of such cards and some AGP cards can generate traffic patterns that result in a system deadlock.
Potential Effect on System
The system deadlocks.
Suggested Workaround
Do not support PCI cards that generate peer-to-peer traffic to the AGP bridge.
Fix Planned
Ye s
10 Product Errata
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25 Input Leakage Parameter Out Of Spec

Description
When operating with AGP2.0 signaling, the input leakage current (ILI) is specified to be limited to less than ±10 µA. However, input leakage current may be as much as ±20 µA in some graphics tunnel parts.
Potential Effect on System
None.
Suggested Workaround
None required.
Fix Planned
No
Product Errata 11
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26 DevB:0x00[DevID] Is Read Only

Description
The four LSBs of DevB:0x00[DevID] should be "write once". However, they are "read only" instead.
Potential Effect on System
A generic graphics driver may be loaded even if the platform does not support the generic driver.
Suggested Workaround
None required.
Fix Planned
Ye s
12 Product Errata
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27 Failure When B-Side Link Is Directed Toward The Host

Description
The AMD-8151 does not master abort a transaction with the HyperTransport COMPAT bit set if all of the following conditions apply:
HyperTransport link B is connected toward the host
HyperTransport link A is the end of chain
Potential Effect on System
The processor will hang.
Suggested Workaround
Connect the AMD-8151 HyperTransport interface A toward the processor.
Fix Planned
No
Product Errata 13
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28 The AMD-8151™ Tunnel Lacks Extended Configuration Space
Memory-Mapped I/O Base Address Register
Description
Current AMD processors do not natively support PCI-defined extended configuration space. A memory-mapped I/O base address register (MMIO BAR) is required in chipset devices to support extended configuration space. The AMD-8151 does not have this MMIO BAR.
Potential Effect on System
The AMD-8151 is not a PCI-X® Mode 2 or PCI Express® capable device and is not required to support the MMIO BAR. However, using a device with an MMIO BAR and an AMD-8151 on the same HyperTransport™ link of the processor may cause firmware/software problems.
Suggested Workaround
It is strongly recommended that system designers do not connect the AMD-8151 and devices that use extended configuration space MMIO BARs (ex: HyperTransport-to-PCI Express bridges) to the same processor HyperTransport link.
Fix Planned
No
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Documentation Support

The following documents provide additional information regarding the operation of the AMD-8151™ HyperTransport™ AGP3.0 graphics tunnel:
AMD-8151™ HyperTransport™ AGP3.0 Graphics Tunnel Data Sheet, order# 24888
HyperTransport™ I/O Link Specification (www.hypertransport.org) See the AMD Web site at www.amd.com for the latest updates to documents. For documents subject
to a non-disclosure agreement, please contact your local sales representative.
Documentation Support 15
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16 Documentation Support
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