Altera Reed-Solomon Compiler User Manual
Reed-Solomon Compiler User Guide
Reed-Solomon Compiler
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
c The Reed-Solomon IP Core is scheduled for product obsolescence and discontinued
support as described in PDN1410. Therefore, Altera does not recommend use of this IP
in new designs. For more information about Altera’s current IP offering, refer to Altera’s
Intellectual Property website.
UG-RSCOMPILER-14.1
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December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
Contents
Chapter 1. About This Compiler
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Chapter 2. Getting Started
Installing and Licensing IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
OpenCore Plus IP Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Specifying IP Core Parameters and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Parameterizing the Reed Solomon MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Generated Files (For Arria V, Cyclone V, MAX 10, and Stratix V Devices) . . . . . . . . . . . . . . . . . . . . . . . 2–4
Files Generated for Altera IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulating IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Adding IP Cores to IP Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Upgrading Outdated IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Upgrading IP Cores at the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
DSP Builder Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Chapter 3. Functional Description
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Shortened Codewords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Variable Encoding and Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
RS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
RS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Error Symbol Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Bit Error Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Throughput Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Appendix A. Using the RS Encoder or Decoder in a CCSDS System
Supplying Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
iv Contents
<edit Document Title variable in cover> <month> <year> Altera Corporation
<edit Document Type variable in cover>
1. About This Compiler
This document describes the Altera® Reed-Solomon (RS) Compiler. The Altera RS
Compiler comprises a fully parameterizable encoder and decoder for forward error
correction applications. RS codes are widely used for error detection and correction in
a wide range of DSP applications for storage, retrieval, and transmission of data. The
RS Compiler has the following options:
■ Erasures-supporting option—the RS decoder can correct symbol errors up to the
number of check symbols, if you give the location of the errors to the decoder.
Refer to “Erasures” on page 3–2.
■ Variable encoding or decoding—you can vary the total number of symbols per
codeword and the number of check symbols, in real time, from their minimum
allowable values up to their selected values, when you are encoding or decoding.
■ Error symbol output—the RS decoder finds the error values and location and adds
these values in the Galois field to the input value.
■ Bit error output—either split count or full count
Features
The Altera Reed-Solomon Compiler supports the following features:
■ High-performance encoder/decoder for error detection and correction
■ Fully parameterized RS function, including:
■ Number of bits per symbol
■ Number of symbols per codeword
■ Number of check symbols per codeword
■ Field polynomial
■ First root of generator polynomial
■ Space between roots in generator polynomial
■ Decoder features:
■ Variable option
■ Erasures-supporting option
■ Encoder features variable architectures
■ Support for shortened codewords
■ Conforms to Consultative Committee for Space Data Systems (CCSDS)
Recommendations for Telemetry Channel Coding, May 1999
■ DSP Builder ready
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
1–2 Chapter 1: About This Compiler
Release Information
■ Support for OpenCore Plus evaluation
Release Information
Tab le 1– 1 provides information about this release of the Reed-Solomon (RS) Compiler.
Table 1–1. RS Compiler Release Information
Item Description
Version 14.1
Release Date December 2014
Ordering Codes
Product IDs
Vendor ID 6AF7
f For more information about this release, refer to the MegaCore IP Library Release Notes.
IP-RSENC (Encoder)
IP-RSDEC (Decoder)
0039 0041 (Encoder)
0080 0041 (Decoder)
Altera verifies that the current version of the Quartus
previous version of each MegaCore
report any exceptions to this verification. Altera does not verify compilation with
MegaCore function versions older than one release.
Device Family Support
Altera offers the following device support levels for Altera IP cores:
■ Preliminary support—Altera verifies the IP core with preliminary timing models
for this device family. The IP core meets all functional requirements, but might still
be undergoing timing analysis for the device family. You can use it in production
designs with caution.
■ Final support—Altera verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family and can be used in production designs.
Tab le 1– 2 shows the level of support offered by the RS Compiler to each of the Altera
device families.
Table 1–2. Device Family Support (Part 1 of 2)
®
II GX Final
Arria
Arria II GZ Final
Arria V final
®
Cyclone
Stratix
Stratix IV GX/E Final
Stratix V Final
IV GX Final
®
IV GT Final
®
®
function. The MegaCore IP Library Release Notes
II software compiles the
Device Family Support
Reed-Solomon Compiler December 2014 Altera Corporation
User Guide
Chapter 1: About This Compiler 1–3
Performance and Resource Utilization
Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support
Stratix GX Final
Other device families No support
Performance and Resource Utilization
Tab le 1– 3 shows the typical performance using the Quartus II software for Stratix IV
(EP4SGX70DF29C2X) devices.
Table 1–3. Performance—Stratix IV Devices
Parameters
Options Keysize
Bits
(1)
Symbols
(2)
Check
(3)
ALUTs
Logic
Registers
Memory
ALUTs M9K
f
MAX
(MHz)
Throughput
(Mbps)
Standard decoder Half 4 15 6 426 382 8 3 413 387
Standard decoder Half 8 204 16 1,220 1,034 64 3 368 2,945
Split bit error decoder Half 8 204 16 1,273 1,092 64 3 340 2,719
Full bit error decoder Half 8 204 16 1,255 1,092 64 3 325 2,603
Standard decoder Half 8 255 32 2,100 1,713 64 3 324 2,038
Variable decoder Half 8 204 16 1,362 1,119 64 3 356 2,850
Erasures decoder Half 8 204 16 2,170 1,596 64 3 314 2,510
Erasures and variable
decoder
Half 8 204 16 2,322 1,746 96 3 310 2,480
Standard encoder — 8 204 16 204 210 — — 620 4,960
Variable encoder — 8 204 16 777 313 — — 387 3,099
Variable encoder — 8 204 32 1,651 582 — — 347 2,775
Notes to Table 1–3:
(1) The number of bits per symbol (m).
(2) The number of symbols per codeword (N).
(3) The number of check symbols per codeword (R).
The throughput in megabits per second (Mbps) is derived from the formulas in
Table 3–9 on page 3–11 and maximum frequency at which the design can operate.
December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
1–4 Chapter 1: About This Compiler
Performance and Resource Utilization
Reed-Solomon Compiler December 2014 Altera Corporation
User Guide
Installing and Licensing IP Cores
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
The Quartus II software includes the Altera IP Library. The library provides many
useful IP core functions for production use without additional license. You can fully
evaluate any licensed Altera IP core in simulation and in hardware until you are
satisfied with its functionality and performance.
Some Altera IP cores, such as MegaCore
separate license for production use. After you purchase a license, visit the Self Service
Licensing Center to obtain a license number for any Altera product. For additional
information, refer to Altera Software Installation and Licensing.
Figure 2–1. IP core Installation Path
2. Getting Started
®
functions, require that you purchase a
1 The default installation directory on Windows is <drive>:\altera\<version number>;
on Linux it is <home directory>/altera/<version number>.
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP
cores in simulation and hardware before purchase. You need only purchase a license
for MegaCore IP cores if you decide to take your design to production. OpenCore Plus
supports the following evaluations:
■ Simulate the behavior of a licensed IP core in your system.
■ Verify the functionality, size, and speed of the IP core quickly and easily.
■ Generate time-limited device programming files for designs that include IP cores.
■ Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
■ Untethered—run the design containing the licensed IP for a limited time.
■ Tethered—run the design containing the licensed IP for a longer time or
indefinitely. This requires a connection between your board and the host
computer.
All IP cores using OpenCore Plus in a design time out simultaneously when any IP
core times out.
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User Guide
2–2 Chapter 2: Getting Started
Specifying IP Core Parameters and Options
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time-out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior might be masked by the time-out behavior
of the other megafunctions.
The untethered time-out for a RS Compiler MegaCore function is one hour; the
tethered time-out value is indefinite.
Your design stops working after the hardware evaluation time expires and the data
output
rsout
remains low.
Specifying IP Core Parameters and Options
The parameter editor GUI allows you to quickly configure your custom IP variation.
Use the following steps to specify IP core options and parameters in the Quartus II
software. Refer to Specifying IP Core Parameters and Options (Legacy Parameter
Editors) for configuration of IP cores using the legacy parameter editor.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP
core to customize. The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves
the IP variation settings in a file named .<your_ip>qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor,
including one or more of the following. Refer to your IP core user guide for
information about specific IP core parameters.
■ Optionally select preset parameter values if provided for your IP core. Presets
specify initial parameter values for specific applications.
■ Specify parameters defining the IP core functionality, port configurations, and
device-specific features.
■ Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation
files generate according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
7. To generate an HDL instantiation template that you can copy and paste into your
text editor, click Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level .qsys file to the current
project automatically. If you are prompted to manually add the .qsys file to the
project, click Project > Add/Remove Files in Project to add the file.
Reed-Solomon Compiler December 2014 Altera Corporation
User Guide
Chapter 2: Getting Started 2–3
Parameterizing the Reed Solomon MegaCore Function
9. After generating and instantiating your IP variation, make appropriate pin
assignments to connect ports.
f For information about using a legacy parameter editor, refer to “Specifying IP Core
Parameters and Options (Legacy Parameter Editors)” in the Introduction to Altera IP
Cores.
Parameterizing the Reed Solomon MegaCore Function
To parameterize your MegaCore function, follow these steps:
1. Select Encoder or Decoder.
2. If you select Encoder, you can also turn on the Va r ia b l e option.
For more information about the variable option, refer to “Variable Encoding and
Decoding” on page 3–3.
3. If Decoder is selected, the following controls are available:
a. You can turn on the Erasures-supporting decoder or Va r ia b l e options.
b. You can select Full or Half keysize.
c. You can turn on the Error Symbol or Bit Error outputs. For the bit error output,
you can select Split Count or Full Count.
For more information about these parameters, refer to Table 3–2 on page 3–7.
4. Click Next.
5. Select the parameters that define the specific RS codeword that you wish to
implement (Figure 2–5).
1 You can enter the parameters individually, or click DVB Standard to use
digital video broadcast (DVB) standard values, or CCSDS Standard to use
the CCSDS standard values.
For more information about these parameters, refer to Table 3–3 on page 3–8.
6. Click Next.
7. For a decoder throughput calculation, enter the frequency in MHz, select the
desired units, and click Calculate. Figure 2–6 shows the decoder throughput
calculation page.
For more information about the throughput calculator, refer to “Throughput
Calculator” on page 3–10.
8. Click Finish.
For more information about the RS Compiler parameters, refer to “Parameters” on
page 3–7.
December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
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