Altera RapidIO MegaCore Function User Manual
RapidIO MegaCore Function v14.0 and v14.0 Arria 10
Edition User Guide
RapidIO MegaCore Function
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
UG-MC_RIOPHY-4.1
Document last updated for Altera Complete Design Suite version:
Document publication date:
14.0 and 14.0 Arria 10 Edition
August 2014
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Registered
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
Contents
Chapter 1. About This MegaCore Function
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
New Features in the RapidIO IP Core v14.0 and v14.0 Arria 10 Edition Releases . . . . . . . . . . . . . . . 1–2
RapidIO IP Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Supported Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
IP Core Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Simulation Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Hardware Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Interoperability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
Chapter 2. Getting Started
Customizing and Generating IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Files Generated for Altera IP Cores (Legacy Parameter Editor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Files Generated for Altera IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Simulating IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Simulating the Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Simulating the Testbench with the VCS Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Integrating Your IP Core in Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Calibration Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Dynamic Transceiver Reconfiguration Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Transceiver Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations . . 2–6
External Transceiver PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Compiling the Full Design and Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Instantiating Multiple RapidIO IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations . . . . . . . . . . . . . 2–10
Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX
Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances . . . . 2–12
Sourcing Multiple Tcl Scripts for non-Arria 10 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Chapter 3. Parameter Settings
Physical Layer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Transceiver Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Enable Transceiver Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Synchronizing Transmitted ackID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Sending Link-Request Reset-Device on Fatal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Number of Link-Request Attempts Before Declaring Fatal Error . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Data Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
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Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Reference Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Receive Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Transmit Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Receive Priority Retry Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Transport and Maintenance Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Enable 16-Bit Device ID Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Enable Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Destination ID Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Input/Output Maintenance Logical Layer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Maintenance Logical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Transmit Address Translation Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Port Write Tx Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Port Write Rx Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
I/O and Doorbell Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
I/O Logical Layer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
I/O Slave Address Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
I/O Read and Write Order Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Doorbell Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Capability Registers Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Assembly Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Assembly ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Assembly Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Assembly Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Extended Features Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Processing Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Bridge Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Processor Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Switch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Enable Switch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Number of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Port Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Data Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Source Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Destination Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Chapter 4. Functional Description
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
RapidIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon-MM Interface Widths in the RapidIO IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon-MM Interface Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon Streaming (Avalon-ST) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Clocking and Reset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
RapidIO IP Core Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
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Avalon System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Other Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Baud Rates and Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Reset for RapidIO IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
General RapidIO Reset Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Reset Requirements for Arria V, Cyclone V, and Stratix V Variations . . . . . . . . . . . . . . . . . . . . . . 4–8
Reset Requirements for Arria 10 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
RapidIO IP Core Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Physical Layer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11
Low-level Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
Receiver Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
CRC Checking and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12
Low-Level Interface Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Transmitter Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Protocol and Flow Control Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13
Physical Layer Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14
Error Conditions that Flush the Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
Error Conditions Flagged for the Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15
Receive Priority Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16
Physical Layer Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17
Transmit and Retransmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
Error Conditions that Flush the Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18
Forced Compensation Sequence Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20
Transaction ID Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Logical Layer Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22
Concentrator Register Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23
Maintenance Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26
Maintenance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
Maintenance Slave Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28
Maintenance Master Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30
Port-Write Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32
Maintenance Module Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Input/Output Logical Layer Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33
Input/Output Avalon-MM Master Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34
RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions . . . . . . . . . . 4–36
Input/Output Avalon-MM Master Module Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40
Input/Output Avalon-MM Slave Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41
Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets . . . . . . . . . . . . . . . . . . . . 4–48
Input/Output Avalon-MM Slave Module Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52
Doorbell Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53
Doorbell Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 4–53
Preserving Transaction Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54
Doorbell Message Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55
Doorbell Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56
Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56
Pass-Through Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57
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Error Detection and Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61
Physical Layer Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61
Protocol Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62
Fatal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62
Logical Layer Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62
Maintenance Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63
Maintenance Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64
Port-Write Reception Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65
Port-Write Transmission Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65
Input/Output Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65
Input/Output Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66
Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67
Chapter 5. Signals
Physical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Status Packet and Error Monitoring Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Multicast Event Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Receive Priority Retry Threshold-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Physical Layer Buffer Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Register-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Transport and Logical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Avalon-MM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Avalon-ST Pass-Through Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Error Management Extension Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Packet and Error Monitoring Signal for the Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Chapter 6. Software Interface
Physical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Transport and Logical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Capability Registers (CARs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Command and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Maintenance Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Receive Maintenance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Transmit Maintenance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Transmit Port-Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Receive Port-Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
Input/Output Master Address Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20
Input/Output Slave Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21
Input/Output Slave Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
Transport Layer Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
Error Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
Doorbell Message Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26
Chapter 7. Testbenches
Reset, Initialization, and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
Maintenance Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
SWRITE Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
NWRITE_R Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
NWRITE Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
NREAD Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
Doorbell Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
Doorbell and Write Transactions With Transaction Order Preservation . . . . . . . . . . . . . . . . . . . . . . . 7–9
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Port-Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
Transactions Across the Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11
Chapter 8. Qsys Design Example
Creating a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Running Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
Adding and Parameterizing the RapidIO Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
Adding and Connecting Other System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Adding the Master Maintenance BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Adding the Master I/O BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Adding the On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
Connecting Clocks and the System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
Connecting Unconnected Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
Connecting System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9
Assigning Addresses and Setting the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Generating the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11
Simulating the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12
Appendix A. Initialization Sequence
Appendix C. Porting a RapidIO Design from the Previous Version of the Software
Upgrading a RapidIO Design Without Changing Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
Upgrading a RapidIO Design to the Arria 10 Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–5
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–5
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RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
1. About This MegaCore Function
DSP
ASSP
DSP
ASSP
CPU
MemoryMemoryMemory
Memory
DSP
Interface
Bridge
FPGA
Controller
RapidIO
MegaCore
Function
DSP
ASSP
Serial
Switch
RapidIO
System Interconnect
Proprietary,
CPRI, OBSAI,
Ethernet, etc.
The RapidIO® interconnect—an open standard developed by the RapidIO Trade
Association—is a high-performance packet-switched interconnect technology
designed to pass data and control information between microprocessors, digital signal
processors (DSPs), communications and network processors, system memories, and
peripheral devices.
The Altera
high-bandwidth, and coprocessing I/O applications. Figure 1–1 shows an example
system implementation.
Figure 1–1. Typical RapidIO Application
®
RapidIO MegaCore® function targets high-performance, multicomputing,
Features
This section outlines the features and supported transactions of the RapidIO IP core.
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
1–2 Chapter 1: About This MegaCore Function
Features
New Features in the RapidIO IP Core v14.0 and v14.0 Arria 10 Edition Releases
The RapidIO IP core v14.0 Arria 10 Edition adds the following new feature:
■ Support for Arria 10 devices
The RapidIO IP core v14.0 adds the following new features:
■ All RapidIO IP core variations have a Transport layer.
■ All RapidIO IP core variations include configuration of the high-speed
transceivers on the device.
For details about changes to the IP core, refer to “Document Revision History” on
page Info–1. For an overview, refer to the RapidIO IP core chapter in the Altera
MegaCore IP Library Release Notes. IP core variations that target an Arria 10 device have
additional interfaces and design requirements.
f For information about the new Altera IP design flow in the Quartus II software v14.0
and v14.0 Arria 10 Edition, which impacts all Altera IP cores, refer to the
“Introduction to Altera IP Cores” section in the “Managing Quartus II Projects”
chapter in Volume 1: Design and Synthesis of the Quartus II Handbook and to Introduction
to Altera IP Cores.
The RapidIO IP core v13.1 does not add any new features.
RapidIO IP Core Features
The RapidIO IP core has the following features:
■ Compliant with RapidIO Trade Association, RapidIO Interconnect Specification,
Revision 2.1, August 2009, available from the RapidIO Trade Association website
at www.rapidio.org
■ Successfully passed RIOLAB’s Device Interoperability Level-3 (DIL-3) testing
■ Supports 8-bit or 16-bit device IDs
■ Supports incoming and outgoing multi-cast events
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Chapter 1: About This MegaCore Function 1–3
Features
■ Physical layer features
■ 1x/2x/4x serial with integrated transceivers in selected device families and
support for external transceivers in older device families
■ All four standard serial data rates supported: 1.25, 2.5, 3.125, and 5.0 gigabaud
(Gbaud)
■ Receive/transmit packet buffering, flow control, error detection, packet
assembly, and packet delineation
■ Automatic freeing of resources used by acknowledged packets
■ Automatic retransmission of retried packets
■ Scheduling of transmission, based on priority
■ Reset controller—fatal error does not require manual resetting
■ Optional automatic resetting of link partner after detection of fatal errors
■ Support for synchronizing with link partner’s expected ackID after reset
■ Full control over integrated transceiver parameters
■ Configurable number of recovery attempts after link response time-out before
declaring fatal error
■ Transport layer features
■ Supports multiple Logical layer modules
■ A round-robin outgoing scheduler chooses packets to transmit from various
Logical layer modules
■ Logical layer features
■ Generation and management of transaction IDs
■ Automatic response generation and processing
■ Request to response time-out checking
■ Capability registers (CARs) and command and status registers (CSRs)
■ Direct register access, either remotely or locally
■ Maintenance master and slave Logical layer modules
■ Input/Output Avalon
®
Memory-Mapped (Avalon-MM) master and slave
Logical layer modules with burst support
■ Avalon streaming (Avalon-ST) interface for custom implementation of message
passing
■ Doorbell module supporting 16 outstanding
DOORBELL
packets with time-out
mechanism
■ Support for preservation of transaction order between outgoing
DOORBELL
messages and I/O write requests
■ New registers and interrupt indicate NWRITE_R transaction completion
■ Support for preservation of transaction order between outgoing I/O read
requests and I/O write requests from Avalon-MM interfaces
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■ Qsys support
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
Device Family Support
HDL simulators
■ Support for OpenCore Plus evaluation
Supported Transactions
The RapidIO IP core supports the following RapidIO transactions:
■
NREAD
request and response
■
NWRITE
■
NWRITE_R
■
SWRITE
■
MAINTENANCE
■
MAINTENANCE
■
MAINTENANCE
request
request and response
request
read request and response
write request and response
port-write request
■
DOORBELL
request and response
Device Family Support
Tab le 1– 1 defines the device support levels for Altera IP cores.
Table 1–1. Altera IP Core Device Support Levels
FPGA Device Families
Preliminary support—The IP core is verified with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. It can be used in production designs with caution.
Final support—The IP core is verified with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family and can be used in production
designs.
Tab le 1– 2 shows the level of support offered by the Rapid IO IP core for each Altera
device family.
Table 1–2. Device Family Support (Part 1 of 2)
Device Family Support
®
Arria
II GX Final
Arria II GZ Final
Arria V (GX, GT, GZ, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.
Arria 10 Refer to the What’s New in Altera IP page of the Altera website.
®
Cyclone
Cyclone V (GX, GT, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.
®
Stratix
IV Final
Stratix IV GT Final
IV GX
(1)
Final
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IP Core Verification
Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support
Stratix V Refer to the What’s New in Altera IP page of the Altera website.
Other device families No support
Note to Table 1–2:
(1) The RapidIO IP core supports only the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Cyclone IV GX devices.
IP Core Verification
Before releasing a version of the RapidIO IP core, Altera runs comprehensive
regression tests in the current version of the Quartus
MegaWizard
instance files. These files are tested in simulation and hardware to confirm
functionality.
Altera also performs interoperability testing to verify the performance of the IP core
and to ensure compatibility with ASSP devices.
The RapidIO IP core v9.0 successfully passed RIOLAB’s Device Interoperability
Level-3 (DIL-3) testing in 2009.
Simulation Testing
Altera verifies the RapidIO IP core using the following industry-standard simulators:
■ ModelSim
■ VCS in combination with the Synopsys Native Testbench (NTB)
The test suite contains testbenches that use the RapidIO bus functional model (BFM)
from the RapidIO Trade Association to verify the functionality of the IP core.
The regression suite tests various functions, including the following functionality:
■ Link initialization
■ Packet format
®
™
Plug-In Manager and the Qsys system integration tool to create the
®
simulator
II software. These tests use the
■ Packet priority
■ Error handling
■ Throughput
■ Flow control
Constrained random techniques generate appropriate stimulus for the functional
verification of the IP core. Functional coverage metrics measure the quality of the
random stimulus, and ensure that all important features are verified.
Hardware Testing
Altera tests and verifies the RapidIO IP core in hardware for different platforms and
environments.
The hardware tests cover 1x, 2x, and 4x variations running at 1.25, 2.5, 3.125, and
5.0 Gbaud, and processing the following traffic types:
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■
NREAD
s of various size payloads—4 bytes to 256 bytes
■
NWRITE
■
NWRITE_R
■
SWRITE
■
Port-writes
■
DOORBELL
■
MAINTENANCE
s of various size payloads—4 bytes to 256 bytes
s of a few different size packets
s
messages
reads and writes
Performance and Resource Utilization
The hardware tests also cover the following control symbol types:
■
Status
■
Packet-accepted
■
Packet-retry
■
Packet-not-accepted
■
Start-of-packet
■
End-of-packet
■
Link-request, Link-response
■
Stomp
■
Restart-from-retry
■
Multicast-event
Interoperability Testing
Altera performs interoperability tests on the RapidIO IP core, which certify that the
RapidIO IP core is compatible with third-party RapidIO devices.
Altera performs interoperability testing with processors and switches from various
manufacturers including:
■ Texas Instruments Incorporated
■ Integrated Device Technology, Inc. (IDT)
Testing of additional devices is an on-going process.
In addition, the RapidIO IP core v9.0 successfully passed RIOLAB’s Device
Interoperability Level-3 (DIL-3) testing in 2009.
Performance and Resource Utilization
This section contains tables showing IP core variation size and performance examples.
Tab le 1– 3 lists the resources and expected performance for selected variations that use
these modules:
■ Physical layer
■ Transport layer
■ Input/Output Avalon-MM master and slave
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Performance and Resource Utilization
■ Maintenance master and slave
Tab le 1– 4 to Table 1–6 list the resources and expected performance for selected
variations that use these modules:
■ Physical layer with 8 KByte transmit buffers and 4 KByte receive buffers
■ Transport layer
■ Input/Output Avalon-MM master and slave
The numbers of LEs, combinational ALUTs, ALMs, and primary logic registers are
rounded up to the nearest 100.
Tab le 1– 3 shows results obtained using the Quartus II software v14.0 Arria 10 Edition
for an Arria 10 10AX115S1F45E1LP device.
Table 1–3. RapidIO IP Core Arria 10 Resource Utilization
Parameters
Device
Arria 10
Variation Mode
Physical and
Transport layers,
I/O master and
slave, and
Maintenance
Baud Rate
(Gbaud)
1x
2x 11600 15400 900 70
5.00
4x 3.125 11300 15200 900 70
ALMs
10000 12500 800 79
master and slave
Tab le 1– 4 shows results obtained using the Quartus II software v13.0 for the following
devices:
■ Arria V GX (5AGXBB1D4F31C4)
■ Arria V GZ (5AGZME1H2F35C3)
■ Cyclone V (5CGXFC7C6F23C6)
■ Stratix V (5SGXMA7H2F35C2)
Table 1–4. RapidIO IP Core 28-nm Device Resource Utilization (Part 1 of 2)
Parameters
Device
Variation Mode
Physical layer only
Baud Rate
(Gbaud)
1x
2x 4600 6100 413 35
5.00
ALMs
4300 6000 336 35
4x 3.125 4300 6000 352 35
Arria V GX
Physical and
Transport layers,
and
I/O master and
slave
1x
2x 7400 10000 654 59
5.00
5300 7100 540 56
4x 3.125 7000 9800 621 59
Registers
Primary Secondary
Registers Memory
Primary Secondary
Memory
Blocks
(M20K)
Blocks
(M10K or
(1)
M20K
)
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Performance and Resource Utilization
Table 1–4. RapidIO IP Core 28-nm Device Resource Utilization (Part 2 of 2)
Parameters
Device
Variation Mode
Physical layer only
Baud Rate
(Gbaud)
1x
2x 4700 6100 482 27
ALMs
2800 3800 263 29
4x 4400 6000 440 27
Arria V GZ
Physical and
Transport layers,
and
I/O master and
slave
Physical layer only
1x 5700 7300 570 36
2x 7600 10000 797 39
4x 7200 9900 782 43
1x
2x 4600 5800 399 35
5.00
3.125
2900 3700 276 35
4x 2.5 4300 5600 357 35
Cyclone V GX
Physical and
Transport layers,
and
I/O master and
slave
Physical layer only
1x
2x 7100 9400 687 59
3.125
5300 7100 570 58
4x 2.5 6700 9300 580 59
1x
2700 3900 300 24
2x 4700 6100 491 20
4x 4500 6000 427 22
Stratix V GX
Physical and
Transport layers,
and
I/O master and
slave
Note to Table 1–4:
(1) M10K for Arria V and Cyclone V devices and M20K for Arria V GZ and Stratix V devices.
1x 5700 7300 585 36
2x 7700 10200 777 33
4x 7200 9900 828 44
5.00
Registers Memory
Primary Secondary
Blocks
(M10K or
(1)
M20K
)
Tab le 1– 5 shows results obtained using the Quartus II software v11.1 for a
Cyclone IV GX (EP4CGX50CF23C6) device.
Table 1–5. RapidIO IP Core Cyclone IV Resource Utilization
Device
Cyclone IV GX
Layers Lane Baud Rate (Gbaud)
Physical layer only
Physical and Transport
Parameters
LEs
1× 3.125 7,600 33
4× 2.500 10,200 32
1× 3.125 13,300 63
Memory:
M9K
layers,
and
4× 2.500 16,500 63
I/O master and slave
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Performance and Resource Utilization
Tab le 1– 6 shows results obtained using the Quartus II software v11.1 for the following
devices:
■ Stratix IV GX (EP4SGX230DF29C2)
■ Arria II GX (EP2AGX65DF25C4)
■ Arria II GZ (EP2AGZ225FF35C3)
Table 1–6. RapidIO IP Core Stratix IV and Legacy Arria Series Resource Utilization
Device
Stratix IV GX
Arria II GX
Arria II GZ
Parameters
Combinational
Layers Mode Baud Rate (Gbaud) M9K
Physical
layer
only
Physical and
1x 3.125 3,700 4,000 27 24
4x 3.125 5,200 5,900 25 38
1x 3.125 7,100 7,600 51 87
ALUTs
Logic
Registers
Transport
layers, and
I/O master and
4x 3.125 9,000 10,300 51 83
slave
Physical
layer
only
Physical and
1x 3.125 3,700 3,900 33 0
4x 3.125 5,400 5,800 32 0
1x 3.125 7,100 7,400 63 0
Transport
layers, and
I/O master and
4x 3.125 8,200 9,600 63 0
slave
Physical
layer
only
Physical and
1x 5.00 3,700 4,000 29 20
4x 3.125 5,500 6,000 29 38
1x 5.00 7,100 7,600 54 74
Transport
layers, and
I/O master and
4x 3.125 8,600 9,800 56 50
slave
Memory
Memory
ALUT
Tab le 1– 7 and Ta bl e 1 –8 show the recommended device family speed grades for the
supported link widths and internal clock frequencies. In all cases, Altera recommends
that you set Quartus II Analysis & Synthesis Optimization Technique to Speed.
f For information about how to apply the Speed setting, refer to volume 1 of the
Quartus II Handbook.
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Performance and Resource Utilization
Tab le 1– 7 shows the recommended device family speed grades for the Arria 10,
Arria V, Cyclone V, and Stratix V device families.
2.5
125
(1)
3.125 Gbaud
5.0
Gbaud
125
MHz
156.25 MHz
250
MHz
Table 1–7. Recommended Device Family Speed Grades for Newer Devices
Device
Family
Mode
Rate 1.25 Gbaud
1x,
f
2x
MAX
31.25 MHz 62.50 MHz 78.125 MHz
4x
62.5
MHz
Gbaud
MHz
1x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2
Arria 10
2x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2
4x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2
(2)
Arria V (GX,
GT, SX, ST)
1x C4, -5, C6 C4, -5, C6 C4, -5, C6 C4
2x C4, -5, C6 C4, -5, C6 C4, -5, C6 C4, -5
4x C4, -5, C6 C4, -5 C4
(2) (3)
1x -3, -4 -3, -4 -3, -4 -3
Arria V GZ
2x -3, -4 -3, -4 -3, -4 -3, -4
4x -3, -4 -3, -4 -3, -4 -3
1x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3
Stratix V
Cyclone V
(5)
(GX, GT
,
SX, ST)
Notes to Table 1–7:
(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device
family, RapidIO mode, and baud rate.
(2) Some simple Arria V 1× variations with lane speed of 5.0 Gbaud, and some simple Arria V 4× variations with lane speeds of 3.125 Gbaud, such
as physical-layer-only variations,may meet timing in -5 speed grade devices, after following the Timing Advisor’s recommendations.
(3) Not supported for this device family.
(4) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix V device, you
use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the Timing
Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially for more
complex variations implemented in the largest devices.
(5) Only the -7 speed grade is available for Cyclone V GT devices.
(6) The RapidIO IP core supports 1× 5.0 Gbaud variations that target the Cyclone V device family in speed grade C7 Cyclone V GT devices only. The
RapidIO parameter editor does not warn you of this fact. You can generate a 1× 5.0 Gbaud variation that targets a Cyclone V GX variation, for
example, but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on
page 2–8, the Quartus II software Analysis and Synthesis tool fails.
(7) The RapidIO IP core supports 2x 5.0 Gbaud variations that target the Cyclone V device family in Cyclone V GT devices only. The RapidIO
parameter editor does not warn you of this fact. You can generate a 2× 5.0 Gbaud variation that targets a Cyclone V GX variation, for example,
but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on page 2–8, the
Quartus II software Analysis and Synthesis tool fails.
2x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4
4x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3
1x C6, -7, C8 C6, -7, C8 C6, -7, C8 C7
2x C6, -7 C6, -7 C6, -7 -7
4x C6, -7, C8 C6, -7
(3) (3)
(4)
(6)
(7)
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Chapter 1: About This MegaCore Function 1–11
Release Information
Tab le 1– 8 shows the recommended device speed grades for earlier device families that
the RapidIO IP core supports.
Table 1–8. Recommended Device Family Speed Grades for Legacy Devices
(1)
Mode 1x 4x
Device
Family
Rate
f
MAX
1.25
Gbaud
31.25
MHz
Arria II GX -4, -5, -6 -4, -5, -6 -4, -5, -6
Arria II GZ -3, -4 -3, -4 -3, -4 -3 -3, -4 -3, -4 -3, -4
Stratix IV -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3
Cyclone IV GX
(4)
Notes to Table 1–8:
(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device
family, RapidIO mode, and baud rate.
(2) Not supported for this device family.
(3) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix IV GX device,
you use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the
Timing Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially
for more complex variations implemented in the largest devices.
(4) The RapidIO IP core supports only the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Cyclone IV GX devices.
(5) Some simple Cyclone IV GX 4× variations, such as physical-layer-only variations, may meet timing at 2.5 Gbaud in -7 speed grade devices, after
following the Timing Advisor’s recommendations.
-6, -7, -8 -6, -7, -8 -6, -7
2.5
Gbaud
62.50
MHz
3.125
Gbaud
78.125
MHz
Gbaud
MHz
(2)
(2)
5.0
125
1.25
Gbaud
62.5
MHz
2.5
Gbaud
125
MHz
3.125
Gbaud
156.25
MHz
-4, -5, -6 -4, -5 -4, -5
-6, -7, -8 -6
(5) (2) (2)
5.0
Gbaud
250
MHz
(2)
(2)
(3)
Release Information
Tab le 1– 9 provides information about this release of the RapidIO IP core.
Table 1–9. RapidIO Release Information
Version 14.0 14.0 Arria 10 Edition
Release Date June 2014 August 2014
Ordering Code IP-RIOPHY
Product ID 0095
Vendor ID 6AF7
Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. Any exceptions to this verification are reported in the
MegaCore IP Library Release Notes or in the errata for the RapidIO IP core in the
Knowledge Base. Altera does not verify compilation with IP core versions older than
the previous release.
Item Description
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User Guide
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Installation and Licensing
Installation and Licensing
The RapidIO IP core is part of the Altera MegaCore IP Library, which is distributed
with the Quartus II software and downloadable from the Altera website,
www.altera.com.
Figure 1–2 shows the directory structure after you install the RapidIO IP core, where
<
path> is the installation directory. The default installation directory on Windows is
C:\altera\<version number>; on Linux it is /opt/altera<version number>.
Figure 1–2. Directory Structure
<path>
Installation directory
ip
Contains the Altera MegaCore IP Library and third-party IP cores
altera
Contains the Altera MegaCore IP Library
common
Contains shared components
You can use Altera’s free OpenCore Plus evaluation feature to evaluate the IP core in
simulation and in hardware before you purchase a license. You must purchase a
license for the IP core only when you are satisfied with its functionality and
performance, and you want to take your design to production.
After you purchase a license for the RapidIO IP core, you can request a license file
from the Altera website at www.altera.com/licensing and install it on your computer.
When you request a license file, Altera emails you a license.dat file. If you do not have
internet access, contact your local Altera representative.
OpenCore Plus Evaluation
With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:
■ Simulate the behavior of a megafunction (Altera IP core or AMPP
megafunction) in your system using the Quartus II software and Altera-supported
VHDL and Verilog HDL simulators.
■ Verify the functionality of your design and evaluate its size and speed quickly and
easily.
altera_rapidio
Contains the _hw.tcl file for the RapidIO Qsys component
rapidio
Contains the RapidIO MegaCore function files
SM
■ Generate time-limited device programming files for designs that include IP cores.
■ Program a device and verify your design in hardware.
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Installation and Licensing
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following two operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1 For Altera IP cores, the untethered time-out is 1 hour; the tethered time-out value is
indefinite.
Your design stops working after the hardware evaluation time expires.
The RapidIO IP core then suppresses all packet transfers through the Physical layer.
As a result, the RapidIO IP core cannot transmit new packets (it only transmits the
idle sequence and status control symbols), and cannot read packets from the Physical
layer. If the remote link partner continues to transmit packets, the RapidIO IP core
refuses new packets by sending packet_retry control symbols after its receiver
buffer fills up beyond the corresponding threshold.
f
For Information About Refer To
Installation and licensing Altera Software Installation and Licensing
Open Core Plus AN 320: OpenCore Plus Evaluation of Megafunctions
August 2014 Altera Corporation RapidIO MegaCore Function
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Installation and Licensing
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
You can customize the RapidIO IP core to support a wide variety of applications.
When you generate the IP core you can choose whether or not to generate a
simulation model. If you generate a simulation model, Altera provides a Verilog
testbench customized for your IP core variation. If you specify a VHDL simulation
model, you must use a mixed-language simulator to run the testbench, or create your
own VHDL-only simulation environment.
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II
IP Catalog displays IP cores available for the current target device. The parameter
editor guides you to set parameter values for optional ports, features, and output files.
To customize and generate a custom IP core variation, follow these steps:
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP
core to customize. The parameter editor appears.
2. Getting Started
2. Specify a top-level name for your custom IP variation. This name identifies the IP
core variation files in your project. If prompted, also specify the target Altera
device family and output file HDL preference. Click OK.
3. Specify the desired parameters, output, and options for your IP core variation:
■ Optionally select preset parameter values. Presets specify all initial parameter
values for specific applications (where provided).
■ Specify parameters defining the IP core functionality, port configuration, and
device-specific features.
■ Specify options for generation of a timing netlist, simulation model, testbench,
or example design (where applicable).
■ Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching
your IP variation specifications. The parameter editor generates the top-level .qip
or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores
also simultaneously generate a testbench or example design for hardware testing.
When you generate the IP variation with a Quartus II project open, the parameter
editor automatically adds the IP variation to the project. Alternatively, click Project >
Add/Remove Files in Project to manually add a top-level .qip or .qsys IP variation
file to a Quartus II project. To fully integrate the IP into the design, make appropriate
pin assignments to connect ports. You can define a virtual pin to avoid making
specific pin assignments to top-level signals.
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
2–2 Chapter 2: Getting Started
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
<Project Directory>
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
<your_ip>.qip - Lists files for synthesis
testbench - Simulation testbench files
1
<testbench_hdl_files>
<simulator_vendor> - Testbench for supported simulators
<simulation_testbench_files>
<your_ip>.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
<your_ip>.sip - NativeLink simulation integration file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
<your_ip> - IP core variation files
<your_ip>.qip or .qsys - System or IP integration file
<your_ip>_generation.rpt - IP generation report
<your_ip>.bsf - Block symbol schematic file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.spd - Combines individual simulation startup scripts
1
<your_ip>.html - Contains memory map
<your_ip>.sopcinfo - Software tool-chain integration file
<your_ip>_syn.v or .vhd - Timing & resource estimation netlist
1
<your_ip>.debuginfo - Lists files for synthesis
<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models
2
<your_ip>_tb - Testbench for supported simulators
<your_ip>_tb.v or .vhd - Top-level HDL testbench file
Files Generated for Altera IP Cores (Legacy Parameter Editor)
Files Generated for Altera IP Cores (Legacy Parameter Editor)
The Quartus II software version 14.0 and previous parameter editor generates the
following output file structure for Altera IP cores:
Figure 2–1. IP Core Generated Files (Legacy Parameter Editor)
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
In the case of the non-Arria 10 RapidIO IP core, the testbench scripts for the different
simulators appear in <your_ip>/simulation/<vendor> and the testbench and
simulation files appear in <your_ip>/simulation/submodules. The main testbench file
is <your_ip>/simulation/submodules/<variation_name>_rapidio_0_tb.v.
The Quartus II software generates the <your_ip>/testbench directory if you click
Generate > Generate Testbench in the RapidIO parameter editor. However, the
resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP
core in any meaningful way. The Altera-provided RapidIO IP core testbench
described in Chapter 7, Testbenches is generated when you generate a simulation
model of the IP core. For non-Arria 10 variations, this testbench is available in
<your_ip>/simulation/submodules.
Chapter 2: Getting Started 2–3
Files Generated for Altera IP Cores
The RapidIO IP core does not generate an example design. The RapidIO installation
directory includes a static design example available in a separate location. Refer to
Chapter 8, Qsys Design Example.
Files Generated for Altera IP Cores
The Quartus II software version 14.0 Arria 10 Edition and later generates the
following output file structure for Altera IP cores:
Figure 2–2. IP Core Generated Files
<Project Directory>
<your_ip>.qsys - System or IP integration file
<your_ip>.sopcinfo - Software tool-chain integration file
<your_ip> - IP core variation files
<your_ip>.cmp - VHDL component declaration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Lists files for simulation
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - IP generation report
<your_ip>.html - Contains memory map
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines individual simulation startup scripts
sim - IP simulation files
<your_ip>.v or .vhd - Top-level simulation file
<EDA_tool_name> - Simulator setup scripts
<simulator_setup_scripts>
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
<IP subcore library> - IP subcore files
sim
<HDL files>
<your_testbench>_tb - Simulation testbench files
<your_ip>_tb.qsys - Testbench system file
<your_testbench>_tb
1. If supported and enabled for your IP variation
1
<your_testbench>_tb.csv
<your_testbench>_tb.spd
sim - IP core simulation files
1
1
In Arria 10 variations, the testbench files appear in
<your_ip>/altera_rapidio_140/sim/tb.
The Quartus II software generates the <your_testbench_name>_tb directory if you click
Generate > Generate Testbench in the RapidIO parameter editor. However, the
resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP
core in any meaningful way. The Altera-provided RapidIO IP core testbench for Arria
10 variations that is described in Chapter 7, Testbenches is generated when you
generate a simulation model of the IP core. This Arria 10 testbench is available in
<your_ip>/altera_rapidio_140/sim/tb.
The RapidIO IP core does not generate an example design. The static design example
included in the RapidIO installation directory does not function correctly with Arria
10 IP core variations.
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
2–4 Chapter 2: Getting Started
Simulating IP Cores
Simulating IP Cores
The Quartus II software supports RTL- and gate-level design simulation of Altera IP
cores in supported EDA simulators. Simulation involves setting up your simulator
working environment, compiling simulation model libraries, and running your
simulation.
You can use the functional simulation model and the testbench or example design
generated with your IP core for simulation. The functional simulation model and
testbench files are generated in a project subdirectory. This directory may also include
scripts to compile and run the testbench. For a complete list of models or libraries
required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation
files and scripts. NativeLink launches your preferred simulator from within the
Quartus II software.
For more information about simulating Altera IP cores, refer to Simulating Altera
Designs in volume 3 of the Quartus II Handbook.
Simulating the Testbench with the ModelSim Simulator
To simulate the RapidIO IP core testbench using the Mentor Graphics ModelSim
simulator, perform the following steps:
1. Start the ModelSim simulator.
2. For non-Arria 10 variations only, in ModelSim, change directory to
<your_ip>/simulation/submodules.
3. For non-Arria 10 variations only, type the following command to update the
simulation scripts in the simulator-specific directories:
do srio_simulator.tcl
r
4. Change directory to the location of the testbench script,
<your_ip>/simulation/mentor.
5. To set up the required libraries, compile the generated IP Functional simulation
model, and exercise the simulation model with the provided testbench, perform
one of the following steps:
a. For non-Arria 10 variations, type the following command:
do msim_setup.tcl
set TOP_LEVEL_NAME tb
ld
run -all
b. For Arria 10 variations, type the following command:
do msim_setup.tcl
set TOP_LEVEL_NAME <your_ip>_altera_rapidio_140.tb_rio
ld
run -all
Simulating the Testbench with the VCS Simulator
To simulate the RapidIO IP core testbench using the Synopsys VCS simulator, perform
the following steps:
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
Chapter 2: Getting Started 2–5
Integrating Your IP Core in Your Design
1. For non-Arria 10 variations only, change directory to
<your_ip>/simulation/submodules.
2. For non-Arria 10 variations only, type the following command to update the
simulation scripts in the simulator-specific directories:
do srio_simulator.tcl
r
3. Change directory to the location of the testbench script,
<your_ip>/simulation/synopsys/vcs.
4. Type the following command to set up the required libraries, compile the
generated IP functional simulation model, and exercise the simulation model with
the provided testbench:
sh vcs_setup.sh TOP_LEVEL_NAME="tb"
./simv
f
Quartus II software See the Quartus II Help topics:
IP Catalog
Altera simulation models
For Information About Refer To
Integrating Your IP Core in Your Design
When you integrate your IP core instance in your design, you must pay attention to
some additional requirements. If you generate your IP core from the Qsys IP catalog
and build your design in Qsys, you can perform these steps in Qsys. If you generate
your IP core directly from the Quartus II IP catalog, you must implement these steps
manually in your design.
“About the Quartus II Software”
“About the IP Catalog”
Simulating Altera Designs chapter in volume 3 of
the Quartus II Handbook
Calibration Clock
For Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX designs, ensure that
you connect the calibration clock (
frequency range of 10 to 125 MHz. The
cal_blk_clk
cal_blk_clk
) to a clock signal with the appropriate
ports on other components that
use transceivers must be connected to the same clock signal.
Dynamic Transceiver Reconfiguration Controller
RapidIO IP core variations that target an Aria 10 device include a reconfiguration
controller block and do not require an external reconfiguration controller. All other
RapidIO IP core variations require an external reconfiguration controller to function
correctly in hardware.
For Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX designs with
high-speed transceivers, you must add a dynamic reconfiguration block
(
altgx_reconfig
Device Handbook, the Cyclone IV Device Handbook, or the Stratix IV Device Handbook.
This block supports offset cancellation. The design compiles without the
altgx_reconfig
August 2014 Altera Corporation RapidIO MegaCore Function
) to your design. You must connect it as specified in the Arria II
block, but it cannot function correctly in hardware.
User Guide
2–6 Chapter 2: Getting Started
For Arria V, Cyclone V, and Stratix V designs, you must add a dynamic
reconfiguration block (Transceiver Reconfiguration Controller) to your design, and
connect it to the RapidIO IP core dynamic reconfiguration signals
and
reconfig_togxb
without the Transceiver Reconfiguration Controller, but it cannot function correctly in
hardware.
For information about the number of reconfiguration interfaces you must configure in
your Arria V, Cyclone V, or Stratix V dynamic reconfiguration block, refer to the
descriptions of the
page 5–4. An informational message in the RapidIO parameter editor tells you the
required number of reconfiguration interfaces.
f For information about the Altera Transceiver Reconfiguration Controller, refer to the
Altera Transceiver PHY IP Core User Guide.
. This block supports offset cancellation. The design compiles
reconfig_togxb
and
reconfig_fromgxb
Integrating Your IP Core in Your Design
reconfig_fromgxb
signals in Table 5–8 on
Transceiver Settings
If you want to modify the high-speed transceiver settings in an Arria II GX, Arria II
GZ, Cyclone IV GX, or Stratix IV GX variation, you must first generate the IP core and
then edit the existing ALTGX megafunction in the Quartus II software. Regenerating
overwrites the changes.
The ALTGX megafunction that is generated in your RapidIO IP core is not accesible
through Qsys. You must edit this megafunction using the Quartus II software.
If your RapidIO IP core targets an Arria V, Cyclone V, or Stratix V device, Altera
recommends you do not modify the default transceiver settings configured in the
Custom PHY IP core instance generated with the RapidIO IP core.
If your RapidIO IP core targets an Arria 10 device, Altera recommends you do not
modify the default transceiver settings configured in the Arria 10 Native PHY IP core.
Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
For Arria II GX, Arria II GZ, and Stratix IV GX designs, after you generate the system,
you must create assignments for the high-speed transceiver VCCH settings by
following these instructions:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor.
2. In the <<new>> cell in the To column, type the top-level signal name for your
RapidIO IP core instance
3. Double-click in the Assignment Name column and click I/O Standard.
4. Double-click in the Va l ue column and click your standard (for example, 1.5-V
PCML).
td
signal.
5. In the new <<new>> row, repeat steps 2 to 4 for your RapidIO IP core instance
signal.
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
rd
Chapter 2: Getting Started 2–7
Integrating Your IP Core in Your Design
External Transceiver PLL
RapidIO IP cores that target an Arria 10 device require an external TX transceiver PLL
to compile and to function correctly in hardware. You must instantiate and connect
this IP core to the RapidIO IP core.
You can create an external transceiver PLL from the IP Catalog. Select the ATX PLL IP
core. In the ATX TX PLL parameter editor, set the following parameter values:
■ Set PLL output frequency to one half the value you select for the Baud rate
parameter in the RapidIO parameter editor. The transceiver performs dual edge
clocking, using both the rising and falling edges of the input clock from the PLL.
Therefore, this PLL output frequency setting supports the customer-selected
maximum data rate on the RapidIO link.
■ Set PLL reference clock frequency to the value you select for the Reference clock
frequency parameter in the RapidIO parameter editor.
■ Turn o n Include Master Clock Generation Block.
■ Turn o n Enable bonding clock output ports.
■ Set PMA interface width to 20.
When you generate a RapidIO IP core, the Quartus II software also generates the HDL
code for an ATX PLL, in the file
<variation>/altera_rapidio_140/synth/altera_rapidio_tx_pll.sv. However, the HDL
code for the RapidIO IP core does not instantiate the ATX PLL. If you choose to use
the ATX PLL provided with the RapidIO IP core, you must instantiate and connect the
ATX PLL instance w i t h t he RapidIO IP core in user logic.
You must connect the TX PLL IP core to the RapidIO IP core according to the
following rules.
Table 2–1. External Transceiver TX PLL Connections to RapidIO IP Core
Signal Direction Connection Requirements
pll_refclk0
tx_bonding_clocks
[(6 x <number of
lanes>)–1:0]
Input
Output
Drive the PLL
core reference clock
source. The minimum allowed frequency for the
pll_refclk0
Connect
tx_bonding_clocks_chN
channel N, for each transceiver channel N that connects to
the RapidIO link. The transceiver channel input ports are
pll_refclk0
input port and the RapidIO IP
clk
signal from the same clock
clock in an Arria 10 ATX PLL is 100 MHz.
tx_bonding_clocks[6n+5:6n]
to the
input bus of transceiver
RapidIO IP core input ports.
For an example of how to configure and connect a TX PLL IP core to the other system
components, such as the external reset controller, refer to the cleartext testbench files
and Chapter 7, Testbenches.
f For information about the connection requirements and flexibility, refer to the Arria 10
Transceiver PHY User Guide.
August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
2–8 Chapter 2: Getting Started
Specifying Constraints
Specifying Constraints
For non-Arria 10 variations, Altera provides constraint files in Tcl format that you
must apply to ensure that the RapidIO IP core meets design timing requirements.
1 Constraints are not set automatically. You must run the Tcl constraint script to apply
the constraints.
To use the generated constraint files, follow these steps:
1. Open your Quartus II project in the Quartus II software.
2. On the View menu, point to Utility Windows and then click Tc l C on s o l e .
3. Source the generated constraint file by typing the following command at the Tcl
console command prompt:
source <variation_name>/synthesis/submodules/<instance_name>_constraints.tcl
r
4. Add the Rapid IO constraints to your project by typing the following command at
the Tcl console command prompt:
add_rio_constraints
r
This command adds the necessary logic constraints to your Quartus II project.
If you rename any clocks in Qsys, you require the
-phy_mgmt_clk
, and
-patch_sdc
command-line options specified in Ta bl e 2– 2.
-ref_clk_name, -sys_clk_name
The script automatically constrains the system clocks and the reference clock based on
the data rate chosen. For supported transceivers, Altera recommends that you adjust
the reference clock frequency in the Physical Layer tab of the RapidIO parameter
editor only. However, you can adjust the system clock frequency in the Tcl constraints
script or the generated Synopsys Design Constraint File (.sdc).
The Tcl script assumes that virtual pins and I/O standards are connected to
Altera-provided pin names. For user-defined pin names, you must edit the script after
generation to ensure that the assignments are made properly.
The
add_rio_constraints
command has the following additional options that you
can use:
add_rio_constraints [-no_compile]
[-ref_clk_name
[-patch_sdc]
<name>]
[-help]
[-sys_clk_name <
name
>] [-phy_mgmt_clk_name <
name
>]
,
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
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