Altera RapidIO MegaCore Function User Manual

RapidIO MegaCore Function v14.0 and v14.0 Arria 10
Edition User Guide

RapidIO MegaCore Function

User Guide

101 Innovation Drive
San Jose, CA 95134

www.altera.com

UG-MC_RIOPHY-4.1

Document last updated for Altera Complete Design Suite version:

Document publication date:

14.0 and 14.0 Arria 10 Edition
August 2014

Feedback Subscribe

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

Contents

Chapter 1. About This MegaCore Function

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

New Features in the RapidIO IP Core v14.0 and v14.0 Arria 10 Edition Releases . . . . . . . . . . . . . . . 1–2

RapidIO IP Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Supported Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

IP Core Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Simulation Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Hardware Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Interoperability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11

Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13

Chapter 2. Getting Started

Customizing and Generating IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Files Generated for Altera IP Cores (Legacy Parameter Editor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Files Generated for Altera IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Simulating IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Simulating the Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Simulating the Testbench with the VCS Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Integrating Your IP Core in Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Calibration Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Dynamic Transceiver Reconfiguration Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Transceiver Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations . . 2–6

External Transceiver PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Specifying Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

Compiling the Full Design and Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Instantiating Multiple RapidIO IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations . . . . . . . . . . . . . 2–10

Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX

Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances . . . . 2–12

Sourcing Multiple Tcl Scripts for non-Arria 10 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

Chapter 3. Parameter Settings

Physical Layer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Transceiver Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Enable Transceiver Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Synchronizing Transmitted ackID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Sending Link-Request Reset-Device on Fatal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Number of Link-Request Attempts Before Declaring Fatal Error . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Data Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

iv Contents

Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Reference Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Receive Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Transmit Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Receive Priority Retry Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Transport and Maintenance Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Enable 16-Bit Device ID Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Enable Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Destination ID Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

Input/Output Maintenance Logical Layer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Maintenance Logical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Transmit Address Translation Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Port Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Port Write Tx Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Port Write Rx Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

I/O and Doorbell Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

I/O Logical Layer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

I/O Slave Address Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

I/O Read and Write Order Preservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Doorbell Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Capability Registers Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Assembly Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Assembly ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Assembly Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Assembly Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Extended Features Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Processing Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Bridge Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Processor Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Switch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Enable Switch Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Number of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Port Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Data Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Source Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Destination Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10

Chapter 4. Functional Description

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

RapidIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Avalon-MM Interface Widths in the RapidIO IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Avalon-MM Interface Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Avalon Streaming (Avalon-ST) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2

Clocking and Reset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

RapidIO IP Core Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Contents v

Avalon System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

Other Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5

Baud Rates and Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6

Reset for RapidIO IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

General RapidIO Reset Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7

Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8

Reset Requirements for Arria V, Cyclone V, and Stratix V Variations . . . . . . . . . . . . . . . . . . . . . . 4–8

Reset Requirements for Arria 10 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

RapidIO IP Core Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

Physical Layer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11

Low-level Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Receiver Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

CRC Checking and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12

Low-Level Interface Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Transmitter Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Protocol and Flow Control Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13

Physical Layer Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

Error Conditions that Flush the Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Error Conditions Flagged for the Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15

Receive Priority Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16

Physical Layer Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Transmit and Retransmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Error Conditions that Flush the Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18

Forced Compensation Sequence Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20

Transaction ID Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

Logical Layer Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22

Concentrator Register Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

Maintenance Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26

Maintenance Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

Maintenance Slave Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28

Maintenance Master Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30

Port-Write Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–32

Maintenance Module Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33

Input/Output Logical Layer Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33

Input/Output Avalon-MM Master Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–34

RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions . . . . . . . . . . 4–36

Input/Output Avalon-MM Master Module Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40

Input/Output Avalon-MM Slave Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–41

Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets . . . . . . . . . . . . . . . . . . . . 4–48

Input/Output Avalon-MM Slave Module Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52

Doorbell Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53

Doorbell Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . 4–53

Preserving Transaction Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54

Doorbell Message Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55

Doorbell Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56

Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56

Pass-Through Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

vi Contents

Error Detection and Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61

Physical Layer Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61

Protocol Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62

Fatal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62

Logical Layer Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–62

Maintenance Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63

Maintenance Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64

Port-Write Reception Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65

Port-Write Transmission Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65

Input/Output Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65

Input/Output Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66

Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67

Chapter 5. Signals

Physical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Status Packet and Error Monitoring Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Multicast Event Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Receive Priority Retry Threshold-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

Physical Layer Buffer Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Transceiver Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Register-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Transport and Logical Layer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Avalon-MM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Avalon-ST Pass-Through Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13

Error Management Extension Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16

Packet and Error Monitoring Signal for the Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17

Chapter 6. Software Interface

Physical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

Transport and Logical Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Capability Registers (CARs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Command and Status Registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

Maintenance Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Receive Maintenance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Transmit Maintenance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Transmit Port-Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Receive Port-Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Input/Output Master Address Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Input/Output Slave Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

Input/Output Slave Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22

Transport Layer Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Error Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24

Doorbell Message Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26

Chapter 7. Testbenches

Reset, Initialization, and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3

Maintenance Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

SWRITE Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5

NWRITE_R Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6

NWRITE Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7

NREAD Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

Doorbell Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8

Doorbell and Write Transactions With Transaction Order Preservation . . . . . . . . . . . . . . . . . . . . . . . 7–9

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Contents vii

Port-Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10

Transactions Across the Avalon-ST Pass-Through Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11

Chapter 8. Qsys Design Example

Creating a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2

Running Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

Adding and Parameterizing the RapidIO Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4

Adding and Connecting Other System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6

Adding the Master Maintenance BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7

Adding the Master I/O BFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7

Adding the On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8

Connecting Clocks and the System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8

Connecting Unconnected Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9

Connecting System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9

Assigning Addresses and Setting the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10

Generating the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11

Simulating the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

Appendix A. Initialization Sequence

Appendix C. Porting a RapidIO Design from the Previous Version of the Software

Upgrading a RapidIO Design Without Changing Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Upgrading a RapidIO Design to the Arria 10 Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–5

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–5

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

viii Contents

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

1. About This MegaCore Function

DSP

ASSP

DSP

ASSP

CPU

MemoryMemoryMemory

Memory

DSP

Interface

Bridge

FPGA

Controller

RapidIO

MegaCore

Function

DSP

ASSP

Serial

Switch

RapidIO

System Interconnect

Proprietary,
CPRI, OBSAI,
Ethernet, etc.

The RapidIO® interconnect—an open standard developed by the RapidIO Trade
Association—is a high-performance packet-switched interconnect technology
designed to pass data and control information between microprocessors, digital signal
processors (DSPs), communications and network processors, system memories, and
peripheral devices.

The Altera
high-bandwidth, and coprocessing I/O applications. Figure 1–1 shows an example
system implementation.

Figure 1–1. Typical RapidIO Application

®

RapidIO MegaCore® function targets high-performance, multicomputing,

Features

This section outlines the features and supported transactions of the RapidIO IP core.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–2 Chapter 1: About This MegaCore Function

Features

New Features in the RapidIO IP Core v14.0 and v14.0 Arria 10 Edition Releases

The RapidIO IP core v14.0 Arria 10 Edition adds the following new feature:

■ Support for Arria 10 devices

The RapidIO IP core v14.0 adds the following new features:

■ All RapidIO IP core variations have a Transport layer.

■ All RapidIO IP core variations include configuration of the high-speed

transceivers on the device.

For details about changes to the IP core, refer to “Document Revision History” on

page Info–1. For an overview, refer to the RapidIO IP core chapter in the Altera

MegaCore IP Library Release Notes. IP core variations that target an Arria 10 device have

additional interfaces and design requirements.

f For information about the new Altera IP design flow in the Quartus II software v14.0

and v14.0 Arria 10 Edition, which impacts all Altera IP cores, refer to the
“Introduction to Altera IP Cores” section in the “Managing Quartus II Projects”
chapter in Volume 1: Design and Synthesis of the Quartus II Handbook and to Introduction

to Altera IP Cores.

The RapidIO IP core v13.1 does not add any new features.

RapidIO IP Core Features

The RapidIO IP core has the following features:

■ Compliant with RapidIO Trade Association, RapidIO Interconnect Specification,

Revision 2.1, August 2009, available from the RapidIO Trade Association website
at www.rapidio.org

■ Successfully passed RIOLAB’s Device Interoperability Level-3 (DIL-3) testing

■ Supports 8-bit or 16-bit device IDs

■ Supports incoming and outgoing multi-cast events

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–3

Features

■ Physical layer features

■ 1x/2x/4x serial with integrated transceivers in selected device families and

support for external transceivers in older device families

■ All four standard serial data rates supported: 1.25, 2.5, 3.125, and 5.0 gigabaud

(Gbaud)

■ Receive/transmit packet buffering, flow control, error detection, packet

assembly, and packet delineation

■ Automatic freeing of resources used by acknowledged packets

■ Automatic retransmission of retried packets

■ Scheduling of transmission, based on priority

■ Reset controller—fatal error does not require manual resetting

■ Optional automatic resetting of link partner after detection of fatal errors

■ Support for synchronizing with link partner’s expected ackID after reset

■ Full control over integrated transceiver parameters

■ Configurable number of recovery attempts after link response time-out before

declaring fatal error

■ Transport layer features

■ Supports multiple Logical layer modules

■ A round-robin outgoing scheduler chooses packets to transmit from various

Logical layer modules

■ Logical layer features

■ Generation and management of transaction IDs

■ Automatic response generation and processing

■ Request to response time-out checking

■ Capability registers (CARs) and command and status registers (CSRs)

■ Direct register access, either remotely or locally

■ Maintenance master and slave Logical layer modules

■ Input/Output Avalon

®

Memory-Mapped (Avalon-MM) master and slave

Logical layer modules with burst support

■ Avalon streaming (Avalon-ST) interface for custom implementation of message

passing

■ Doorbell module supporting 16 outstanding

DOORBELL

packets with time-out

mechanism

■ Support for preservation of transaction order between outgoing

DOORBELL

messages and I/O write requests

■ New registers and interrupt indicate NWRITE_R transaction completion

■ Support for preservation of transaction order between outgoing I/O read

requests and I/O write requests from Avalon-MM interfaces

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–4 Chapter 1: About This MegaCore Function

■ Qsys support

■ IP functional simulation models for use in Altera-supported VHDL and Verilog

Device Family Support

HDL simulators

■ Support for OpenCore Plus evaluation

Supported Transactions

The RapidIO IP core supports the following RapidIO transactions:

■

NREAD

request and response

■

NWRITE

■

NWRITE_R

■

SWRITE

■

MAINTENANCE

■

MAINTENANCE

■

MAINTENANCE

request

request and response

request

read request and response

write request and response

port-write request

■

DOORBELL

request and response

Device Family Support

Tab le 1– 1 defines the device support levels for Altera IP cores.

Table 1–1. Altera IP Core Device Support Levels

FPGA Device Families

Preliminary support—The IP core is verified with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. It can be used in production designs with caution.

Final support—The IP core is verified with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family and can be used in production
designs.

Tab le 1– 2 shows the level of support offered by the Rapid IO IP core for each Altera

device family.

Table 1–2. Device Family Support (Part 1 of 2)

Device Family Support

®

Arria

II GX Final

Arria II GZ Final

Arria V (GX, GT, GZ, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.

Arria 10 Refer to the What’s New in Altera IP page of the Altera website.

®

Cyclone

Cyclone V (GX, GT, SX, and ST) Refer to the What’s New in Altera IP page of the Altera website.

®

Stratix

IV Final

Stratix IV GT Final

IV GX

(1)

Final

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–5

IP Core Verification

Table 1–2. Device Family Support (Part 2 of 2)

Device Family Support

Stratix V Refer to the What’s New in Altera IP page of the Altera website.

Other device families No support

Note to Table 1–2:

(1) The RapidIO IP core supports only the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Cyclone IV GX devices.

IP Core Verification

Before releasing a version of the RapidIO IP core, Altera runs comprehensive
regression tests in the current version of the Quartus
MegaWizard
instance files. These files are tested in simulation and hardware to confirm
functionality.

Altera also performs interoperability testing to verify the performance of the IP core
and to ensure compatibility with ASSP devices.

The RapidIO IP core v9.0 successfully passed RIOLAB’s Device Interoperability
Level-3 (DIL-3) testing in 2009.

Simulation Testing

Altera verifies the RapidIO IP core using the following industry-standard simulators:

■ ModelSim

■ VCS in combination with the Synopsys Native Testbench (NTB)

The test suite contains testbenches that use the RapidIO bus functional model (BFM)
from the RapidIO Trade Association to verify the functionality of the IP core.

The regression suite tests various functions, including the following functionality:

■ Link initialization

■ Packet format

®

™

Plug-In Manager and the Qsys system integration tool to create the

®

simulator

II software. These tests use the

■ Packet priority

■ Error handling

■ Throughput

■ Flow control

Constrained random techniques generate appropriate stimulus for the functional
verification of the IP core. Functional coverage metrics measure the quality of the
random stimulus, and ensure that all important features are verified.

Hardware Testing

Altera tests and verifies the RapidIO IP core in hardware for different platforms and
environments.

The hardware tests cover 1x, 2x, and 4x variations running at 1.25, 2.5, 3.125, and

5.0 Gbaud, and processing the following traffic types:

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–6 Chapter 1: About This MegaCore Function

■

NREAD

s of various size payloads—4 bytes to 256 bytes

■

NWRITE

■

NWRITE_R

■

SWRITE

■

Port-writes

■

DOORBELL

■

MAINTENANCE

s of various size payloads—4 bytes to 256 bytes

s of a few different size packets

s

messages

reads and writes

Performance and Resource Utilization

The hardware tests also cover the following control symbol types:

■

Status

■

Packet-accepted

■

Packet-retry

■

Packet-not-accepted

■

Start-of-packet

■

End-of-packet

■

Link-request, Link-response

■

Stomp

■

Restart-from-retry

■

Multicast-event

Interoperability Testing

Altera performs interoperability tests on the RapidIO IP core, which certify that the
RapidIO IP core is compatible with third-party RapidIO devices.

Altera performs interoperability testing with processors and switches from various
manufacturers including:

■ Texas Instruments Incorporated

■ Integrated Device Technology, Inc. (IDT)

Testing of additional devices is an on-going process.

In addition, the RapidIO IP core v9.0 successfully passed RIOLAB’s Device
Interoperability Level-3 (DIL-3) testing in 2009.

Performance and Resource Utilization

This section contains tables showing IP core variation size and performance examples.

Tab le 1– 3 lists the resources and expected performance for selected variations that use

these modules:

■ Physical layer

■ Transport layer

■ Input/Output Avalon-MM master and slave

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–7

Performance and Resource Utilization

■ Maintenance master and slave

Tab le 1– 4 to Table 1–6 list the resources and expected performance for selected

variations that use these modules:

■ Physical layer with 8 KByte transmit buffers and 4 KByte receive buffers

■ Transport layer

■ Input/Output Avalon-MM master and slave

The numbers of LEs, combinational ALUTs, ALMs, and primary logic registers are
rounded up to the nearest 100.

Tab le 1– 3 shows results obtained using the Quartus II software v14.0 Arria 10 Edition

for an Arria 10 10AX115S1F45E1LP device.

Table 1–3. RapidIO IP Core Arria 10 Resource Utilization

Parameters

Device

Arria 10

Variation Mode

Physical and
Transport layers,
I/O master and
slave, and
Maintenance

Baud Rate

(Gbaud)

1x

2x 11600 15400 900 70

5.00

4x 3.125 11300 15200 900 70

ALMs

10000 12500 800 79

master and slave

Tab le 1– 4 shows results obtained using the Quartus II software v13.0 for the following

devices:

■ Arria V GX (5AGXBB1D4F31C4)

■ Arria V GZ (5AGZME1H2F35C3)

■ Cyclone V (5CGXFC7C6F23C6)

■ Stratix V (5SGXMA7H2F35C2)

Table 1–4. RapidIO IP Core 28-nm Device Resource Utilization (Part 1 of 2)

Parameters

Device

Variation Mode

Physical layer only

Baud Rate

(Gbaud)

1x

2x 4600 6100 413 35

5.00

ALMs

4300 6000 336 35

4x 3.125 4300 6000 352 35

Arria V GX

Physical and
Transport layers,
and
I/O master and
slave

1x

2x 7400 10000 654 59

5.00

5300 7100 540 56

4x 3.125 7000 9800 621 59

Registers

Primary Secondary

Registers Memory

Primary Secondary

Memory

Blocks
(M20K)

Blocks

(M10K or

(1)

M20K

)

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–8 Chapter 1: About This MegaCore Function

Performance and Resource Utilization

Table 1–4. RapidIO IP Core 28-nm Device Resource Utilization (Part 2 of 2)

Parameters

Device

Variation Mode

Physical layer only

Baud Rate

(Gbaud)

1x

2x 4700 6100 482 27

ALMs

2800 3800 263 29

4x 4400 6000 440 27

Arria V GZ

Physical and
Transport layers,
and
I/O master and
slave

Physical layer only

1x 5700 7300 570 36

2x 7600 10000 797 39

4x 7200 9900 782 43

1x

2x 4600 5800 399 35

5.00

3.125

2900 3700 276 35

4x 2.5 4300 5600 357 35

Cyclone V GX

Physical and
Transport layers,
and
I/O master and
slave

Physical layer only

1x

2x 7100 9400 687 59

3.125

5300 7100 570 58

4x 2.5 6700 9300 580 59

1x

2700 3900 300 24

2x 4700 6100 491 20

4x 4500 6000 427 22

Stratix V GX

Physical and
Transport layers,
and
I/O master and
slave

Note to Table 1–4:

(1) M10K for Arria V and Cyclone V devices and M20K for Arria V GZ and Stratix V devices.

1x 5700 7300 585 36

2x 7700 10200 777 33

4x 7200 9900 828 44

5.00

Registers Memory

Primary Secondary

Blocks

(M10K or

(1)

M20K

)

Tab le 1– 5 shows results obtained using the Quartus II software v11.1 for a

Cyclone IV GX (EP4CGX50CF23C6) device.

Table 1–5. RapidIO IP Core Cyclone IV Resource Utilization

Device

Cyclone IV GX

Layers Lane Baud Rate (Gbaud)

Physical layer only

Physical and Transport

Parameters

LEs

1× 3.125 7,600 33

4× 2.500 10,200 32

1× 3.125 13,300 63

Memory:

M9K

layers,
and

4× 2.500 16,500 63

I/O master and slave

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–9

Performance and Resource Utilization

Tab le 1– 6 shows results obtained using the Quartus II software v11.1 for the following

devices:

■ Stratix IV GX (EP4SGX230DF29C2)

■ Arria II GX (EP2AGX65DF25C4)

■ Arria II GZ (EP2AGZ225FF35C3)

Table 1–6. RapidIO IP Core Stratix IV and Legacy Arria Series Resource Utilization

Device

Stratix IV GX

Arria II GX

Arria II GZ

Parameters

Combinational

Layers Mode Baud Rate (Gbaud) M9K

Physical
layer
only

Physical and

1x 3.125 3,700 4,000 27 24

4x 3.125 5,200 5,900 25 38

1x 3.125 7,100 7,600 51 87

ALUTs

Logic

Registers

Transport
layers, and
I/O master and

4x 3.125 9,000 10,300 51 83

slave

Physical
layer
only

Physical and

1x 3.125 3,700 3,900 33 0

4x 3.125 5,400 5,800 32 0

1x 3.125 7,100 7,400 63 0
Transport
layers, and
I/O master and

4x 3.125 8,200 9,600 63 0

slave

Physical
layer
only

Physical and

1x 5.00 3,700 4,000 29 20

4x 3.125 5,500 6,000 29 38

1x 5.00 7,100 7,600 54 74
Transport
layers, and
I/O master and

4x 3.125 8,600 9,800 56 50

slave

Memory

Memory

ALUT

Tab le 1– 7 and Ta bl e 1 –8 show the recommended device family speed grades for the

supported link widths and internal clock frequencies. In all cases, Altera recommends
that you set Quartus II Analysis & Synthesis Optimization Technique to Speed.

f For information about how to apply the Speed setting, refer to volume 1 of the

Quartus II Handbook.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–10 Chapter 1: About This MegaCore Function

Performance and Resource Utilization

Tab le 1– 7 shows the recommended device family speed grades for the Arria 10,

Arria V, Cyclone V, and Stratix V device families.

2.5

125

(1)

3.125 Gbaud

5.0

Gbaud

125

MHz

156.25 MHz

250

MHz

Table 1–7. Recommended Device Family Speed Grades for Newer Devices

Device
Family

Mode

Rate 1.25 Gbaud

1x,

f

2x

MAX

31.25 MHz 62.50 MHz 78.125 MHz

4x

62.5
MHz

Gbaud

MHz

1x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2

Arria 10

2x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2

4x -1, -2, -3 -1, -2, -3 -1, -2, -3 -1, -2

(2)

Arria V (GX,
GT, SX, ST)

1x C4, -5, C6 C4, -5, C6 C4, -5, C6 C4

2x C4, -5, C6 C4, -5, C6 C4, -5, C6 C4, -5

4x C4, -5, C6 C4, -5 C4

(2) (3)

1x -3, -4 -3, -4 -3, -4 -3

Arria V GZ

2x -3, -4 -3, -4 -3, -4 -3, -4

4x -3, -4 -3, -4 -3, -4 -3

1x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3

Stratix V

Cyclone V

(5)

(GX, GT

,

SX, ST)

Notes to Table 1–7:

(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device

family, RapidIO mode, and baud rate.

(2) Some simple Arria V 1× variations with lane speed of 5.0 Gbaud, and some simple Arria V 4× variations with lane speeds of 3.125 Gbaud, such

as physical-layer-only variations,may meet timing in -5 speed grade devices, after following the Timing Advisor’s recommendations.
(3) Not supported for this device family.
(4) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix V device, you

use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the Timing

Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially for more

complex variations implemented in the largest devices.
(5) Only the -7 speed grade is available for Cyclone V GT devices.
(6) The RapidIO IP core supports 1× 5.0 Gbaud variations that target the Cyclone V device family in speed grade C7 Cyclone V GT devices only. The

RapidIO parameter editor does not warn you of this fact. You can generate a 1× 5.0 Gbaud variation that targets a Cyclone V GX variation, for

example, but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on

page 2–8, the Quartus II software Analysis and Synthesis tool fails.

(7) The RapidIO IP core supports 2x 5.0 Gbaud variations that target the Cyclone V device family in Cyclone V GT devices only. The RapidIO

parameter editor does not warn you of this fact. You can generate a 2× 5.0 Gbaud variation that targets a Cyclone V GX variation, for example,

but when you attempt to add the extra constraints required for the RapidIO IP core, as discussed in “Specifying Constraints” on page 2–8, the

Quartus II software Analysis and Synthesis tool fails.

2x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4

4x C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3, -4 C1, -2, -3

1x C6, -7, C8 C6, -7, C8 C6, -7, C8 C7

2x C6, -7 C6, -7 C6, -7 -7

4x C6, -7, C8 C6, -7

(3) (3)

(4)

(6)

(7)

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–11

Release Information

Tab le 1– 8 shows the recommended device speed grades for earlier device families that

the RapidIO IP core supports.

Table 1–8. Recommended Device Family Speed Grades for Legacy Devices

(1)

Mode 1x 4x

Device
Family

Rate

f

MAX

1.25

Gbaud

31.25
MHz

Arria II GX -4, -5, -6 -4, -5, -6 -4, -5, -6

Arria II GZ -3, -4 -3, -4 -3, -4 -3 -3, -4 -3, -4 -3, -4

Stratix IV -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3

Cyclone IV GX

(4)

Notes to Table 1–8:

(1) In this table, the entry -n indicates that both the industrial speed grade In and the commercial speed grade Cn are supported for this device

family, RapidIO mode, and baud rate.
(2) Not supported for this device family.
(3) Altera recommends that for designs that include a 4× 5.0 Gbaud RapidIO IP core variation and that target a -3 speed grade Stratix IV GX device,

you use multiple seeds in the Quartus II Design Space Explorer to find the optimal Fitter settings to meet the timing constraints. Following the

Timing Advisor's recommendations, including optimizing for speed and using LogicLock regions may be necessary to meet timing, especially

for more complex variations implemented in the largest devices.
(4) The RapidIO IP core supports only the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Cyclone IV GX devices.
(5) Some simple Cyclone IV GX 4× variations, such as physical-layer-only variations, may meet timing at 2.5 Gbaud in -7 speed grade devices, after

following the Timing Advisor’s recommendations.

-6, -7, -8 -6, -7, -8 -6, -7

2.5

Gbaud

62.50
MHz

3.125
Gbaud

78.125
MHz

Gbaud

MHz

(2)

(2)

5.0

125

1.25

Gbaud

62.5
MHz

2.5

Gbaud

125

MHz

3.125

Gbaud

156.25
MHz

-4, -5, -6 -4, -5 -4, -5

-6, -7, -8 -6

(5) (2) (2)

5.0

Gbaud

250

MHz

(2)

(2)

(3)

Release Information

Tab le 1– 9 provides information about this release of the RapidIO IP core.

Table 1–9. RapidIO Release Information

Version 14.0 14.0 Arria 10 Edition

Release Date June 2014 August 2014

Ordering Code IP-RIOPHY

Product ID 0095

Vendor ID 6AF7

Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. Any exceptions to this verification are reported in the

MegaCore IP Library Release Notes or in the errata for the RapidIO IP core in the

Knowledge Base. Altera does not verify compilation with IP core versions older than

the previous release.

Item Description

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–12 Chapter 1: About This MegaCore Function

Installation and Licensing

Installation and Licensing

The RapidIO IP core is part of the Altera MegaCore IP Library, which is distributed
with the Quartus II software and downloadable from the Altera website,

www.altera.com.

Figure 1–2 shows the directory structure after you install the RapidIO IP core, where

<

path> is the installation directory. The default installation directory on Windows is

C:\altera\<version number>; on Linux it is /opt/altera<version number>.

Figure 1–2. Directory Structure

<path>

Installation directory

ip

Contains the Altera MegaCore IP Library and third-party IP cores

altera

Contains the Altera MegaCore IP Library

common

Contains shared components

You can use Altera’s free OpenCore Plus evaluation feature to evaluate the IP core in
simulation and in hardware before you purchase a license. You must purchase a
license for the IP core only when you are satisfied with its functionality and
performance, and you want to take your design to production.

After you purchase a license for the RapidIO IP core, you can request a license file
from the Altera website at www.altera.com/licensing and install it on your computer.
When you request a license file, Altera emails you a license.dat file. If you do not have
internet access, contact your local Altera representative.

OpenCore Plus Evaluation

With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:

■ Simulate the behavior of a megafunction (Altera IP core or AMPP

megafunction) in your system using the Quartus II software and Altera-supported
VHDL and Verilog HDL simulators.

■ Verify the functionality of your design and evaluate its size and speed quickly and

easily.

altera_rapidio

Contains the _hw.tcl file for the RapidIO Qsys component

rapidio

Contains the RapidIO MegaCore function files

SM

■ Generate time-limited device programming files for designs that include IP cores.

■ Program a device and verify your design in hardware.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 1: About This MegaCore Function 1–13

Installation and Licensing

OpenCore Plus Time-Out Behavior

OpenCore Plus hardware evaluation supports the following two operation modes:

■ Untethered—the design runs for a limited time.

■ Tethered—requires a connection between your board and the host computer. If

tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.

All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior may be masked by the time-out behavior of
the other megafunctions.

1 For Altera IP cores, the untethered time-out is 1 hour; the tethered time-out value is

indefinite.

Your design stops working after the hardware evaluation time expires.

The RapidIO IP core then suppresses all packet transfers through the Physical layer.
As a result, the RapidIO IP core cannot transmit new packets (it only transmits the
idle sequence and status control symbols), and cannot read packets from the Physical
layer. If the remote link partner continues to transmit packets, the RapidIO IP core
refuses new packets by sending packet_retry control symbols after its receiver
buffer fills up beyond the corresponding threshold.

f

For Information About Refer To

Installation and licensing Altera Software Installation and Licensing

Open Core Plus AN 320: OpenCore Plus Evaluation of Megafunctions

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

1–14 Chapter 1: About This MegaCore Function

Installation and Licensing

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

You can customize the RapidIO IP core to support a wide variety of applications.

When you generate the IP core you can choose whether or not to generate a
simulation model. If you generate a simulation model, Altera provides a Verilog
testbench customized for your IP core variation. If you specify a VHDL simulation
model, you must use a mixed-language simulator to run the testbench, or create your
own VHDL-only simulation environment.

Customizing and Generating IP Cores

You can customize IP cores to support a wide variety of applications. The Quartus II
IP Catalog displays IP cores available for the current target device. The parameter
editor guides you to set parameter values for optional ports, features, and output files.

To customize and generate a custom IP core variation, follow these steps:

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP
core to customize. The parameter editor appears.

2. Getting Started

2. Specify a top-level name for your custom IP variation. This name identifies the IP
core variation files in your project. If prompted, also specify the target Altera
device family and output file HDL preference. Click OK.

3. Specify the desired parameters, output, and options for your IP core variation:

■ Optionally select preset parameter values. Presets specify all initial parameter

values for specific applications (where provided).

■ Specify parameters defining the IP core functionality, port configuration, and

device-specific features.

■ Specify options for generation of a timing netlist, simulation model, testbench,

or example design (where applicable).

■ Specify options for processing the IP core files in other EDA tools.

4. Click Finish or Generate to generate synthesis and other optional files matching
your IP variation specifications. The parameter editor generates the top-level .qip
or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores
also simultaneously generate a testbench or example design for hardware testing.

When you generate the IP variation with a Quartus II project open, the parameter
editor automatically adds the IP variation to the project. Alternatively, click Project >
Add/Remove Files in Project to manually add a top-level .qip or .qsys IP variation
file to a Quartus II project. To fully integrate the IP into the design, make appropriate
pin assignments to connect ports. You can define a virtual pin to avoid making
specific pin assignments to top-level signals.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

2–2 Chapter 2: Getting Started

Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<Project Directory>

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<your_ip>_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

<your_ip>.qip - Lists files for synthesis

testbench - Simulation testbench files

1

<testbench_hdl_files>

<simulator_vendor> - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>.sip - NativeLink simulation integration file

<simulator vendor> - Simulator setup scripts

<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.qip or .qsys - System or IP integration file

<your_ip>_generation.rpt - IP generation report

<your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file

<your_ip>.spd - Combines individual simulation startup scripts

1

<your_ip>.html - Contains memory map

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

1

<your_ip>.debuginfo - Lists files for synthesis

<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models

2

<your_ip>_tb - Testbench for supported simulators

<your_ip>_tb.v or .vhd - Top-level HDL testbench file

Files Generated for Altera IP Cores (Legacy Parameter Editor)

Files Generated for Altera IP Cores (Legacy Parameter Editor)

The Quartus II software version 14.0 and previous parameter editor generates the
following output file structure for Altera IP cores:

Figure 2–1. IP Core Generated Files (Legacy Parameter Editor)

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

In the case of the non-Arria 10 RapidIO IP core, the testbench scripts for the different
simulators appear in <your_ip>/simulation/<vendor> and the testbench and
simulation files appear in <your_ip>/simulation/submodules. The main testbench file
is <your_ip>/simulation/submodules/<variation_name>_rapidio_0_tb.v.

The Quartus II software generates the <your_ip>/testbench directory if you click
Generate > Generate Testbench in the RapidIO parameter editor. However, the
resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP
core in any meaningful way. The Altera-provided RapidIO IP core testbench
described in Chapter 7, Testbenches is generated when you generate a simulation
model of the IP core. For non-Arria 10 variations, this testbench is available in
<your_ip>/simulation/submodules.

Chapter 2: Getting Started 2–3

Files Generated for Altera IP Cores

The RapidIO IP core does not generate an example design. The RapidIO installation
directory includes a static design example available in a separate location. Refer to

Chapter 8, Qsys Design Example.

Files Generated for Altera IP Cores

The Quartus II software version 14.0 Arria 10 Edition and later generates the
following output file structure for Altera IP cores:

Figure 2–2. IP Core Generated Files

<Project Directory>

<your_ip>.qsys - System or IP integration file

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip> - IP core variation files

<your_ip>.cmp - VHDL component declaration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>.ppf - XML I/O pin information file

<your_ip>.qip - Lists IP synthesis files

<your_ip>.sip - Lists files for simulation

<your_ip>_generation.rpt - IP generation report

<your_ip>.debuginfo - IP generation report

<your_ip>.html - Contains memory map

<your_ip>.bsf - Block symbol schematic

<your_ip>.spd - Combines individual simulation startup scripts

sim - IP simulation files

<your_ip>.v or .vhd - Top-level simulation file

<EDA_tool_name> - Simulator setup scripts

<simulator_setup_scripts>

synth - IP synthesis files

<your_ip>.v or .vhd - Top-level IP synthesis file

<IP subcore library> - IP subcore files

sim

<HDL files>

<your_testbench>_tb - Simulation testbench files

<your_ip>_tb.qsys - Testbench system file

<your_testbench>_tb

1. If supported and enabled for your IP variation

1

<your_testbench>_tb.csv

<your_testbench>_tb.spd

sim - IP core simulation files

1

1

In Arria 10 variations, the testbench files appear in
<your_ip>/altera_rapidio_140/sim/tb.

The Quartus II software generates the <your_testbench_name>_tb directory if you click
Generate > Generate Testbench in the RapidIO parameter editor. However, the
resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP
core in any meaningful way. The Altera-provided RapidIO IP core testbench for Arria
10 variations that is described in Chapter 7, Testbenches is generated when you
generate a simulation model of the IP core. This Arria 10 testbench is available in
<your_ip>/altera_rapidio_140/sim/tb.

The RapidIO IP core does not generate an example design. The static design example
included in the RapidIO installation directory does not function correctly with Arria
10 IP core variations.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

2–4 Chapter 2: Getting Started

Simulating IP Cores

Simulating IP Cores

The Quartus II software supports RTL- and gate-level design simulation of Altera IP
cores in supported EDA simulators. Simulation involves setting up your simulator
working environment, compiling simulation model libraries, and running your
simulation.

You can use the functional simulation model and the testbench or example design
generated with your IP core for simulation. The functional simulation model and
testbench files are generated in a project subdirectory. This directory may also include
scripts to compile and run the testbench. For a complete list of models or libraries
required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation
files and scripts. NativeLink launches your preferred simulator from within the
Quartus II software.

For more information about simulating Altera IP cores, refer to Simulating Altera

Designs in volume 3 of the Quartus II Handbook.

Simulating the Testbench with the ModelSim Simulator

To simulate the RapidIO IP core testbench using the Mentor Graphics ModelSim
simulator, perform the following steps:

1. Start the ModelSim simulator.

2. For non-Arria 10 variations only, in ModelSim, change directory to
<your_ip>/simulation/submodules.

3. For non-Arria 10 variations only, type the following command to update the
simulation scripts in the simulator-specific directories:

do srio_simulator.tcl

r

4. Change directory to the location of the testbench script,
<your_ip>/simulation/mentor.

5. To set up the required libraries, compile the generated IP Functional simulation
model, and exercise the simulation model with the provided testbench, perform
one of the following steps:

a. For non-Arria 10 variations, type the following command:

do msim_setup.tcl
set TOP_LEVEL_NAME tb
ld
run -all

b. For Arria 10 variations, type the following command:

do msim_setup.tcl
set TOP_LEVEL_NAME <your_ip>_altera_rapidio_140.tb_rio
ld
run -all

Simulating the Testbench with the VCS Simulator

To simulate the RapidIO IP core testbench using the Synopsys VCS simulator, perform
the following steps:

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 2: Getting Started 2–5

Integrating Your IP Core in Your Design

1. For non-Arria 10 variations only, change directory to
<your_ip>/simulation/submodules.

2. For non-Arria 10 variations only, type the following command to update the
simulation scripts in the simulator-specific directories:

do srio_simulator.tcl

r

3. Change directory to the location of the testbench script,
<your_ip>/simulation/synopsys/vcs.

4. Type the following command to set up the required libraries, compile the
generated IP functional simulation model, and exercise the simulation model with
the provided testbench:

sh vcs_setup.sh TOP_LEVEL_NAME="tb"
./simv

f

Quartus II software See the Quartus II Help topics:

IP Catalog

Altera simulation models

For Information About Refer To

Integrating Your IP Core in Your Design

When you integrate your IP core instance in your design, you must pay attention to
some additional requirements. If you generate your IP core from the Qsys IP catalog
and build your design in Qsys, you can perform these steps in Qsys. If you generate
your IP core directly from the Quartus II IP catalog, you must implement these steps
manually in your design.

“About the Quartus II Software”

“About the IP Catalog”

Simulating Altera Designs chapter in volume 3 of

the Quartus II Handbook

Calibration Clock

For Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX designs, ensure that
you connect the calibration clock (
frequency range of 10 to 125 MHz. The

cal_blk_clk

cal_blk_clk

) to a clock signal with the appropriate

ports on other components that

use transceivers must be connected to the same clock signal.

Dynamic Transceiver Reconfiguration Controller

RapidIO IP core variations that target an Aria 10 device include a reconfiguration
controller block and do not require an external reconfiguration controller. All other
RapidIO IP core variations require an external reconfiguration controller to function
correctly in hardware.

For Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX designs with
high-speed transceivers, you must add a dynamic reconfiguration block
(

altgx_reconfig

Device Handbook, the Cyclone IV Device Handbook, or the Stratix IV Device Handbook.

This block supports offset cancellation. The design compiles without the

altgx_reconfig

August 2014 Altera Corporation RapidIO MegaCore Function

) to your design. You must connect it as specified in the Arria II

block, but it cannot function correctly in hardware.

User Guide

2–6 Chapter 2: Getting Started

For Arria V, Cyclone V, and Stratix V designs, you must add a dynamic
reconfiguration block (Transceiver Reconfiguration Controller) to your design, and
connect it to the RapidIO IP core dynamic reconfiguration signals
and

reconfig_togxb

without the Transceiver Reconfiguration Controller, but it cannot function correctly in
hardware.

For information about the number of reconfiguration interfaces you must configure in
your Arria V, Cyclone V, or Stratix V dynamic reconfiguration block, refer to the
descriptions of the

page 5–4. An informational message in the RapidIO parameter editor tells you the

required number of reconfiguration interfaces.

f For information about the Altera Transceiver Reconfiguration Controller, refer to the

Altera Transceiver PHY IP Core User Guide.

. This block supports offset cancellation. The design compiles

reconfig_togxb

and

reconfig_fromgxb

Integrating Your IP Core in Your Design

reconfig_fromgxb

signals in Table 5–8 on

Transceiver Settings

If you want to modify the high-speed transceiver settings in an Arria II GX, Arria II
GZ, Cyclone IV GX, or Stratix IV GX variation, you must first generate the IP core and
then edit the existing ALTGX megafunction in the Quartus II software. Regenerating
overwrites the changes.

The ALTGX megafunction that is generated in your RapidIO IP core is not accesible
through Qsys. You must edit this megafunction using the Quartus II software.

If your RapidIO IP core targets an Arria V, Cyclone V, or Stratix V device, Altera
recommends you do not modify the default transceiver settings configured in the
Custom PHY IP core instance generated with the RapidIO IP core.

If your RapidIO IP core targets an Arria 10 device, Altera recommends you do not
modify the default transceiver settings configured in the Arria 10 Native PHY IP core.

Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations

For Arria II GX, Arria II GZ, and Stratix IV GX designs, after you generate the system,
you must create assignments for the high-speed transceiver VCCH settings by
following these instructions:

1. In the Quartus II window, on the Assignments menu, click Assignment Editor.

2. In the <<new>> cell in the To column, type the top-level signal name for your
RapidIO IP core instance

3. Double-click in the Assignment Name column and click I/O Standard.

4. Double-click in the Va l ue column and click your standard (for example, 1.5-V
PCML).

td

signal.

5. In the new <<new>> row, repeat steps 2 to 4 for your RapidIO IP core instance
signal.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

rd

Chapter 2: Getting Started 2–7

Integrating Your IP Core in Your Design

External Transceiver PLL

RapidIO IP cores that target an Arria 10 device require an external TX transceiver PLL
to compile and to function correctly in hardware. You must instantiate and connect
this IP core to the RapidIO IP core.

You can create an external transceiver PLL from the IP Catalog. Select the ATX PLL IP
core. In the ATX TX PLL parameter editor, set the following parameter values:

■ Set PLL output frequency to one half the value you select for the Baud rate

parameter in the RapidIO parameter editor. The transceiver performs dual edge
clocking, using both the rising and falling edges of the input clock from the PLL.
Therefore, this PLL output frequency setting supports the customer-selected
maximum data rate on the RapidIO link.

■ Set PLL reference clock frequency to the value you select for the Reference clock

frequency parameter in the RapidIO parameter editor.

■ Turn o n Include Master Clock Generation Block.

■ Turn o n Enable bonding clock output ports.

■ Set PMA interface width to 20.

When you generate a RapidIO IP core, the Quartus II software also generates the HDL
code for an ATX PLL, in the file
<variation>/altera_rapidio_140/synth/altera_rapidio_tx_pll.sv. However, the HDL
code for the RapidIO IP core does not instantiate the ATX PLL. If you choose to use
the ATX PLL provided with the RapidIO IP core, you must instantiate and connect the
ATX PLL instance w i t h t he RapidIO IP core in user logic.

You must connect the TX PLL IP core to the RapidIO IP core according to the
following rules.

Table 2–1. External Transceiver TX PLL Connections to RapidIO IP Core

Signal Direction Connection Requirements

pll_refclk0

tx_bonding_clocks
[(6 x <number of
lanes>)–1:0]

Input

Output

Drive the PLL
core reference clock
source. The minimum allowed frequency for the

pll_refclk0

Connect

tx_bonding_clocks_chN

channel N, for each transceiver channel N that connects to
the RapidIO link. The transceiver channel input ports are

pll_refclk0

input port and the RapidIO IP

clk

signal from the same clock

clock in an Arria 10 ATX PLL is 100 MHz.

tx_bonding_clocks[6n+5:6n]

to the

input bus of transceiver

RapidIO IP core input ports.

For an example of how to configure and connect a TX PLL IP core to the other system
components, such as the external reset controller, refer to the cleartext testbench files
and Chapter 7, Testbenches.

f For information about the connection requirements and flexibility, refer to the Arria 10

Transceiver PHY User Guide.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

2–8 Chapter 2: Getting Started

Specifying Constraints

Specifying Constraints

For non-Arria 10 variations, Altera provides constraint files in Tcl format that you
must apply to ensure that the RapidIO IP core meets design timing requirements.

1 Constraints are not set automatically. You must run the Tcl constraint script to apply

the constraints.

To use the generated constraint files, follow these steps:

1. Open your Quartus II project in the Quartus II software.

2. On the View menu, point to Utility Windows and then click Tc l C on s o l e .

3. Source the generated constraint file by typing the following command at the Tcl
console command prompt:

source <variation_name>/synthesis/submodules/<instance_name>_constraints.tcl

r

4. Add the Rapid IO constraints to your project by typing the following command at
the Tcl console command prompt:

add_rio_constraints

r

This command adds the necessary logic constraints to your Quartus II project.

If you rename any clocks in Qsys, you require the

-phy_mgmt_clk

, and

-patch_sdc

command-line options specified in Ta bl e 2– 2.

-ref_clk_name, -sys_clk_name

The script automatically constrains the system clocks and the reference clock based on
the data rate chosen. For supported transceivers, Altera recommends that you adjust
the reference clock frequency in the Physical Layer tab of the RapidIO parameter
editor only. However, you can adjust the system clock frequency in the Tcl constraints
script or the generated Synopsys Design Constraint File (.sdc).

The Tcl script assumes that virtual pins and I/O standards are connected to
Altera-provided pin names. For user-defined pin names, you must edit the script after
generation to ensure that the assignments are made properly.

The

add_rio_constraints

command has the following additional options that you

can use:

add_rio_constraints [-no_compile]
[-ref_clk_name
[-patch_sdc]

<name>]

[-help]

[-sys_clk_name <

name

>] [-phy_mgmt_clk_name <

name

>]

,

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 2: Getting Started 2–9

Compiling the Full Design and Programming the FPGA

Tab le 2– 2 explains these options.

Table 2–2. add_rio_constraints Options

Constraint Use

-no_compile

-ref_clk_name

-sys_clk_name

Use the
performed analysis and synthesis or fully compiled your project prior to using this script. Using
this option decreases turnaround time during development.

The Rapid IO IP core has a top-level reference clock name
or you connect the reference clock port of the IP core to a clock named something other than
you must run the
clock connected to the reference clock port of the RapidIO IP core. The following example
command illustrates the syntax:

By default, the Avalon system clock name used for the RapidIO IP core is named
Qsys, you rename this clock or connect it to a clock named something other than
must run the
name. The following example command illustrates the syntax:

-no_compile

add_rio_constraints -ref_clk_name CLK125

add_rio_constraints

option to prevent analysis and synthesis. Use this option only if you

add_rio_constraints

command with this option followed by the name of the

command with this option followed by the updated clock

clk

. If, in Qsys, you rename this clock

sysclk

sysclk

clk

. If, in

, you

,

add_rio_constraints -sys_clk_name CLK50

This option is available only for RapidIO variations that target an Arria V, Cyclone V, or Stratix V
device. By default, the PHY IP core management clock, which is present only in RapidIO variations

phy_mgmt_clk

-phy_mgmt_clk_name

-patch_sdc

-help

that target an Arria V, Cyclone V, or Stratix V device, is named
rename this clock or you connect it to a clock named something other than
<variation>_
followed by the updated clock name. The following example command illustrates the syntax:

add_rio_constraints -phy_mgmt_clk_name CLK_PHY_MGMT

This option is only valid when used with the

-phy_mgmt_clk

clock names. A back-up copy of the SDC script is created before the patch is made, and any edits
that were previously made to the SDC script are preserved.

Use the
command.

phy_mgmt_clk

option. The

-help

option for information about the options used with the

, you must run the

-ref_clk_name, -sys_clk_name

-patch_sdc

option patches the generated SDC script with the new

add_rio_constraints

f For more information about timing analyzers, refer to the Quartus II Help and the

Timing Analysis section in volume 3 of the Quartus II Handbook.

Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the
Quartus II software to compile your design. After successfully compiling your design,
program the targeted Altera device with the Programmer and verify the design in
hardware.

. If, in Qsys, you

command with this option

, or

add_rio_constraints

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

2–10 Chapter 2: Getting Started

1 Before compiling your design in the Quartus II software, you must apply the

constraints as described in “Specifying Constraints” on page 2–8.

Instantiating Multiple RapidIO IP Cores

f

For Information About Refer To

Compiling your design

Programming the device

Quartus II Incremental Compilation for Hierarchical and Team­Based Design chapter in volume 1 of the Quartus II Handbook

Device Programming section in volume 3 of the Quartus II
Handbook

Instantiating Multiple RapidIO IP Cores

If you want to instantiate multiple RapidIO IP cores, a few additional steps are
required. The following sections outline these steps.

Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations

When your design targets an Arria V, Cyclone V, or Stratix V device, the transceivers
are configured with the Altera Custom PHY IP core. When your design contains
multiple RapidIO IP cores, the Quartus II Fitter handles the merge of multiple Custom
PHY IP cores in the same transceiver block automatically. To merge multiple Custom
PHY IP cores in the same transceiver block, the Fitter requires that the

phy_mgmt_clk_reset

source.

If you have different RapidIO IP cores in different transceiver blocks on your device,
you may choose to include multiple Transceiver Reconfiguration Controllers in your
design. However, you must ensure that the Transceiver Reconfiguration Controllers
that you add to your design have the correct number of interfaces to control dynamic
reconfiguration of all your RapidIO IP core transceivers. The correct total number of
reconfiguration interfaces is the sum of the reconfiguration interfaces for each
RapidIO IP core; the number of reconfiguration interfaces for each RapidIO IP core is
the number of channels plus one. You must ensure that the

reconfig_fromgxb

Transceiver Reconfiguration Controller.

input signal for all of the merged IP cores be driven by the same

signals of an individual RapidIO IP core connect to a single

reconfig_togxb

and

For example, if your design includes one 4× RapidIO IP core and three 1× RapidIO IP
cores, the Transceiver Reconfiguration Controllers in your design must include eleven
dynamic reconfiguration interfaces: five for the 4× RapidIO IP core, and two for each
of the 1× RapidIO IP cores. The dynamic reconfiguration interfaces connected to a
single RapidIO IP core must belong to the same Transceiver Reconfiguration
Controller. In most cases, your design has only a single Transceiver Reconfiguration
Controller, which has eleven dynamic reconfiguration interfaces. If you choose to use
two Transceiver Reconfiguration Controllers, for example, to accommodate
placement and timing constraints for your design, each of the RapidIO IP cores must
connect to a single Transceiver Reconfiguration Controller.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 2: Getting Started 2–11

Altera

Transceiver

Reconfiguration

Controller

0

1x RapidIO

IP Core

1x RapidIO

IP Core

Altera

Transceiver

Reconfiguration

Controller

1

reconfig_from_xcvr[N-1:0]
reconfig_to_xcvr[M-1:0]

reconfig_fromgxb[N-1:0]

reconfig_togxb[M-1:0]

reconfig_from_xcvr[N-1:0]
reconfig_to_xcvr[M-1:0]

reconfig_fromgxb[2N-1:N]

reconfig_togxb[2M-1:M]

reconfig_from_xcvr[N-1:0]
reconfig_to_xcvr[M-1:0]

reconfig_fromgxb[N-1:0]

reconfig_togxb[M-1:0]

reconfig_from_xcvr[N-1:0]
reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_from_xcvr[N-1:0]

reconfig_to_xcvr[M-1:0]

reconfig_fromgxb[2N-1:N]

reconfig_togxb[2M-1:M]

1x RapidIO

IP Core

reconfig_fromgxb[N-1:0]
reconfig_togxb[M-1:0]

reconfig_fromgxb[2N-1:N]
reconfig_togxb[2M-1:M]

4x RapidIO

IP Core

reconfig_fromgxb[5N-1:4N]
reconfig_togxb[5M-1:4M]

reconfig_fromgxb[3N-1:2N]
reconfig_togxb[3M-1:2M]

reconfig_fromgxb[4N-1:3N]
reconfig_togxb[4M-1:3M]

reconfig_fromgxb[N-1:0]
reconfig_togxb[M-1:0]

reconfig_fromgxb[2N-1:N]
reconfig_togxb[2M-1:M]

Instantiating Multiple RapidIO IP Cores

Figure 2–3 illustrates an example design with two Transceiver Reconfiguration

Controllers and four RapidIO IP cores. In the example, Altera Transceiver
Reconfiguration Controller 0 has seven reconfiguration interfaces, and Altera
Transceiver Reconfiguration Controller 1 has four reconfiguration interfaces. Each
sub-block shown in a Transceiver Reconfiguration Controller block represents a single
reconfiguration interface. The example shows only one possible configuration for this
combination of RapidIO IP cores; subject to the constraints described, you may choose
a different configuration.

Figure 2–3. Example Connections Between Two Transceiver Reconfiguration Controllers and Four RapidIO IP Cores

August 2014 Altera Corporation RapidIO MegaCore Function

Refer to Table 5–8 on page 5–4 for the values of N and M in Figure 2–3.

f Refer to the "Transceiver Reconfiguration Controller" chapter of the Altera Transceiver

PHY IP Core User Guide for more information about the Transceiver Reconfiguration

Controller interfaces and how to control dynamic reconfiguration for multiple
transceiver channels. Refer to Table 5–8 on page 5–4 for information about the

reconfig_fromgxb

to multiple Transceiver Reconfiguration Controller interfaces of the same Transceiver
Reconfiguration Controller.

To enable the Quartus II software to place distinct RapidIO IP cores in the same
Arria V, Cyclone V, or Stratix V transceiver block, you must ensure that the

phy_mgmt_clk

and

reconfig_togxb

input to each RapidIO IP core is driven by the same programming

signals that connect a single RapidIO IP core

interface clock.

User Guide

2–12 Chapter 2: Getting Started

Instantiating Multiple RapidIO IP Cores

Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations

RapidIO IP cores that target an Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV
GX device all instantiate an ALTGX transceiver megafunction to configure the device
transceivers. When your design contains multiple IP cores that use the ALTGX
megafunction, you must ensure that the
signals are connected properly.

cal_blk_clk

and

gxb_powerdown

input

You m u st e n sure that the
megafunction or user logic that uses the ALTGX megafunction) is driven by the same
calibration clock source.

When you merge multiple RapidIO IP cores in a single transceiver block, the same
signal must drive
megafunctions, IP cores, and user logic that use the ALTGX megafunction.

To successfully combine multiple high-speed transceiver channels in the same
transceiver block, they must have the same dynamic reconfiguration setting. If two IP
cores implement dynamic reconfiguration in the same transceiver block of an
Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device, the parameters or
characteristics that you want to control with the dynamic reconfiguration
megafunction instance must be identical.

To support the dynamic reconfiguration block, turn on Analog controls on the
Reconfiguration Settings tab in the transceiver parameter editor. Arria II GX,
Arria II GZ, Cyclone IV GX, and Stratix IV GX device transceivers require a dynamic
reconfiguration block, to support offset cancellation.

gxb_powerdown

cal_blk_clk

to each of the RapidIO IP core variations and other

input to each RapidIO IP core (or any other

Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances

When you instantiate multiple RapidIO IP core instances in your design, you must
modify the Synopsys Design Constraints File (.sdc) to repeat the

create_generated_clock

include the full name of the variation in the clock names.

statements for each IP core instance. The statements must

If you do not do this, the source and destination clocks each have multiple matches;
the

rxclk

and

clk_div_by_2

instances.

filters match the relevant clocks in all of the IP core

Sourcing Multiple Tcl Scripts for non-Arria 10 Variations

If you use Altera-provided Tcl scripts to specify constraints for IP cores, you must run
the Tcl script associated with each generated RapidIO IP core. For example, if a system
has

rio1

and

rio2

IP core variations, then you must source rio1_constraints.tcl,
execute the
run the
generation.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

add_rio_constraints

add_rio_constraints

command and then source rio2_constraints.tcl and

command, sequentially, from the Tcl console after

Chapter 2: Getting Started 2–13

Instantiating Multiple RapidIO IP Cores

1 After you compile the design once, you can run the

with the

-no_compile

option to suppress analysis and synthesis, and decrease

add_rio_constraints

turnaround time during development. More specifically, after you run

source rio1_constraints.tcl; add_rio_constraints

you can run

source rio2_constraints.tcl; add_rio_constraints -no_compile

command

r

r

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

2–14 Chapter 2: Getting Started

Instantiating Multiple RapidIO IP Cores

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

3. Parameter Settings

You customize the RapidIO IP core by specifying parameters in the RapidIO
parameter editor, which you access from the IP Catalog.

This chapter describes the parameters and how they affect the behavior of the IP core.

In the RapidIO parameter editor, you use the following pages from the Parameter
Settings tab to parameterize the RapidIO IP core:

■ Physical Layer

■ Transport and Maintenance

■ I/O and Doorbell

■ Capability Registers

f For information about setting simulation options, refer to the Creating a System with

Qsys chapter in volume 1 of the Quartus II Handbook.

Physical Layer Settings

The Physical Layer tab defines the characteristics of the Physical layer based on these
categories: Device Options, Data Settings, and Receive Priority Retry Threshold.

Device Options

Device Options comprise the following configuration options:

■ Mode selection

■ Transceiver selection

■ Enable transceiver dynamic reconfiguration

■ Automatically synchronize transmitted ackID

■ Send link-request reset-device on fatal errors

■ Link-request attempts

Mode Selection

Mode selection allows you to specify a 1x serial, 2x serial, or 4x serial port consisting
of one-, two-, or four-lane high-speed data serialization and deserialization.

The 2x mode is available only in variations that target an Arria V, Arria 10, Cyclone V,
or Stratix V device.

The 2x and 4x variations do not support fallback to 1x or 2x mode. You must know
whether the IP core has a 1x, 2x, or 4x link partner and configure the FPGA
accordingly. If fallback is required, the FPGA can be programmed with a 2x or 4x
variation by default and then reprogrammed to a 1x (or 2x) configuration under
system control after failure to synchronize in the original mode.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

3–2 Chapter 3: Parameter Settings

Physical Layer Settings

Transceiver Selection

The Transceiver selection parameter value is determined by the device family your IP
core targets.Although this parameter appears in the parameter editor, you cannot
modify its value.

Enable Transceiver Dynamic Reconfiguration

The Enable transceiver dynamic reconfiguration parameter allows you to specify
whether or not the Arria 10 Native PHY IP core dynamic reconfiguration interface is
available in the visible signals of the RapidIO IP core. If you do not expect to use this
interface, you can turn off this parameter to lower the number of IP core signals to
route.

This parameter is available only in IP core variations that target an Arria 10 device.

Synchronizing Transmitted ackID

The Automatically synchronize transmitted ackID option turns on support for using
an initial
first seven status control symbols it receives on the link are identical, the RapidIO IP
core uses this value as the starting
turned off, the starting

ackID

value specified by the RapidIO link partner. If the

ackID

value for packets it transmits. If this option is

ackID

value is 0.

ackID

value in the

This parameter is not available for variations that target an Arria 10 device. In Arria
10 variations, this option is turned on internally and cannot be modified.

Sending Link-Request Reset-Device on Fatal Errors

The Send link-request reset-device on fatal errors option specifies that if the
RapidIO IP core identifies a fatal error, it transmits four
with
The option is available for backward compatibility, because previous releases of the
RapidIO IP core implement this behavior.

Number of Link-Request Attempts Before Declaring Fatal Error

The Link-request attempts parameter allows you to specify the number of times the
RapidIO IP core sends a

link-request

1 through 7. The default value in a new variation is 7.

This parameter is not available for variations that target an Arria 10 device. In Arria
10 variations, this parameter is set internally to the value 7 and cannot be modified.

Data Settings

Data Settings set the Baud rate, Reference clock frequency, Receive buffer size, and
Transmit buffer size.

cmd

link-request

set to

reset-device

time-out, before declaring a fatal error. This parameter can have values

on the RapidIO link. By default, this option is turned off.

link-request reset-device

control symbol following a

control symbols

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 3: Parameter Settings 3–3

Physical Layer Settings

Baud Rate

Baud rate defines the baud rate based on the value that you specify. Table 1–7 and

Tab le 1– 8 show the baud rates supported by the RapidIO IP core for each device

family. A device family may include devices at speed grades that do not support all
the indicated baud rates. Tab le 1– 7 and Ta bl e 1 –8 provide information about the speed
grades supported for each device family, RapidIO mode, and baud rate combination.

Reference Clock Frequency

Reference clock frequency defines the frequency of the reference clock for your
RapidIO IP core internal transceiver. The RapidIO parameter editor allows you to
select any frequency supported by the transceiver.

For more information about the reference clock in high-speed transceiver blocks, and
the supported frequencies, refer to “Clocking and Reset Structure” on page 4–3.

Receive Buffer Size

Receive buffer size defines the receive buffer size in KBytes based on the value that
you specify. You can select a receive buffer size of 4, 8, 16, or 32 KBytes.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations have a Physical layer receive buffer size of 32 KBytes.

Transmit Buffer Size

Transmit buffer size defines the transmit buffer size in KBytes based on the value that
you specify. You can select a transmit buffer size of 4, 8, 16, or 32 KBytes.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations have a Physical layer transmit buffer size of 32 KBytes.

1 Buffers are implemented in embedded RAM blocks. Depending on the size of the

device used, the maximum buffer size may be limited by the number of available
RAM blocks.

Receive Priority Retry Thresholds

Retry thresholds can be set automatically by turning on Auto-configured from
receiver buffer size, or manually by specifying the thresholds for Priority 0, Priority
1, and Priority 2. To specify valid values for these priority thresholds, follow these

four guidelines:

■ Priority 2 Threshold > 9

■ Priority 1 Threshold > Priority 2 Threshold + 4

■ Priority 0 Threshold > Priority 1 Threshold + 4

■ Priority 0 Threshold < (receive buffer size x 1024/64)

Receive priority retry threshold values are numbers of 64-byte buffers. For more
information about retry thresholds, refer to “Physical Layer Receive Buffer” on

page 4–14.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

3–4 Chapter 3: Parameter Settings

Transport and Maintenance Settings

Transport and Maintenance Settings

The Transport and Maintenance tab lets you enable and configure the Transport layer
and Logical layer Input/Output Maintenance modules.

Transport Layer

All RapidIO IP core variations have a Transport layer. The Tra n s p o r t L a y e r
parameters determine whether the RapidIO IP core uses 8-bit or 16-bit device IDs,
whether the Transport layer has an Avalon-ST pass-through interface, and whether
the IP core is in promiscuous mode.

Enable 16-Bit Device ID Width

The Enable 16-bit device ID width setting specifies whether the IP core supports an
8-bit device ID width or a 16-bit device ID width. RapidIO packets contain destination
ID and source ID fields, which have the specified width. If this IP core uses 16-bit
device IDs, it supports large common transport systems.

Enable Avalon-ST Pass-Through Interface

Turn o n Enable Avalon-ST pass-through interface to include the Avalon-ST
pass-through interface in your RapidIO variation.

The Transport layer routes all unrecognized packets to the Avalon-ST pass-through
interface. Unrecognized packets are those that contain Format Types (
Logical layers not enabled in this IP core, or destination IDs not assigned to this
endpoint. However, if you disable destination ID checking, the packet is a request
packet with a supported
matches the device ID width setting of this IP core, the packet is routed to the
appropriate Logical layer.

1 The destination ID can match this endpoint only if the

the device ID width setting of the endpoint.

Request packets with a supported

ttype

, are routed to the Logical layer supporting the

following tasks:

■ An

■ An

Response packets are routed to a Logical layer module or the Avalon-ST pass-through
port based on the value of the target transaction ID field. For more information, refer
to Table 4–4 on page 4–21, which defines the transaction ID ranges.

ERROR

response can be sent to requests that require a response.

unsupported_transaction

extension registers.

ftype

, and the Transport Type (tt) field of the packet

tt

field in the packet matches

ftype

and correct tt field, but an unsupported

ftype

, which allows the

error can be recorded in the Error Management

ftypes

Destination ID Checking

Disable Destination ID checking by default lets you turn on or off the option to
route a request packet with a supported
this endpoint. The effect of this setting is detailed in the “Enable Avalon-ST Pass-

Through Interface” section.

ftype

but a destination ID not assigned to

) for

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 3: Parameter Settings 3–5

Transport and Maintenance Settings

You specify the initial value for the option in the RapidIO parameter editor, and
software can change it by modifying the value of the

Transport Control

register. Refer to Table 6–51 on page 6–24 for information about

PROMISCUOUS_MODE

bit in the

Rx

this register.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations do not check destination IDs by default. However, you can
modify the

PROMISCUOUS_MODE

setting during normal operation.

Input/Output Maintenance Logical Layer Module

The I/O Maintenance Logical Layer Module parameters specify the interface to the
Maintenance Logical layer and the number of translation windows.

Maintenance Logical Layer

Maintenance logical layer interface(s) selects which parts of the Maintenance Logical
layer to implement. You can specify any one of the following valid options:

■ Avalon-MM Master and Slave

■ Avalon-MM Master (this option is not valid in Arria 10 variations)

Port Write

■ Avalon-MM Slave (this option is not valid in Arria 10 variations)

■ None

For variations that target an Arria 10 device. RapidIO IP core, only two of the values
are valid. Arria 10 variations either include a Maintenance Logical layer module
(Avalon-MM Master and Slave) or do not include a Maintenance Logical layer
module (None).

Transmit Address Translation Windows

Number of transmit address translation windows is applicable only if you select
Avalon-MM Slave or Avalon-MM Master and Avalon-MM Slave as the
Maintenance logical layer interface(s). You can specify a value from 1 to 16 to define

the number of transmit address translation windows supported.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations that include a Maintenance Logical layer module have 16
Maintenance transmit address translation windows.

The Port Write options control whether the Maintenance Logical layer module can
transmit or receive
Maintenance Logical layer has an Avalon-MM slave port.

port-write

requests. These options are available only if the

These options are not available independently for variations that target an Arria 10
device. RapidIO IP core Arria 10 variations that include a Maintenance Logical layer
module either support both reception and transmission of
not support

August 2014 Altera Corporation RapidIO MegaCore Function

port-write

requests at all (neither reception nor transmission).

port-write

requests., or do

User Guide

3–6 Chapter 3: Parameter Settings

I/O and Doorbell Settings

Port Write Tx Enable

Port write Tx enable turns on or turns off the transmission of
the Maintenance Logical layer module.

port-write

requests by

Port Write Rx Enable

Port write Rx enable turns on or turns off the reception of
Maintenance Logical layer module.

port-write

requests by the

I/O and Doorbell Settings

This page lets you enable and configure the Input/Output and Doorbell Logical layer
modules

I/O Logical Layer Interfaces

I/O logical layer Interfaces selects whether or not to add an Avalon-MM master
interface and whether or not to add an Avalon-MM slave interface. You can specify
one of the following options:

■ Avalon-MM Master and Slave

■ Avalon-MM Master (this option is not valid in Arria 10 variations)

■ Avalon-MM Slave (this option is not valid in Arria 10 variations)

■ None

For RapidIO IP core variations that target an Arria 10 device, only two of the values
are valid. Arria 10 variations either include both an I/O Logical layer master module
and an I/O Logical layer slave module (Avalon-MM Master and Slave) or do not
include a I/O Logical layer module (None).

I/O Slave Address Width

I/O slave address width specifies the Input/Output slave address width. The default
width is 30 bits.

However, because the I/O Logical layer slave module addresses all hold word
address values in 1x variations or double-word address values in 2x and 4x variations,
the width of the external I/O Logical layer slave module address busses is the value
you specify, minus 2 in 1x variations, or the value you specify, minus 3 in 2x and 4x
variations.

I/O Read and Write Order Preservation

I/O read and write order preservation controls support for order preservation
between read and write operations (
the I/O Avalon-MM Logical layer slave module. By default this feature is turned off.

This parameter is available only if you set I/O logical layer Interfaces to Avalon-MM
Master and Slave or Avalon-MM Slave.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

NWRITE, NWRITE_R, SWRITE

, and

NREAD

requests) in

Chapter 3: Parameter Settings 3–7

I/O and Doorbell Settings

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations that include an I/O Logical layer Avalon-MM slave
module preserve transaction ordering between read and write operations in the I/O
Avalon-MM Logical layer slave module.

Whether you turn on this feature or not, as required by the Avalon-MM specification,
each individual Logical layer Avalon-MM slave module preserves response order.
Even if the responses to two requests from the same Logical layer Avalon-MM slave
module arrive in reverse order on the RapidIO link, the Logical layer module enforces
the response order on the Avalon-MM interface. The slave module enforces the order
by maintaining a queue of the Transaction IDs of transactions awaiting responses
from the RapidIO link.

For more information about the I/O read and write order preservation feature, refer
to “Input/Output Avalon-MM Slave Module” on page 4–41.

Avalon-MM Master

Number of Rx address translation windows is only applicable if you select an I/O
Avalon-MM master as an I/O Logical layer interface. You can specify a value from 1
to 16.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations that include I/O Logical layer master module have 16 Rx
address translation windows.

Avalon-MM Slave

Number of Tx address translation windows is only applicable if you select an I/O
Avalon-MM slave as an I/O Logical layer interface. You can specify a value from 1 to

16.

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations that include I/O Logical layer slave module have 16 Tx
address translation windows.

Doorbell Slave

Doorbell Tx enable controls support for the generation of outbound
messages.

Doorbell Rx enable controls support for the processing of inbound
messages. If not enabled, received
pass-through interface if it is enabled, or are silently dropped if the pass-through
interface is not enabled.

These parameters are linked for variations that target an Arria 10 device. RapidIO IP
core Arria 10 variations either support outbound and inbound
do not support
on both.

DOORBELL

DOORBELL

DOORBELL

DOORBELL

messages. If you turn on one of these options, you must turn

messages are routed to the Avalon-ST

DOORBELL

messages, or

Prevent doorbell messages from passing write transactions controls support for
preserving transaction order between
transactions. This option is available only if you turn on Doorbell Tx enable and set
I/O logical layer Interfaces to Avalon-MM Master and Slave or Avalon-MM Slave.

August 2014 Altera Corporation RapidIO MegaCore Function

DOORBELL

messages and I/O write request

User Guide

3–8 Chapter 3: Parameter Settings

This parameter is not available for variations that target an Arria 10 device. RapidIO
IP core Arria 10 variations that support
between

DOORBELL

messages and I/O write request transactions.

DOORBELL

messages preserve transaction order

Capability Registers Settings

Capability Registers Settings

The Capability Registers tab lets you set values for some of the capability registers
(CARs), which exist in every RapidIO processing element and allow an external
processing element to determine the endpoint’s capabilities through
read operations. All CARs are 32 bits wide.

1 The settings on the Capability Registers page do not cause any features to be enabled

or disabled in the RapidIO IP core. Instead, they set the values of certain bit fields in
some CARs.

Device Registers

The Device Registers options identify the device, vendor, and revision level and set
values in the
(Table 6–13 on page 6–12) CARs.

Device Identity

(Table 6–12 on page 6–11) and

Device Information

MAINTENANCE

Device ID

Device ID sets the
uniquely identifies the type of device from the vendor specified in the

Identity

1 This

confused with the

page 6–16).

field of the

DEVICE_ID

Vendor ID

Vendor ID uniquely identifies the vendor and sets the

Identity

Trade Association to your company.

register. Set Vendor ID to the identifier value assigned by the RapidIO

Revision ID

Revision ID identifies the revision level of the device. This value in the

Information

the

VENDOR_ID

Assembly Registers

The Assembly Registers options identify the vendor who manufactured the assembly
or subsystem of the device. These registers include the

on page 6–12) and the

DEVICE_ID

Device Identity

field of the

DEVICE_ID

register (Ta bl e 6 –1 3) is assigned and managed by the vendor specified in

field of the

Assembly Information

field of the

Device Identity

field in the

Device Identity

Device Identity

register.

Base Device ID

register. This option

Vendor

register (Table 6–12) should not be

CSR (Table 6–23 on

VENDOR_ID

register (Table 6–12).

Assembly Identity

(Table 6–15) CARs.

field in the

Device

(Table 6–14

Device

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 3: Parameter Settings 3–9

Capability Registers Settings

Assembly ID

Assembly ID corresponds to the
(Table 6–14), which uniquely identifies the type of assembly. This field is assigned and
managed by the vendor specified in the

Identity

register.

ASSY_ID

field of the

ASSY_VENDOR_ID

Assembly Identity

field of the

register

Assembly

Assembly Vendor ID

Assembly vendor ID uniquely identifies the vendor who manufactured the assembly.
This value corresponds to the

ASSY_VENDOR_ID

field of the

Assembly Identity

register.

Assembly Revision ID

Assembly revision ID indicates the revision level of the assembly and sets the

ASSY_REV

field of the

Assembly Information

CAR (Tab le 6– 15 ).

Extended Features Pointer

Extended features pointer points to the first entry in the extended feature list and
corresponds to the

EXT_FEATURE_PTR

in the

Assembly Informatio

n CAR.

Processing Element Features

The

Processing Element Features

features of the processing element.

Bridge Support

Bridge support, when turned on, sets the

Features

interface such as PCI Express, a proprietary processor bus such as Avalon-MM,
DRAM, or other interface.

Memory Access

Memory access, when turned on, sets the

Features

local address space that can be accessed as an endpoint through non-maintenance
operations. This local address space may be limited to local configuration registers, or
can be on-chip SRAM, or another memory device.

Processor Present

Processor present, when turned on, sets the

Features

processor such as the Nios
code. A device that bridges to an interface that connects to a processor should set the

BRIDGE

CAR and indicates that this processing element can bridge to another

CAR and indicates that the processing element has physically addressable

CAR and indicates that the processing element physically contains a local

bit—as described in “Bridge Support”—instead of the

CAR (Table 6–16 on page 6–12) identifies the major

BRIDGE

MEMORY

®

II embedded processor or similar device that executes

bit in the

bit in the

PROCESSOR

Processing Element

Processing Element

bit in the

Processing Element

PROCESSOR

bit.

Switch Support

The Switch Support options define switch support characteristics.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

3–10 Chapter 3: Parameter Settings

Capability Registers Settings

Enable Switch Support

Enable switch support, when turned on, sets the

Element Features

element can bridge to another external RapidIO interface. A processing element that
only bridges to a local endpoint is not considered a switch port.

CAR (Table 6–16 on page 6–12) and indicates that the processing

SWITCH

bit in the

Processing

Number of Ports

Number of ports specifies the total number of ports on the processing element. This
value sets the

page 6–13).

PORT_TOTAL

field of the

Switch Port Information

CAR (Table 6–17 on

Port Number

Port number sets the
value is the number of the port from which the
this register.

PORT_NUMBER

field of the

Switch Port Information

MAINTENANCE

read operation accesses

CAR. This

Data Messages

The Data Messages options indicate which, if any, data message operations are
supported by user logic attached to the pass-through interface, which you must select
on the Transport and Maintenance page.

1 Turning on one or both of Source operation and Destination operation causes

additional input ports to be added to the RapidIO IP core to support reporting of
data-message related errors through the standard Error Management Extension
registers.

For more information, refer to Chapter 5, Signals and Chapter 6, Software Interface.

Source Operation

Source operation, when turned on, sets the
CAR (Table 6–18 on page 6–14) and indicates that this endpoint can issue Data
Message request packets.

Data Message

bit in the

Source Operations

Destination Operation

Destination operation, when turned on, sets the

Operations

process received Data Message request packets.

CAR (Table 6–19 on page 6–14) and indicates that this endpoint can

Data Message

bit in the

Destination

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Interfaces

RapidIO Interface

f More detailed information about the RapidIO interface specification is available from

4. Functional Description

The Altera RapidIO IP core supports the following interfaces:

■ RapidIO Interface

■ Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces

■ Avalon Streaming (Avalon-ST) Interface

The RapidIO interface complies with revision 2.1 of the RapidIO® serial interface
standard described in the RapidIO Trade Association specifications. The protocol is
divided into a three-layer hierarchy: Physical layer, Transport layer, and Logical layer.

the RapidIO Trade Association website at www.rapidio.org.

Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces

The Avalon-MM master and slave interfaces execute transfers between the RapidIO IP
core and the system interconnect. The system interconnect allows you to use the Qsys
system integration tool to connect any master peripheral to any slave peripheral,
without detailed knowledge of either the master or slave interface. The RapidIO IP
core implements both Avalon-MM master and Avalon-MM slave interfaces.

f For more information about the Avalon-MM interface, refer to Avalon Interface

Specifications.

Avalon-MM Interface Widths in the RapidIO IP Core

The RapidIO IP core has multiple Avalon-MM interfaces. The width of the data bus
varies with the interface and with the RapidIO IP core mode.

■ I/O Logical layer master and slave interfaces have a databus width of 32 bits in 1x

variations and a databus width of 64 bits in 2x and 4x variations.

■ Maintenance module has a databus width of 32 bits.

■ Doorbell module has a databus width of 32 bits.

Avalon-MM Interface Byte Ordering

The RapidIO protocol uses big endian byte ordering, whereas Avalon-MM interfaces
use little endian byte ordering. Tab le 4– 1 shows the byte ordering for the Avalon-MM
and RapidIO interfaces.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–2 Chapter 4: Functional Description

Interfaces

No byte- or bit-order swaps occur between the Avalon-MM protocol and RapidIO
protocol, only byte- and bit-number changes. For example, RapidIO Byte0 is
Avalon-MM Byte7, and for all values of i from 0 to 63, bit i of the RapidIO 64-bit
double word[0:63] of payload is bit (63-i) of the Avalon-MM 64-bit double word[63:0].

Table 4–1. Byte Ordering

Byte
Lane

(Binary)

RapidIO

Protocol

(Big

Endian)

Avalon-

MM

Protocol

(Little

Endian)

1000_0000 0100_0000 0010_0000 0001_0000 0000_1000 0000_0100 0000_0010 0000_0001

Byte0[0:7] Byte1[0:7] Byte2[0:7] Byte3[0:7] Byte4[0:7] Byte5[0:7] Byte6[0:7] Byte7[0:7]

32-Bit Word[0:31] 32-Bit Word[0:31]

wdptr=0 wdptr=1

Double Word[0:63]

RapidIO Address N = {29'hn, 3'b000}

Byte7[7:0] Byte6[7:0] Byte5[7:0] Byte4[7:0] Byte3[7:0] Byte2[7:0] Byte1[7:0] Byte0[7:0]

Address=

N+7

Address=

N+6

32-Bit Word[31:0] 32-Bit Word[31:0]

Avalon-MM Address = N+4 Avalon-MM Address = N

Address=

N+5

Address=

N+4

64-bit Double Word0[63:0]

Avalon-MM Address = N

Address=

N+3

Address=

N+2

Address=

N+1

Address=

N

In variations of the RapidIO IP core that have 32-bit wide Avalon-MM interfaces, the
order in which the two 32-bit words in a double word appear on the Avalon-MM
interface in a burst transaction, is inverted from the order in which they appear inside
a RapidIO packet. The RapidIO 32-bit word with
of the double word at RapidIO address N, and the 32-bit word with
least significant 32-bit word at RapidIO address N. Therefore, in a burst transaction on
the Avalon-MM interface, the 32-bit word with
Avalon-MM 32-bit word at address N+4 in the Avalon-MM address space, and must
follow the 32-bit word with

wdptr=1

which corresponds to the Avalon-MM 32-bit
word at address N in the Avalon-MM address space. Thus, when a burst of two or
more 32-bit Avalon-MM words is transported in RapidIO packets, the order of the
pair of 32-bit words is inverted so that the most significant word of each pair is
transmitted or received first in the RapidIO packet.

Avalon Streaming (Avalon-ST) Interface

The Avalon-ST interface provides a standard, flexible, and modular protocol for data
transfers from a source interface to a sink interface. The Avalon-ST interface protocol
allows you to easily connect components together by supporting a direct connection
to the Transport layer. The Avalon-ST interface is either 32 or 64 bits wide depending
on the RapidIO lane width. This interface is available to create custom Logical layer
functions like message passing.

For more information about how this interface functions with the RapidIO IP core,
refer to the “Avalon-ST Pass-Through Interface” on page 4–56.

wdptr=0

wdptr=0

is the most significant half

wdptr=1

is the

corresponds to the

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–3

Clocking and Reset Structure

Clocking and Reset Structure

RapidIO IP Core Clocking

The RapidIO IP core has the following clock inputs:

■

sysclk:

■

clk:

this clock port drives only the Rx PLL.

■

cal_blk_clk: t

Cyclone IV GX, and Stratix IV GX variations only).

■

reconfig_clk: t

GZ, Cyclone IV GX, and Stratix IV GX variations only).

■

phy_mgmt_clk: t

V, and Stratix V variations only).

■

tx_bonding_clocks_chN:

transceiver channel that corresponds to RapidIO lane N (Arria 10 variations only)

Avalon system clock.

reference clock for the transceiver Tx PLL and Rx PLL. In Arria 10 variations,

ransceiver calibration-block clock (Arria II GX, Arria II GZ,

ransceiver reconfiguration interface clock (Arria II GX, Arria II

ransceiver software interface clock (Arria V, Arria V GZ, Cyclone

Arria 10 device transceiver channel clocks for the

In addition, if you turn on Enable transceiver dynamic reconfiguration for your
RapidIO Arria 10 variation, the IP core includes a

for each RapidIO lane N. Each reconfig_clk_chN clocks the

PHY dynamic reconfiguration interface for RapidIO lane

reconfig_clk_chN input clock

Arria 10 Native

N.

The RapidIO IP core provides the following clock outputs from the transceiver:

■ Transceiver receiver clock (recovered clock) (

■ Recovered data clock (

rxclk

). Recovered clock that drives the receiver modules in

rxgxbclk

)

the Physical layer.

■ Transceiver transmit-side clock (

txclk

). Main clock for the transmitter modules in

the Physical layer.

RapidIO IP core 2x and 4x variations are implemented in the transceiver TX bonded
mode. All channels of a 2x or 4x variation, on any supported device, must reside in a
single transceiver block.

To support this requirement in Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV
GX variations, the starting channel number for a 4x variation must be a multiple of
four.

When you generate a custom non-Arria 10 IP core, the
<variation name>_constraints.tcl script contains the required assignments. When you
run the script, the constraints are applied to your project.

Avalon System Clock

The Avalon system clock drives the Transport and Logical layer modules; its
frequency is nominally the same frequency as the Physical layer's internal clocks

txclk

and

rxclk

, but it can differ by up to ±50% provided the Avalon system clock

meets f

clock

August 2014 Altera Corporation RapidIO MegaCore Function

limitations. This clock is called

MAX

signal with a name of your choice.

sysclk

. Qsys allows you to export the

User Guide

4–4 Chapter 4: Functional Description

Clocking and Reset Structure

1 You must drive the Avalon system clock from a clock source that is running reliably

when the RapidIO IP core comes out of reset.

Reference Clock

The reference clock signal drives the transceiver and the Physical layer. By default,
this clock is called
signal with a name of your choice.

clk

in the generated IP core. Qsys allows you to export the

clk

The reference clock,

clk

, is the incoming reference clock for the transceiver’s PLL. The
frequency of the input clock must match the value you specify for the Reference clock
frequency parameter. The transceiver PLL converts the reference clock frequency to
the internal clock speed that supports the RapidIO IP core baud rate.

The RapidIO parameter editor lets you select one of the supported frequencies. The
selection allows you to use an existing clock in your system as the reference clock for
the RapidIO IP core.

1 You must drive the external transceiver TX PLL

same source from which you drive the RapidIO IP core

Figure 4–1 shows how the transceiver uses the reference clock in non-Arria 10

variations. In Arria 10 variations,
these variations, the reference clock for the TX PLL is an input signal to the TX PLL IP
core that you connect to the RapidIO IP core. For Arria 10 variations, refer to the Arria

10 Transceiver PHY User Guide.

Figure 4–1. Reference Clock in a non-Arria 10 RapidIO IP Core

Reference

Clock

Transceiver

Transmitter

4

td

PLL

txgxbclk

TX data

pll_refclk0

clk

is the reference clock only for the RX PLL. In

(1)

RapidIO MegaCore function

txclk

input clock from the

clk

input clock.

Avalon system clock

Serial Interfaces

rd

Note to Figure 4–1:

(1) This figure does not show the Custom PHY IP core clock

Receiver

CRU

4

PLL

rxgxbclk

RX data

phy_mgmt_clk

rxclk

.

The PLL generates the high-speed transmit clock and the input clocks to the receiver
high-speed deserializer clock and recovery unit (CRU). The CRU generates the
recovered clock (

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

rxclk

) that drives the receiver logic.

Chapter 4: Functional Description 4–5

Clocking and Reset Structure

f For more information about the supported frequencies for the reference clock in your

RapidIO variation, refer to the relevant device handbook.

Other Input Clocks

In variations that target a device for which the transceivers are configured with the
ALTGX megafunction, and not with a Transceiver PHY IP core, the transceiver's
calibration-block clock is called

cal_blk_clk

.

In Arria V, Cyclone V, and Stratix V devices, the transceiver has an additional clock,

phy_mgmt_clk

devices, the transceiver has an input clock bus

, which clocks the software interface to the transceiver. In Arria 10

tx_bonding_clocks_chN

. These clocks
should be driven by the external TX transceiver PLL. Arria 10 variations also have an
option interface, the Arria 10 Native PHY dynamic reconfiguration interface, which
includes a clock signal for each transceiver channel.

Clock Domains

The Physical layer's buffers implement clock domain crossing between the Avalon
system clock domain and the Physical layer's clock domains.

In systems created with Qsys, the system interconnect manages clock domain crossing
if some of the components of the system run on a different clock. For optimal
throughput, run all the components in the datapath on the same clock.

1 All of the clock inputs for the Logical layer modules must be connected to the same

clock source as the Avalon system clock.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–6 Chapter 4: Functional Description

Logical
Layer

Transpor t

Layer

clk

(reference clock)

Physical Layer Registers

Clock Domain

Boundary

Receiver
Transceiver

Transmitter
Transceiver

rxclk

rxgxbclk

tx_bonding_clocks_chN

(Arria 10 only)

txclk

Avalon
system

clock

(2)

S

y
s
t
e

m

I
n
t
e
r
c
o
n
n
e
c
t

phy_mgmt_clk

(Arria V, Cyclone V, Stratix V only)

reconfig_clk_chN

(Arria 10 only)

Clocking and Reset Structure

Figure 4–2 is a block diagram of the clock structure of the RapidIO IP core.

Figure 4–2. Clock Domains in RapidIO IP Core

phy_mgmt_clk

(Arria V, Cyclone V, Stratix V only)

clk

(reference clock)

Receiver
Transceiver

rxgxbclk

Transmitter
Transceiver

Notes to Figure 4–2:

(1) Clock descriptions:

phy_mgmt_clk
reconfig_clk_chN
rxclk
rxgxbclk
txclk
tx_bonding_clocks_chN

(2) The Avalon system clock is called

PHY IP core management clock (Arria V, Cyclone V, Stratix V devices only)
Arria 10 transceiver dynamic reconfiguration interface clock (Arria 10 devices only)
Receiver internal global clock (recovered clock)
Receiver transceiver clock
Transmitter internal global clock
Transmitter transceiver clock

sysclk

.

(1)

rxclk

txclk

Clock Domain

Boundary

Physical Layer Registers

Transpor t

Layer

Logical
Layer

Avalon

system

clock

(2)

S
y
s

t

e

m

I

n

t

e

r
c
o
n
n
e
c

t

Baud Rates and Clock Frequencies

The RapidIO specification specifies baud rates of 1.25, 2.5, 3.125, and 5.0 Gbaud.

Tab le 4– 2 and Ta bl e 4 –3 show the relationship between baud rates, transceiver clock

rates, and internal clock rates. For information about device family support for
different RapidIO variations, refer to Table 1–7 on page 1–10 and Table 1– 8 on

page 1–11.

Table 4–2. Clock Frequencies for 1x and 2x RapidIO IP Core Variations

rxgxbclk

1x 2x

txclk, rxclk

(MHz)

Baud Rate

(Gbaud)

Default reference

clock frequency

(1), (2)

(MHz)

1.25 62.5 62.5 31.25 31.25 15.625 31.25 46.875

2.5 125 125 62.5 62.5 31.25 62.5 93.75

3.125 156.25 156.25 78.125 78.125 39.065 78.125 117.19

5.0 250 250 125 125.0 62.50 125.0 187.50

Notes to Table 4–2:

(1) For information about the allowed reference clock frequencies, refer to “Reference Clock” on page 4–4.
(2) The reference clock is called
(3) The maximum system clock frequency might be limited by the achievable f

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

clk

.

and can vary based on the family and speed grade.

MAX

Avalon system clock (sysclk)

Minimum

(MHz)

Typical

(MHz)

Maximum

(MHz)

(3)

Chapter 4: Functional Description 4–7

Clocking and Reset Structure

Table 4–3. Clock Frequencies for 4x RapidIO IP Core Variations

Avalon System Clock (sysclk)

Typical

Maximum

(MHz)

Baud Rate

(Gbaud)

txclk, rxclk, and

default reference clock

frequency

(1)

(MHz)

rxgxbclk

Minimum (MHz)

1.25 62.5 62.5 31.25 62.5 93.75

2.5 125 125 62.5 125 187.5

3.125 156.25 156.25 78.125 156.25 234.275

5.0 250 250 125.0 250 250

Notes to Table 4–3:

(1) For information about the allowed reference clock frequencies, refer to “Reference Clock” on page 4–4.
(2) The maximum system clock frequency might be limited by the achievable f

and can vary based on the family and speed grade.

MAX

Reset for RapidIO IP Cores

The RapidIO IP core has the following reset input signals:

■

reset_n: m

■

phy_mgmt_clk_reset: t

the Custom PHY IP core included in the RapidIO Arria V, Cyclone V, or Stratix V
variation (Arria V, Cyclone V, and Stratix V variations only)

■

tx_analogreset, rx_analogreset, tx_digitalreset, rx_digitalreset

transceiver reset signals (Arria 10 variations only)

ain active-low reset signal

ransceiver software management interface signal to reset

(MHz)

:

(2)

In addition, if you turn on Enable transceiver dynamic reconfiguration for your
RapidIO Arria 10 variation, the IP core includes

reset the

RapidIO lane

an Arria 10 Native PHY dynamic reconfiguration interface for each

N

.

reconfig_reset_chN input clock to

General RapidIO Reset Signal Requirements

All reset signals can be asserted asynchronously to any clock. However, most reset
signals must be deasserted synchronously to a specific clock.

The

reset_n

Avalon system clock period and be deasserted synchronously to the rising edge of the
Avalon system clock. Figure 4–3 shows a circuit that ensures these conditions.

Figure 4–3. Circuit to Ensure Synchronous Deassertion of reset_n

input signal can be asserted asynchronously, but must last at least one

rst_n

RapidIO

IP Core

reset_n

sysclk

V

CC

rst_nrst_n

DDQ Q

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–8 Chapter 4: Functional Description

Clocking and Reset Structure

In systems generated by Qsys, this circuit is generated automatically. However, if
your RapidIO IP core variation is not generated by Qsys, you must implement logic to
ensure the minimal hold time and synchronous deassertion of the

reset_n

input

signal to the RapidIO IP core.

Reset Controller

All non-Arria 10 RapidIO IP core variations include a dedicated reset control module
to handle the specific requirements of the internal transceiver module. Arria 10
RapidIO IP core variations do not include a reset controller.

The reset control module is named

riophy_reset

. This

riophy_reset

module is

defined in the riophy_reset.v clear-text Verilog HDL source file, and is instantiated
inside the top-level module found in the clear text <variation name>_riophy_xcvr.v
Verilog HDL source file.

The

riophy_reset

module controls all of the RapidIO IP core's internal reset signals.
In particular, it generates the recommended reset sequence for the transceiver. The
reset sequence and requirements vary among device families. For details, refer to the
relevant device handbook.

Reset Requirements for Arria V, Cyclone V, and Stratix V Variations

Arria V, Cyclone V, and Stratix V variations have the following additional constraints:

■ The Custom PHY IP core

reset_n

signal must be driven from the same source, with the caveat that the

phy_mgmt_clk_reset

two reset signals must be asserted synchronously, but deasserted each according
to its corresponding clock. Figure 4–4 on page 4–9 shows a circuit that ensures the
requirements for these two reset signals are met.

■ You must ensure that the system does not deassert

phy_mgmt_clk_reset
reconfig_busy

signal is asserted. The RapidIO IP core must remain in reset until

the Transceiver Reconfiguration Controller is available.

phy_mgmt_clk_reset

signal is active high and the

signal and the RapidIO IP core

reset_n

signal is active low. The

reset_n

and

when the Altera Transceiver Reconfiguration Controller

The assertion of
Stratix V devices, the requirement that

reset_n

causes the whole IP core to reset. In Arria V, Cyclone V, and

phy_mgmt_clk_reset

be asserted with

reset_n

ensures that the PHY IP core resets with the RapidIO IP core. While the module is
held in reset, the Avalon-MM

waitrequest

outputs are driven high and all other
outputs are driven low. When the module comes out of the reset state, all buffers are
empty. Refer to Chapter 6, Software Interface for the default value of registers after
reset.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–9

Clocking and Reset Structure

In Arria V, Cyclone V, and Stratix V devices,
with

reset_n

. However, each signal is deasserted synchronously with its

phy_mgmt_clk_reset

must be asserted

corresponding clock. Figure 4–4 shows a circuit that ensures these conditions.

Figure 4–4. Circuit to Also Ensure Synchronous Assertion of phy_mgmt_clk_reset with reset_n

phy_mgmt_clk

V

CC

phy_mgmt_clk_reset

RapidIO

IP Core

reset_n

rst

sysclk

Q

DDQ

rstrst

V

CC

rst_nrst_n

DDQ Q

In systems generated by Qsys, this circuit is generated automatically. However, if
your Arria V, Cyclone V, or Stratix V RapidIO IP core variation is not generated by
Qsys, you must implement logic to ensure that

reset_n

and

phy_mgmt_clk_reset

are
driven from the same source, and that each meets the minimal hold time and
synchronous deassertion requirements.

For more information about the requirements for reset signals, refer to Chapter 5,

Signals.

Reset Requirements for Arria 10 Variations

To implement the reset sequence correctly for your RapidIO IP core configured on an
Arria 10 device, you must connect the

rx_analogreset

, and

rx_digitalreset

Controller IP core. User logic must drive the following signals from a single reset
source:

■ RapidIO IP core

■ Transceiver PHY Reset Controller

■

TX PLL mcgb_rst

reset_n

(active low) input signal.

(active high) input signal. However, Arria 10 device
requirements take precedence. Depending on the TX PLL configuration, your
design might need to drive

TX PLL mcgb_rst

User logic must connect the remaining input reset signals of the RapidIO IP core to the
corresponding output signals of the Transceiver PHY Reset Controller IP core.

f For information about the Altera Transceiver PHY Reset Controller IP core, refer to

the Arria 10 Transceiver PHY User Guide.

tx_analogreset, tx_digitalreset

,

signals to an Altera Transceiver PHY Reset

reset

(active high) input signal.

with different constraints.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–10 Chapter 4: Functional Description

Physical Layer

RapidIO IP Core Reset Behavior

Consistent with normal operation, following the IP core reset sequence, the
Initialization state machine transitions to the SILENT state.

f For details of the RapidIO Initialization state machine, refer to section 4.12 of Part 6:

LP-Serial Physical Layer Specification of the RapidIO Interconnect Specification, Revision

2.1, available at www.rapidio.org.

If two communicating RapidIO IP cores are reset one after the other, one of the IP
cores may enter the Input Error Stopped state because the other IP core is in the SILENT
state while this one is already initialized. The initialized IP core enters the Input Error
Stopped state and subsequently recovers.

Physical Layer

This section describes features and blocks of the 1x, 2x, or 4x serial Physical layer of
the RapidIO IP core. Figure 4–5 on page 4–11 shows a high-level block diagram of the
RapidIO IP core’s Physical layer.

Features

The Physical layer has the following features:

■ Port initialization

■ Transmitter and receiver with the following features:

■ One, two, or four lane high-speed data serialization and deserialization (up to

5.0 Gbaud for 1x variations with 32-bit Atlantic

interface; up to 5.0 Gbaud for

2x and 4x variations with 64-bit Atlantic interface)

■ Clock and data recovery (receiver)

■ 8B10B encoding and decoding

■ Lane synchronization (receiver)

■ Packet/control symbol assembly and delineation

■ Cyclic redundancy code (CRC) generation and checking on packets

■ Control symbol CRC-5 generation and checking

■ Error detection

■ Pseudo-random idle sequence generation

■ Idle sequence removal

■ Software interface (status/control registers)

■ Flow control (

■ Time-out on acknowledgements

■ Order of retransmission maintenance and acknowledgements

■

ackID

assignment

■

ackID

synchronization after reset

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

ackID

tracking)

Chapter 4: Functional Description 4–11

Receive

Buffer

Transmit

Buffer

Control

Receive

Buffer

Control

td

rd

tx_bonding_clocks_chN

clk

reset_n

RapidIO InterfaceRapidIO Interface

Transmit

Buffer

buf_av0

atxwl

e

vel

arxwl

e

vel

packet_transmitted

packet_cancelled

packet_accepted

packet_retry

packet_not_accepted

packet_crc_error

symbol_error

buf_av1

rxclk

atxo

vf

buf_av2
buf_av3

rx_errdetect

gxbpll_locked

char_err

cal_blk_clk or

phy_mgmt_clk_reset

reconfig_clk

reconfig_clk_chN
reconfig_reset_chN
reconfig_waitrequest_chN
reconfig_read_chN
reconfig_write_chN
reconfig_address_chN
reconfig_readdata_chN
reconfig_writedata_chN

{rx,tx}_analogreset
{rx,tx}_digitalreset
{rx,tx}_cal_busy
rx_is_lockedtodata

reconfig_togxb

reconfig_fromgxb

txclk

multicast_event_rx

multicast_event_tx

port_initialized

port_error

ef_ptr[15:0]

port_response_timeout[23:0]

Registers

master_enable

gxb_powerdown

Low Level Interface

Transmitter
Transceiver

Transmitter

Receiver

Transceiver

Receiver

Protocol and Flow Control

Engine

phy_mgmt_clk

(Arria V, Cyclone V,
Stratix V only)

To/From

Tx Transport

Layer

To/From

Rx Transport

Layer

Arria 10
dynamic
reconfiguration
interfaces

Arria 10
only

Physical Layer

■ Error management

■ Clock decoupling

■ FIFO buffer with level output port

■ Adjustable buffer sizes (4 KBytes to 32 KBytes)

■ Four transmission queues and four retransmission queues to handle packet

prioritization

■ Can be configured to send

reset-device

■ Attempts

on fatal error

link-request link-response

number of times before declaring fatal error, when a

Physical Layer Architecture

Figure 4–5 shows the architecture of the Physical layer and illustrates the interfaces

that it supports. Dotted lines indicate clock domain boundaries within the layer.

Figure 4–5. Physical Layer High Level Block Diagram

link-request

control symbols with

cmd

set to

control symbol pair a configurable

link-response

is not received

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–12 Chapter 4: Functional Description

Physical Layer

Low-level Interface Receiver

The receiver in the low-level interface receives the input from the RapidIO interface,
and performs the following tasks:

■ Separates packets and control symbols

■ Removes idle sequence characters

■ Detects

■ Detects packet-size errors

■ Checks the control symbol 5-bit CRC and asserts

multicast-event

and

stomp

control symbols

symbol_error

if the CRC is

incorrect

Receiver Transceiver

The receiver transceiver is an embedded megafunction in the Arria II GX, Arria II GZ,
Cyclone IV GX, or Stratix IV GX device, or an embedded Custom PHY IP core in the
Arria V, Cyclone V, or Stratix V device, or an embedded Arria 10 Native PHY IP core
in the Arria 10 device. The receiver transceiver implements the following process:

1. Feeds serial data from differential input pins to the CRU to detect clock and data.

2. Deserializes recovered data into 10-bit code groups.

3. Sends the code groups to the pattern detector and word-aligner block to detect
word boundaries.

4. Performs 8B10B decoding on properly aligned 10-bit code groups to convert them
to 8-bit characters.

5. Converts 8-bit characters to 16-bit or 32-bit data in the 8-to-16 or 8-to-32
demultiplexer.

CRC Checking and Removal

The RapidIO specification states that the Physical layer must add a 16-bit CRC to all
packets. The size of the packet determines how many CRCs are required.

■ For packets of 80 bytes or fewer—header and payload data included—a single

16-bit CRC is appended to the end of the packet.

■ For packets longer than 80 bytes—header and payload data included—two 16-bit

CRCs are inserted; one after the 80th transmitted byte and the other at the end of
the packet.

Two null padding bytes are appended to the packet if the resulting packet size is not
an integer multiple of four bytes.

In variations of the RapidIO IP core that include the Transport layer, the Transport
layer removes the CRC after the 80

th

byte (if present), but does not remove the final
CRC nor the padding bytes. Therefore, a packet sent to the Avalon-ST pass-through
receiver interface by the Transport layer is two or four bytes longer than the
equivalent packet received by the Transport layer from the Avalon-ST pass-through
interface. When processing the received packets, the Logical layer modules must
ignore the final CRC and padding bytes (if present). In variations of the RapidIO IP
core that include only the Physical layer, the 80

th

byte CRC of a received packet is not

removed.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–13

Physical Layer

The receiver uses the CCITT polynomial x16 + x12 + x5 + 1 to check the 16-bit CRCs that
cover all packet header bits (except the first 6 bits) and all data payload, and flags
CRC and packet size errors.

Low-Level Interface Transmitter

The transmitter in the low-level interface transmits output to the RapidIO interface.
This module performs the following tasks:

■ Assembles packets and control symbols into a proper output format

■ Generates the 5-bit CRC to cover the 19-bit symbol and appends the CRC at the

end of the symbol

■ Transmits an idle sequence during port initialization and when no packets or

control symbols are available to transmit

■ Transmits outgoing multicast-event control symbols in response to user requests

■ Transmits status control symbols and the rate compensation sequence periodically

as required by the RapidIO specification

The low-level transmitter block creates and transmits outgoing multicast-event
control symbols. Each time the
block inserts a multicast-event control symbol in the outgoing bit stream as soon as
possible.

multicast_event_tx

input signal changes value, this

In 1.25, 2.5, and 3.125 Gbaud variations, the internal transmitters are not turned off
while the initialization state machine is in the SILENT state. Instead, while in SILENT
state, the transmitters send a continuous stream of K28.5 characters, all of the same
disparity. This behavior causes the receiving end to declare numerous disparity errors
and to detect a loss of

lane_sync

In 5.0 Gbaud variations, the internal transmitters are turned off while the initialization
state machine is in the SILENT state. This behavior also causes the link partner to
detect the need to reinitialize the RapidIO link.

Transmitter Transceiver

The transmitter transceiver is an embedded megafunction in the Arria II GX,
Arria II GZ, Cyclone IV GX, or Stratix IV GX device, or an embedded Custom PHY IP
core in the Arria V, Cyclone V, or Stratix V device, or an embedded Arria 10 Native
PHY IP core in the Arria 10 device.

The transmitter transceiver implements the following process:

1. Multiplexes the 16-bit or 32-bit parallel input data to the transmitter to 8-bit data.

2. Performs 8B10B encoding on the 8-bit data to convert it to 10-bit code groups.

3. Serializes the 10-bit encoded data and sends it to differential output pins.

Protocol and Flow Control Engine

as intended by the specification.

The Physical layer protocol and flow control engine uses a sliding window protocol to
handle incoming and outgoing packets.This block performs the following tasks:

■ Monitors incoming and outgoing packet

August 2014 Altera Corporation RapidIO MegaCore Function

ackID

s to maintain proper flow

User Guide

4–14 Chapter 4: Functional Description

■ Processes incoming control symbols

■ Creates and transmits outgoing control symbols

Physical Layer

On the receiver side, this block keeps track of the sequence of

ackID

s and determines
which packets are acknowledged and which packets to retry or drop. On the
transmitter side, it keeps track of the sequence of
control block which packet to send, and sets the outgoing packets’

ackID

s, tells the transmit buffer

ackID.

It also tells
the transmit buffer control block when a packet has been acknowledged—and can
therefore be discarded from the buffers.

The Physical layer protocol and flow control engine ensures that a maximum of 31
unacknowledged packets are transmitted, and that the

ackID

s are used and

acknowledged in sequential order.

If the receiver cannot accept a packet due to buffer congestion, a
symbol with the packet’s

restart-from-retry

specified

ackID

. The RapidIO IP core supports receiver-controlled flow control in both

ackID

is sent to the transmitter. The sender then sends a

control symbol and retransmits all packets starting from the

packet-retry

control

directions.

If the receiver or the protocol and flow control block detects that an incoming packet
or control symbol is corrupted or a link protocol violation has occurred, the protocol
and flow control block enters an error recovery process. Link protocol violations
include acknowledgement time-outs based on the timers the protocol and flow
control block sets for every outgoing packet. In the case of a corrupted incoming
packet or control symbol, and some link protocol violations, the block instructs the
transmitter to send a

link-response

the sender then retransmits all packets starting from the

link-response
link-response

packet-not-accepted

symbol to the sender. A

link-request

control symbol pair is then exchanged between the link partners and

ackID

specified in the

control symbol. The transmitter attempts the

link-request

control symbol pair exchange as many times as specified by the value
N that you provided for the Link-request attempts parameter in the RapidIO
parameter editor. If the protocol and control block times out awaiting the response to
the Nth

link-request

control symbol, it declares a fatal error.

The Physical layer can retransmit any unacknowledged packet because it keeps a
copy of each transmitted packet until the packet is acknowledged with a

packet-accepted

control symbol.

When a time-out occurs for an outgoing packet, the protocol and flow control block
treats it as an unexpected acknowledge control symbol, and starts the recovery
process. If a packet is retransmitted, the time-out counter is reset.

Physical Layer Receive Buffer

The Physical layer passes data to the Transport layer through a Physical layer receive
buffer.. The data passes between the buffer and the Transport layer on a bus that is 32
bits wide in 1x variations and 64 bits wide in 2x and 4x variations.

The Physical layer receiver block accepts packet data from the low-level interface
receiver module and stores the data in its receive buffer. The receive buffer provides
clock decoupling between the Physical layer
layer

sysclk

clock domain.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

rxclk

clock domain and the Transport

Chapter 4: Functional Description 4–15

Physical Layer

You can specify a value of 4, 8, 16, or 32 KBytes to configure the receive buffer size in
non-Arria 10 variations. RapidIO Arria 10 varations have a receive buffer size of 32
KBytes. The receiver buffer is partitioned into 64-byte blocks that are allocated from a
free queue and returned to the free queue when no longer needed. The IP core
provides the current number of 64-byte blocks in the free queue in the

arxwlevel

output signal.

As many as five 64-byte blocks may be required to store a packet.

Error Conditions that Flush the Receive Buffer

The following fatal errors cause the receive buffer to be flushed and any stored
packets to be lost:

■ Receive a

■ Receive a

ackid_status

port-response

port-response

set to an

ackID

control symbol with the

control symbol with the

port_status

port_status

that is not pending (transmitted but not

set to

Error

.

set to OK but the

acknowledged yet).

■ Transmitter times out while waiting for

■ Receiver times out while waiting for

link-response

link-request

.

.

The following event also causes the receive buffer to be flushed, and any stored
packets to be lost:

■ Receive four consecutive

device

.

link-request

control symbols with the

cmd

set to

reset-

Error Conditions Flagged for the Transport Layer

The Physical layer passes data from the receive buffer to the Transport layer in 64­Kbyte blocks. The Physical layer might identify an error condition after it begins
passing a packet from the receive buffer to the Transport layer. In that case, the
Physical layer flags an Errored packet indication to the Transport layer. The Physical
layer flags an Errored packet in the following cases:

■ CRC error—when a CRC error is detected, the

for one

rxclk

clock period. If the packet size is at least 64 bytes, the Physical layer
flags the error. If the packet size is less than 64 bytes, the Physical layer identifies
and drops the errored packet before it begins sending the packet to the Transport
layer.

packet_crc_error

signal is asserted

■ Stomp—the Physical layer flags an error if it receives a s

tomp

control symbol in the

midst of a packet, causing the packet to be prematurely terminated.

■ Packet size—if a received packet exceeds the allowable size, the Physical layer cuts

it short to the maximum allowable size (276 bytes total), and flags the error.

■ Outgoing symbol buffer full—under some congestion conditions, the outgoing

symbol buffer has no space available for the

packet_accepted

control symbol. In
this case, the RapidIO IP core cannot acknowledge the packet, and the link partner
must retry transmission. The Physical layer flags an error to indicate to the
Transport layer that it should ignore the received packet because it will be retried.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–16 Chapter 4: Functional Description

■ Control symbol error —if an embedded or packet-delimiting control symbol is

Physical Layer

errored, the Physical layer flags the error. The packet in which the errored control
symbol is embedded should be retransmitted by the link partner as part of the
error recovery process.

■ Character error—if the Physical layer receives an errored character (an invalid 10-

bit code, or a character of wrong disparity) or an illegal character (any control
character other than the non-delimiting Start of Control (SC) character inside a
packet) within a packet. In this case the Physical layer flags the error and drops the
rest of the packet.

Receive Priority Threshold Values

The Physical layer implements the RapidIO specification deadlock prevention rules
by accepting or retrying packets based on three programmable threshold levels, called
Priority Threshold values. The algorithm uses the packet’s priority field value. The
block determines whether to accept or retry a packet based on its priority, the
threshold values, and the number of free blocks available in the receiver buffer, using
the following rules:

■ Packets of priority

0

(lowest priority) are retried if the number of available free

64-byte blocks is less than the Priority 0 Threshold.

■ Packets of priority

1

are retried only if the number of available free 64-byte blocks

is less than the Priority 1 Threshold.

■ Packets of priority

2

are retried only if the number of available free 64-byte blocks

is less than the Priority 2 Threshold.

■ Packets of priority

3

(highest priority) are retried only if the receiver buffer is full.

The default threshold values are:

■ Priority 2 Threshold = 10

■ Priority 1 Threshold = 15

■ Priority 0 Threshold = 20

You can specify other threshold values by turning off Auto-configured from receiver
buffer size on the Physical Layer page in the RapidIO parameter editor.

The RapidIO parameter editor enforces the following constraints to ensure the
threshold values increase monotonically by at least the maximum size of a packet
(five buffers), as required by the deadlock prevention rules:

■ Priority 2 Threshold > 9

■ Priority 1 Threshold > Priority 2 Threshold + 4

■ Priority 0 Threshold > Priority 1 Threshold + 4

■ Priority 0 Threshold < Number of available buffers

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–17

Start retrying priority 0 packets

Start retrying priority 1 packets

Priority 0 Threshold

Priority 1 Threshold

Priority 2 Threshold

Start retrying priority 2 packets

Retry priority 3 packets

Buffer Full

Physical Layer

Figure 4–6 shows sample threshold values in context to illustrate how they work

together to enforce the deadlock prevention rules.

Figure 4–6. Receiver Threshold Levels

August 2014 Altera Corporation RapidIO MegaCore Function

Physical Layer Transmit Buffer

The Physical layer accepts packet data from the Transport layer and stores it in the
transmit buffer for the RapidIO link low-level interface transmitter. The data passes
from the Transport layer to the Physical layer on a bus that is 32 bits wide in 1x
variations and 64 bits wide in 2x and 4x variations.

The transmit buffer implements the following features:

■ Provides clock decoupling between the Transport layer

the Physical layer

■ Implements the RapidIO specification requirements for packet priority handling

txclk

and deadlock avoidance, by configuring individual priority transmit and
retransmit queues.

clock domain.

sysclk

clock domain and

User Guide

4–18 Chapter 4: Functional Description

Physical Layer

The transmit buffer is the main memory in which the packets are stored before they
are transmitted. You can specify a value of 4, 8, 16, or 32 KBytes to configure the total
memory space available for the transmit buffer in non-Arria 10 variations. RapidIO
Arria 10 varations have a total transmit buffer size of 32 KBytes.

The transmit buffer space is partitioned into 64-byte blocks that are allocated from a
free queue and returned to the free queue when no longer needed. The 64-byte blocks
are used on a first-come, first-served basis by the individual transmit and retransmit
queues.

The IP core provides the current number of 64-byte blocks in the free queue in the

atxwlevel

output signal. The transmit buffer also has an output signal,

atxovf

, which

indicates a transmit buffer overflow condition.

Transmit and Retransmit Queues

To meet the RapidIO specification requirements for packet priority handling and
deadlock avoidance, the Physical layer transmit buffer implements four transmit
queues and four retransmit queues, one for each priority level.

As the Transport layer writes packets to the Physical layer, the Physical layer adds
them to the end of the appropriate priority transmit queue. The transmitter always
transmits the packet at the head of the highest priority non-empty queue. After the
packet is transmitted, the Physical layer moves the packet from the transmit queue to
the corresponding priority retransmit queue.

When a

packet-accepted

control symbol is received for a non-acknowledged
transmitted packet, the transmit buffer block removes the accepted packet from its
retransmit queue.

If a

packet-retry

control symbol is received, all of the packets in the retransmit
queues are returned to the head of the corresponding transmit queues. The
transmitter sends a

restart-from-retr

y symbol, and the transmission resumes with
the highest priority packet available, possibly not the same packet that was originally
transmitted and retried. The Transport layer might have written higher priority
packets to the Physical layer since the retried packet was originally transmitted. In
that case, the higher priority packets are chosen automatically to be transmitted before
lower priority packets are retransmitted.

The Physical layer protocol and flow control engine ensures that a maximum of 31
unacknowledged packets are transmitted, and that the

ackID

s are used and

acknowledged in ascending order.

Error Conditions that Flush the Transmit Buffer

The following fatal errors cause the transmit buffer to be flushed, and any stored
packets to be lost:

■ Receive a

■ Receive a

ackid_status

acknowledged yet).

link-response

link-response

set to an

ackID

control symbol with the

control symbol with the

port_status

port_status

that is not pending (transmitted but not

set to

Error

.

set to OK but the

■ Transmitter times out while waiting for

■ Receiver times out while waiting for

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

link-response

link-request

.

.

Chapter 4: Functional Description 4–19

Transport Layer

The following event also causes the transmit buffer to be flushed, and any stored
packets to be lost:

■ Receive four consecutive

reset-device

.

link-request

control symbols with the

cmd

set to

Forced Compensation Sequence Insertion

As packet data is written to the transmit buffer, it is stored in 64-byte blocks. To
minimize the latency introduced by the RapidIO IP core, transmission of the packet
starts as soon as the first 64-byte block is available (or the end of the packet is reached,
for packets shorter than 64 bytes). Should the next 64-byte block not be available by
the time the first one has been completely transmitted,
inserted in the middle of the packet instead of idles as the true idle sequence can be
inserted only between packets and cannot be embedded inside a packet. Embedding
these status control symbols along with other symbols, such as
symbols, causes the transmission of the packet to be stretched in time.

The RapidIO specification requires that compensation sequences be inserted every
5,000 code groups or columns, and that they be inserted only between packets. The
RapidIO IP core checks whether the 5,000 code group quota is approaching before the
transmission of every packet and inserts a compensation sequence when the number
of code groups or columns remaining before the required compensation sequence
insertion falls below a specified threshold.

The threshold is chosen to allow time for the transmission of a packet of maximum
legal size—276 bytes—even if it is stretched by the insertion of a significant number of
embedded symbols. The threshold assumes a maximum of 37 embedded symbols, or
148 bytes, which is the number of

status

control symbols that are theoretically

embedded if the traffic in the other direction consists of minimum-sized packets.

status

control symbols are

packet-accepted

Despite these precautions, in some cases—for example when using an extremely slow
Avalon system clock—the transmission of a packet can be stretched beyond the point
where a RapidIO link protocol compensation sequence must be inserted. In this case,
the packet transmission is aborted with a
sequence is inserted, and normal transmission resumes.

When the receive side receives a
provides an error indication to the Transport layer. Because the packet was
prematurely terminated at transmission, no traffic is lost and no protocol violation
occurs.

Transport Layer

The Transport layer is a required module of the RapidIO IP core. The Transport layer
is intended for use in an endpoint processing element and must be used with at least
one Logical layer module or the Avalon-ST pass-through interface.

You can optionally turn on the following two Transport layer parameters:

■ Enable Avalon-ST pass-through interface—If you turn on this parameter, the

stomp

control symbol, the compensation

stomp

control symbol in the midst of a packet, it

Transport layer routes all unrecognized packets to the Avalon-ST pass-through
interface.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–20 Chapter 4: Functional Description

Rx

Buffer

Logical Layer

Rx

scheduler

Tx

Transport

Layer

Physical Layer

Avalon-ST

Pass Through

■ Disable Destination ID checking by default—If you turn on this parameter,

Transport Layer

request packets are considered recognized even if the destination ID does not
match the value programmed in the Base Device ID CSR—Offset: 0x60. This
feature enables the RapidIO IP core to process multi-cast transactions correctly.
This parameter is turned on in RapidIO Arria 10 variations.

You can also turn on and turn off destination ID checking in the
field of the

Rx Transport Control

page 6–24).

1 The Transport layer is enabled automatically by default, and cannot be disabled.

Beginning with the RapidIO IP core v14.0 release, the RapidIO IP core no longer
supports Physical-layer only instances.

The Transport layer module is divided into receiver and transmitter submodules.

Figure 4–7 shows a block diagram of the Transport layer module.

Figure 4–7. Transport Layer Block Diagram

PROMISCUOUS_MODE

register at offset 0x10600 (Table 6–51 on

Receiver

On the receive side, the Transport layer module receives packets from the Physical
layer. Packets travel through the Rx buffer, and any errored packet is eliminated. The
Transport layer module routes the packets to one of the Logical layer modules or to
the Avalon-ST pass-through interface based on the packet's destination ID, format
type (

ftype

), and target transaction ID (

matches only if the transport type (

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

targetTID

tt

) field matches.

) header fields. The destination ID

Chapter 4: Functional Description 4–21

Transport Layer

Packets with a destination ID different from the content of the relevant Base Device ID
CSR ID field are routed to the Avalon-ST pass-through interface, unless you disable
destination ID checking and the packet is a request packet with a

tt

field that matches
the device ID width setting of the IP core. If you disable destination ID checking, the
packet is a request packet with a supported

ftype

, and the tt field matches the device
ID width setting of the current RapidIO IP core, the packet is routed to the
appropriate Logical layer.

■ Packets with unsupported

interface. Request packets with a supported
RapidIO IP core’s device ID width, but an unsupported
Logical layer supporting the

ftype

are routed to the Avalon-ST pass-through

ftype

and a tt value that matches the

ttype

are routed to the

ftype

. The Logical layer module then performs the

following tasks:

■ Sends an

■ Records an

ERROR

response for request packets that require a response.

unsupported_transaction

error in the Error Management

extension registers.

■ Packets that would be routed to the Avalon-ST pass-through interface, in the case

that the RapidIO IP core does not implement an Avalon-ST pass-through interface,
are dropped. In this case, the Transport layer module asserts the

rx_packet_dropped

■

ftype=13

response packets are routed based on the value of their target

transaction ID (

signal.

targetTID

) field. Each Logical layer module is assigned a range of
transaction IDs (Ta bl e 4 –4 specifies these ranges). If the transaction ID of a
received response packet is not within one of the ranges assigned to one of the
enabled Logical layer modules, the packet is routed to the pass-through interface.

Packets marked as errored by the Physical layer (for example, packets with a CRC
error or packets that were stomped) are filtered out and dropped from the stream of
packets sent to the Logical layer modules or pass-through interface. In these cases, the

rx_packet_dropped

output signal is not asserted.

Transaction ID Ranges

To limit the required storage, a single pool of transaction IDs is shared between all
destination IDs, although the RapidIO specification allows for independent pools for
each Source-Destination pair. Further simplifying the routing of incoming
response packets to the appropriate Logical layer module, the Input-Output
Avalon-MM slave module and the Doorbell Logical layer module are each assigned
an exclusive range of transaction IDs that no other Logical layer module can use for
transmitted request packets that expect an

ftype=13

response packet. Table 4–4 shows

the transaction ID ranges assigned to various Logical layers.

Table 4–4. Transaction ID Ranges and Assignments (Part 1 of 2)

Range Assignments

0–63

64–127

August 2014 Altera Corporation RapidIO MegaCore Function

This range of Transaction IDs is used for
Avalon-MM slave module.

ftype=13

Avalon-MM slave module.

responses in this range are reserved for exclusive use by the Input-Output Logical layer

ftype=8

responses by the Maintenance Logical layer

ftype=13

User Guide

4–22 Chapter 4: Functional Description

Table 4–4. Transaction ID Ranges and Assignments (Part 2 of 2)

Range Assignments

128–143

144–255

ftype=13

This range of Transaction IDs is currently unused and is available for use by Logical layer modules
connected to the pass-through interface.

responses in this range are reserved for exclusive use by the Doorbell Logical layer module.

Logical Layer Modules

Response packets of

ftype=13

with transaction IDs outside the 64–143 range are
routed to the Avalon-ST pass-through interface. Transaction IDs in the 0-63 range
should not be used if the Maintenance Logical layer Avalon-MM slave module is
instantiated because their use might cause the uniqueness of transaction ID rule to be
violated.

If the Input-Output Avalon-MM slave module or the Doorbell Logical layer module is
not instantiated, response packets in the corresponding Transaction IDs ranges for
these layers are routed to the Avalon-ST pass-through interface.

Transmitte r

On the transmit side, the Transport layer module uses a round-robin scheduler to
select the Logical layer module to transmit packets. The Transport layer polls the
various Logical layer modules to determine whether a packet is available. When a
packet is available, the Transport layer transmits the whole packet, and then continues
polling the next logical modules.

In a variation with a user-defined Logical layer connected to the Avalon-ST
pass-through interface, you can abort the transmission of an errored packet by
asserting the Avalon-ST pass-through interface

gen_tx_endofpacket

.

f For more information about the Transport layer, refer to Part 3: Common Transport

Specification of the RapidIO Interconnect Specification, Revision 2.1.

gen_tx_error

signal and

Logical Layer Modules

This section describes the features of the Logical layers, and how they integrate and
interact with the Transport and Physical layers to create the three-layer RapidIO
protocol. Figure 4–8 shows a high-level block diagram of the Logical layer, which
consists of the following modules:

■ Concentrator module that consolidates register access.

■ Maintenance module that initiates and terminates

■ I/O slave and master modules that initiate and terminate

and

NWRITE_R

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

transactions.

MAINTENANCE

NREAD, NWRITE, SWRITE

transactions.

,

Chapter 4: Functional Description 4–23

Logical Layer Modules

■ Doorbell module that transacts RapidIO

Figure 4–8. RapidIO IP Core Functional Block Diagram

System
Maintenance

Avalon-MM

S

Concentrator

CSRs
and
CARs

Maintenance
Master/Slave

Avalon-MM

M S

Maintenance

Logical Layer

Transport Layer

Physical Layer

Input/Output

Master

Avalon-MM

RD

WR RD

I/O Master

DOORBELL

Input/Output

Slave

Avalon-MM

RDWR

I/O Slave

messages.

Doorbell

Message

Avalon-MM

S

Doorbell

Avalon-ST

Pass-Through

Sink

SRC

Legend
S = Slave port
M = Master port
WR = Write port
RD = Read port

SRC = Source

= Dashed lines represent access to register values as sho

Concentrator Register Module

The Concentrator module provides an Avalon-MM slave interface that accesses all
configuration registers in the RapidIO IP core, including the CARs and CSRs. The
configuration registers are distributed among the implemented Logical layer modules
and the Physical layer module. Figure 4–9 shows how the Concentrator module
provides access to all the registers, which are implemented in different Logical layer
modules. The Concentrator module is automatically included when you include the
Transport layer.

RapidIO

wn in Figure 4-9

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–24 Chapter 4: Functional Description

CARs

and

CSRs

I/O Master

I/O Slave

Concentrator

Transport Layer

Physical Layer

Transport Layer

Maintenance

Avalon Slave

System Maintenance

Avalon-MM Slave

Logical Layer Modules

1 Registers in the Doorbell Logical layer module are not accessed through the

Concentrator. Instead, they are accessed directly through the Doorbell module's
Avalon-MM slave interface.

Figure 4–9. Concentrator Module Provides Configuration Register Access

The Concentrator module provides access to the Avalon-MM slave interface and the
RapidIO IP core register set. The interface supports simple reads and writes with
variable latency. Accesses are to 32-bit words addressed by a 17-bit wide byte address.
When accessed, the lower 2 bits of the address are ignored and assumed to be 0, which
aligns the transactions to 4-byte words. The interface supports an interrupt line,

sys_mnt_s_irq

. When enabled, the following interrupts assert the

sys_mnt_s_irq

signal:

■ Received port-write

■ I/O read out of bounds

■ I/O write out of bounds

■ Invalid write

■ Invalid write burstcount

For details on these and other interrupts, refer to Table 6–26 on page 6–16 and

Table 6–27 on page 6–17.

Figure 4–10 and Figure 4–11 show different ways to access the RapidIO registers.

A local host can access these registers using one of the following methods:

■ Qsys interconnect

■ Custom logic

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–25

Maintenance

Master

CARs

and

CSRs

Nios II

Processor

System Interconnect

Qsys System

I/O Master I/O Slave

Concentrator

System

Maintenance

Avalon-MM Slave

Transport Layer

Physical Layer

Transport Layer

Logical Layer Modules

A local host can access the RapidIO registers from a Qsys system as illustrated in

Figure 4–10. In this figure, a Nios II processor is part of the Qsys system and is

configured as an Avalon-MM master that accesses the RapidIO IP core registers
through the System Maintenance Avalon-MM slave. Alternatively, you can
implement custom logic to access the RapidIO registers as shown in Figure 4–11.

f For implementation details, refer to the System Design with Qsys section in volume 1 of

the Quartus II Handbook.

Figure 4–10. Local Host Accesses RapidIO Registers from a Qsys System

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–26 Chapter 4: Functional Description

Logical Layer Modules

A remote host can access the RapidIO registers by sending
targeted to this local RapidIO IP core. The Maintenance module processes

MAINTENANCE

transactions. If the transaction is a read or write, the operation is
presented on the Maintenance Avalon-MM master interface. This interface must be
routed to the System Maintenance Avalon-MM slave interface. This routing can be
done with a Qsys system shown by the routing to the Concentrator's system
Maintenance Avalon-MM slave in Figure 4–10. If you do not use a Qsys system, you
can create custom logic as shown in Figure 4–11.

Figure 4–11. Custom Logic Accesses RapidIO IP core Registers

local processor interface

Custom Logic

System

Maintenance

Avalon-MM Slave

Concentrator

Master

Maintenance

I/O Master

MAINTENANCE

I/O Slave

transactions

CARs

and

CSRs

Maintenance Module

The Maintenance module is an optional component of the I/O Logical layer. The
Maintenance module processes
transactions:

■ Type 8 –

■ Type 8 –

MAINTENANCE

Port-write

Transport Layer

Transport Layer

Physical Layer

MAINTENANCE

reads and writes

packets

transactions, including the following

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–27

Logical Layer Modules

When you create your custom RapidIO IP core variation in the parameter editor, you
have the two or four choices for this module shown in Table 4–5.

Table 4–5. Maintenance Logical Layer Interface Options

Option Use

Avalon-MM Master and
Slave

Avalon-MM Master

Avalon-MM Slave

Allows your IP core to initiate and terminate

Restricts your IP core to terminating
for Arria 10 variations.

Restricts your IP core to initiating

MAINTENANCE

Arria 10 variations.

None Prevents your IP core from initiating or terminating

MAINTENANCE

MAINTENANCE

transactions. This option is not available for

transactions.

transactions. This option is not available

MAINTENANCE

transactions.

1 If you add this module to your non-Arria 10 variation and select an Av alon-MM

Slave interface, you must also select a Number of Tx address translation windows. A

minimum of one window is required and a maximum of 16 windows are available.
Arria 10 variations have 16 Maintenance transmit address translation windows.

For more information, refer to “Input/Output Maintenance Logical Layer Module”

on page 3–5.

Figure 4–12 shows a high-level block diagram of the Maintenance module and the

interfaces to other supporting modules. The Maintenance module can be segmented
into the following four major submodules:

■ Maintenance register

■ Maintenance slave processor

■ Maintenance master processor

■ Port-write processor

The following interfaces are supported:

■ Avalon-MM slave interface—User-exposed interface

■ Avalon-MM master interface—User-exposed interface

■ Tx interface—Internal interface used to communicate with the Transport layer

■ Rx interface—Internal interface used to communicate with the Transport layer

■ Register interface—Internal interface used to communicate with the Concentrator

Module

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–28 Chapter 4: Functional Description

Logical Layer Modules

Figure 4–12. Maintenance Module Block Diagram

System Maintenance

Avalon-MM Slave Interface

Avalon-MM

Slave

Concentrator

Register
Interface

Maintenance

Avalon-MM Slave

Interface

Avalon-MM

Slave

slave

processor

maintenance

register

Tx Interface

Maintenance

Avalon-MM Master

Interface

Avalon-MM

Master

master

processor

Rx Interface

Transport Layer

port_write

processor

Maintenance Register

The Maintenance Register module implements all of the control and status registers
required by this module to perform its functions. These include registers described in

Table 6–26 on page 6–16 through Table 6–32 on page 6–18. These registers are

accessible through the System Maintenance Avalon-MM interface.

Maintenance Slave Processor

The Maintenance Slave Processor module performs the following tasks:

■ For an Avalon read, composes the RapidIO logical header fields of a

read request packet

■ For an Avalon write, composes the RapidIO logical header fields of a

write request packet

■ Maintains status related to the composed

■ Presents the composed

MAINTENANCE

The Avalon-MM slave interface allows you to initiate a

MAINTENANCE

packet

packet to the Transport layer for transmission

MAINTENANCE

operation. The Avalon-MM slave interface supports the following Avalon transfers:

■ Single slave write transfer with variable wait-states

■ Pipelined read transfers with variable latency

1 At any time, there can be a maximum of 64 outstanding

be

MAINTENANCE

reads,

MAINTENANCE

writes, or

port-write

MAINTENANCE

requests.

f Refer to the Avalon Interface Specifications for more details on the supported transfers.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

MAINTENANCE

MAINTENANCE

read or write

requests that can

Chapter 4: Functional Description 4–29

mnt_s_chipselect

mnt_s_read

mnt_s_address

mnt_s_readdata

mnt_s_readerror

0x14 0x4C

system clock

mnt_s_readdatavalid

mnt_s_waitrequest

Logical Layer Modules

Figure 4–13 shows the signal relationships for four write transfers on the Avalon-MM

slave interface.

Figure 4–13. Write Transfers on the Avalon-MM Slave Interface

sysclk

mnt_s_chipselect

mnt_s_waitrequest

mnt_s_write

mnt_s_address

mnt_s_writedata

0x4 0x8 0xC 0x10

32’hACACACAC 32’h5C5C5C5C 32’hBEEFBEEF 32’hFACEFACE

Figure 4–14 shows the signal relationships for two read transfers on the Avalon-MM

interface.

Figure 4–14. Read Transfers on the Avalon-MM Slave Interface

Reads and writes on the Avalon-MM slave interface are converted to RapidIO
maintenance reads and writes. The following fields of a

MAINTENANCE

type packet are

assigned by the Maintenance module:

■

prio

■

tt

■

ftype

■

dest_id

■

src_id

■

ttype

■

rdsize/wrsize

is assigned a value of

is assigned a value of

field is fixed at

4'b1000

4'b0000

4'b1000

for reads and a value of

4'b0001

for writes

, because only 4-byte reads and writes are

supported

■

source_tid

■

hop_count

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–30 Chapter 4: Functional Description

■

config_offset
Maintenance Address Translation Window

is generated by using the values programmed in the Tx

registers, as described in Table 6–28

Logical Layer Modules

through Table 6–35.

■

wdptr

Each window is enabled if the window enable (

n

Mask

register (Table 6–30 on page 6–18) is set. Each window is defined by the

WEN

) bit of the

Tx Maintenance Window

following registers:

■ A base register:

■ A mask register:

■ An offset register:

■ A control register:

Tx Maintenance Mapping Window

Tx Maintenance Mapping Window

Tx Maintenance Mapping Window

Tx Maintenance Mapping Window

n

n

Base

(Table 6–29 on page 6–18)

Mask

(Table 6–30)

n

Offset

n

Control

(Table 6–31)

(Table 6–32)

For each defined and enabled window, the Avalon-MM address's least significant bits
are masked out by the window mask and the resulting address is compared to the
window base. If the addresses match,

config_offset

is created based on the

following equation:

If

(mnt_s_address[23:1] & mask[25:3]) == base[25:3]

then

config_offset = (offset[23:3] & mask[23:3])

(mnt_s_address[21:1] &

~mask

|

[23:3])

where:

■

mnt_s_address[23:0]

■

config_offset[20:0]

■

base[31:0]

■

mask[31:0]

is the base address register

is the mask register

is the Avalon-MM slave interface address

is the outgoing RapidIO register double-word offset

■

offset[23:0]

is the window offset register

If the address matches multiple windows, the lowest number window register set is
used.

The following fields are inserted from the control register of the mapping window
that matches.

■

prio

■

dest_id

■

hop_count

The tt value is determined by your selection of device ID width at the time you create
this RapidIO IP core variation. The
is assigned the negation of

For a

MAINTENANCE

Avalon-MM slave write, the value on the

bus is inserted in the

mnt_s_address[0]

payload

source_tid

field of the

is generated internally and the

.

mnt_s_writedata[31:0]

MAINTENANCE

write packet.

wdptr

Maintenance Master Processor

This module performs the following tasks:

■ For a

MAINTENANCE

read, converts the received request packet to an Avalon read

and presents it across the Maintenance Avalon-MM master interface.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–31

mnt_m_read

mnt_m_address

mnt_m_readdatavalid

mnt_m_readdata

system clock

0x10

0x14

0x18

mnt_m_waitrequest

Logical Layer Modules

■ For a

MAINTENANCE

write, converts the received request packet to an Avalon write

and presents it across the Maintenance Avalon-MM master interface.

■ Performs accounting related to the received RapidIO

operation.

■ For each

MAINTENANCE

request packet received from remote endpoints, generates a

Type 8 Response packet and presents it to the Transport layer for transmission.

The Avalon-MM master interface supports the following Avalon transfers:

■ Single master write transfer

■ Pipelined master read transfers

f Refer to Avalon Interface Specifications for details on the supported transfers.

Figure 4–15 shows the signal relationships for a sequence of four write transfers on

the Maintenance Avalon-MM master interface.

Figure 4–15. Write Transfers on the Maintenance Avalon-MM Master Interface

sysclk

mnt_m_waitrequest

mnt_m_write

mnt_m_address

mnt_m_writedata

4 8 C 10

ACACACAC 5C5C5C5C BEEFBEEF FACEFACE

MAINTENANCE

read or write

Figure 4–16 shows the signal relationships for a sequence of three read requests

presented on the Maintenance Avalon-MM master interface.

Figure 4–16. Timing of a Read Request on the Maintenance Avalon-MM Master Interface

When a

MAINTENANCE

packet is received from a remote device, it is first processed by
the Physical layer. After the Physical layer processes the packet, it is sent to the
Transport layer. The Maintenance module receives the packet on the Rx interface. The
Maintenance module extracts the fields of the packet header and uses them to
compose the read or write transfer on the Maintenance Avalon-MM master interface.
The following packet header fields are extracted:

■

ttype

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–32 Chapter 4: Functional Description

■

rdsize/wrsize

■

wdptr

■

config_offset

■

payload

Logical Layer Modules

The Maintenance module only supports single 32-bit word transfers, that is,
and

wrsize = 4’b1000

The

wdptr

and

; other values cause an error response packet to be sent.

config_offset

values are used to generate the Avalon-MM address.

rdsize

The following expression is used to derive the address:

mnt_m_address = {rx_base, config_offset, wdptr, 2'b00}

where

rx_base

is the value programmed in the

Rx Maintenance Mapping

register at

location 0x10088 (Table 6–28 on page 6–17).

The

payload

is presented on the

mnt_m_writedata[31:0]

bus.

Port-Write Processor

The port-write processor performs the following tasks:

■ Composes the RapidIO logical header of a

packet.

■ Presents the port-write request packet to the Transport layer for transmission.

■ Processes port-write request packets received from a remote device.

■ Alerts the user of a received port-write using the

The port-write processor is controlled through the use of the registers that are
described in the following sections:

MAINTENANCE port-write

sys_mnt_s_irq

signal.

request

■ “Transmit Port-Write Registers” on page 6–18

■ “Receive Port-Write Registers” on page 6–19

Port-Write Transmission

To send a port-write to a remote device, you must program the transmit port-write
control and data registers. The

Table 6–33 on page 6–19 and the

Tx Port Write Control

Tx Port Write Buffer

register is described in

is described in Table 6–35 on

page 6–19. These registers are accessed using the System Maintenance Avalon-MM

slave interface. The following header fields are supplied by the values stored at the

Port Write Control

■

DESTINATION_ID

■

priority

■

wrsize

The other fields of the

ftype

is assigned a value of

4'b0100

. The

the size of the

Control

register. The

wdptr

payload

register:

MAINTENANCE port-write

and

4'b1000

wrsize

and the

fields of the transmitted packet are calculated from

to be sent as defined by the

source_tid

and

config_offset

packet are assigned as follows. The

ttype

field is assigned a value of

size

field of the Tx

Port Write

are reserved and set to zero.

Tx

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–33

Logical Layer Modules

The

payload

is written to a Tx

Port Write Buffer

starting at address

0x10210

. This
buffer can store a maximum of 64 bytes. The port-write processor starts the packet
composition and transmission process after the

Control

register is set. The composed

Maintenance port-write

PACKET_READY

bit in the Tx

Port Write

packet is sent to the

Transport layer for transmission.

Port-Write Reception

The Maintenance module receives a
from the Transport layer. The port-write processor handles
a

ttype

value set to

4'b0100

. The port-write processor extracts the following fields

from the packet header and uses them to write the appropriate content to registers

Port Write Control

(Table 6–36 on page 6–19) through Rx

MAINTENANCE

packet on the Rx Atlantic interface

MAINTENANCE

packets with

Rx

Port Write Buffer

(Table 6–38 on page 6–20):

■

wrsize

■

wdptr

■

payload

The

wrsize
Port Write Status
Rx Port Write Buffer

written. While the

Port Write Status

to the buffer, the interrupt signal

and the

wdptr

determine the value of the

PAYLOAD_SIZE

register (Table 6–37 on page 6–20). The

starting at address

payload

is written to the buffer, the

register remains asserted. After the

sys_mnt_s_irq

0x10260

. A maximum of 64 bytes can be

PORT_WRITE_BUSY

payload

is asserted by the Concentrator on

field in the

payload

is written to the

bit of the Rx

is completely written

Rx

behalf of the Port Write Processor. The interrupt is asserted only if the

RX_PACKET_STORED

bit of the

Maintenance Interrupt Enable

register (Table 6–27 on

page 6–17) is set.

Maintenance Module Error Handling

The

Maintenance Interrupt
Enable

register (at

0x10084

error handling and reporting for

register (at

), described in Table 6–26 and Table 6–27, determine the

MAINTENANCE

The following errors can also occur for

■ A

MAINTENANCE

PKT_RSP_TIMEOUT

read or

MAINTENANCE

interrupt (bit 24 of the
CSR, described in Table 6–52 on page 6–24) is generated if a response packet is not
received within the time specified by the
register (Table 6–7 on page 6–6).

■ The

IO_ERROR_RSP

when an

(bit 31 of the

ERROR

response is received for a transmitted

For information about how the time-out value is calculated, refer to Table 6–7 on

page 6–6.

For more information about the error management registers, refer to Table 6–52 on

page 6–24.

Input/Output Logical Layer Modules

This section describes the following Input/Output Logical layer modules:

0x10080

) and the

Maintenance Interrupt

packets.

MAINTENANCE

packets:

write request time-out occurs and a

Logical/Transport Layer Error Detect

Port Response Time-Out Control

Logical/Transport Layer Error Detect

MAINTENANCE

packet.

CSR) is set

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–34 Chapter 4: Functional Description

Transport Side

TX

Interface

32 or 64 bits

Transport Side

RX

Interface

32 or 64 bits

Tx

Sink

Source

Read

Master

Write

Master

io_m_rd_readdata

io_m_rd_readdatavalid

io_m_rd_read

io_m_rd_waitrequest

io_m_rd_address

io_m_rd_burstcount

io_m_rd_readerror

io_m_wr_wr itedata

io_m_wr_write

io_m_wr_waitrequest

io_m_wr_address

io_m_wr_burstcount

io_m_wr_ byteenable

Rx

Datapath Read
Avalon-MM Interface
32 or 64 bits

Datapath Write
Avalon-MM Interface
32 or 64 bits

■ “Input/Output Avalon-MM Master Module”

■ “Input/Output Avalon-MM Slave Module” on page 4–41

Logical Layer Modules

Input/Output Avalon-MM Master Module

The Input/Output (I/O) Avalon-MM master Logical layer module receives RapidIO
read and write request packets from a remote endpoint through the Transport layer
module. The I/O Avalon-MM master module translates the request packets into
Avalon-MM transactions, and creates and returns RapidIO response packets to the
source of the request through the Transport layer. Figure 4–17 shows a block diagram
of the I/O Avalon-MM master Logical module and its interfaces.

1 The I/O Avalon-MM master module is referred to as a master module because it is an

Avalon-MM interface master.

To maintain full-duplex bandwidth, two independent Avalon-MM interfaces are used
in the I/O master module—one for read transactions and one for write transactions.

The I/O Avalon-MM master module can process a mix of as many as seven

NWRITE_R
NWRITE_R

requests simultaneously. If the Transport layer module receives an

request packet while seven requests are already pending in the I/O
Avalon-MM master module, the new packet remains in the Transport layer until one
of the pending transactions completes.

Figure 4–17. I/O Master Block Diagram

NREAD

NREAD

or

or

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–35

Logical Layer Modules

Input/Output Avalon-MM Master Address Mapping Windows

Address mapping or translation windows are used to map windows of 34-bit
RapidIO addresses into windows of 32-bit Avalon-MM addresses. Tab le 4 –6 lists the
registers used for address translation.

Table 4–6. Address Translation Registers

Registers Location

Input/Output master base address Table 6–39 on page 6–20

Input/Output master address mask Table 6–40 on page 6–20

Input/Output master address offset Table 6–41 on page 6–21

Your variation must have at least one translation window. Arria 10 variations have 16
address translation windows. You can change the values of the window defining
registers at any time. You should disable a window before changing its window
defining registers.

A window is enabled if the window enable (

Window n Mask

register is set.

WEN)

bit of the

I/O Master Mapping

The number of mapping windows is defined by the Number of receive address
translation windows parameter, which supports up to 16 sets of registers. Each set of

registers supports one address mapping window.

For each window that is defined and enabled, the least significant bits of the incoming
RapidIO address are masked out by the window mask and the resulting address is
compared to the window base. If the addresses match, the Avalon-MM address is
made of the least significant bits of the RapidIO address and the window offset using
the following equation:

Let

rio_addr[33:0]

be the 34-bit RapidIO address, and

address[31:0]

the local

Avalon-MM address.

Let

base[31:0], mask[31:0]

registers. The least significant three bits of these registers are always

Starting from window

((rio_addr & {xamm, mask}) ==

xamm

and

xamb

where

Window

let

n

Mask

address[31:3] = (offset[31:3] & mask[31:3]) |

(rio_addr[31:3]

are the

and the

&

~mask[31:3])

and

offset[31:0]

0

, for the first window in which

({

xamb, base} & {xamm, mask})

Extended Address MSB

be the three window-defining

fields of the

I/O Master Mapping Window n Base

3’b000

.

,

I/O Master Mapping

registers, respectively,

The value of

address[2]

is zero for variations with 64-bit wide datapath Avalon-MM

interfaces.

The value of

address[2]

is determined by the values of

wdptr

and

rdsize

or

wrsize

for variations with 32-bit wide datapath Avalon-MM interfaces.

The value of

For each received
window, an

August 2014 Altera Corporation RapidIO MegaCore Function

address[1:0]

NREAD

ERROR

response packet is returned.

is always zero.

or

NWRITE_R

request packet that does not match any enabled

User Guide

4–36 Chapter 4: Functional Description

Logical Layer Modules

Figure 4–18 shows a block diagram of the I/O master‘s window translation.

Figure 4–18. I/O Master Window Translation

RapidIO

Address Space

0x3FFFFFFF8

Window

Base

Avalon-MM

Address Space

0xFFFFFFF8

Offset

0x00000000

023

023

RapidIO Address

Initial

Window Base

Window Mask

Window Offset

Resulting

Avalon-MM Address

0x000000000

31

33

XAMB

XAMM

11111111.........................11

31

(1)

(1)

Window Size

Don’t Care

000000000000000..............00

Don’t Care

Note to Figure 4–18:

(1) These bits must have the same value in the initial RapidIO address and in the window base.

RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions

The RapidIO IP core converts RapidIO packets to Avalon-MM transactions. The
RapidIO packets’ read size, write size, and word pointer fields are translated to the
Avalon-MM burst count and byteenable values.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–37

Logical Layer Modules

For information about the burst count values determined in the conversion process
for read transactions, refer to Ta bl e 4 –7 . For information about the burst count and
byteenable values determined in the conversion process for 32-bit datapath write
transactions, by RapidIO IP core 1x variations, refer to Ta bl e 4 –8 . For information
about the burst count and byteenable values determined in the conversion process for
64-bit datapath write transactions, by RapidIO IP core 2x and 4x variations, refer to

Tab le 4 –9 .

Table 4–7. Avalon-MM I/O Master Read Transaction Burstcount (32-bit or 64-bit datapath)

RapidIO Values Avalon-MM Burstcount Value

rdsize

'

(4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

bxxxx)

wdptr

(1'bx)

in 32-Bit Datapath In 64-Bit Datapath

011
111
011
111
011
111
011
111
011
111
011
111
011
111
021
121
011
111
021
121
021
121
021
142
084
1168
02412
13216
04020
14824
05628
16432

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–38 Chapter 4: Functional Description

Logical Layer Modules

Tab le 4 –8 lists the allowed write-request conversions for RapidIO IP core 1x

variations.

Table 4–8. RapidIO Master Write Transaction Burstcount and Byteenable (32-Bit Datapath)

RapidIO Values Avalon-MM Values

Byteenable (8’b0000xxxx)

wrsize

(4

'

bxxxx)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Notes to Table 4–8:

(1) If the maximum burst count is larger than 2, the actual burst count depends on the size of the payload in the

received request packet.

(2) This combination of

allowed by the Avalon-MM specification.

(3) This combination of

declares an error.

wdptr

(1'bx)

Maximum

Burstcount

(1)

First Cycle

or

All Cycles

0 1 1000 —
1 1 1000 —
0 1 0100 —
1 1 0100 —
0 1 0010 —
1 1 0010 —
0 1 0001 —
1 1 0001 —
0 1 1100 —
1 1 1100 —

(2)

0

(2)

1

1 1110 —

1 0111 —
0 1 0011 —
1 1 0011 —
0 2 1000 1111
1 2 1111 0001
0 1 1111 —
1 1 1111 —
0 2 1100 1111
1 2 1111 0011

(2)

0

(2)

1

2 1110 1111

2 1111 0111
0 2 1111 1111
1 4 1111 —
0 8 1111 —
1 16 1111 —

(3)

0

—— —

1 32 1111 —

(3)

0

(3)

1

(3)

0

—— —
—— —
—— —

1 64 1111 —

wdptr

and

wrsize

values should be avoided, because the resulting byteenable value is not

wdptr

and

wrsize

values is reserved. If this combination is received, the RapidIO IP core

Second Cycle

(If Different)

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–39

Logical Layer Modules

Tab le 4 –9 lists the allowed write-request conversions for RapidIO IP core 2x and 4x

variations.

Table 4–9. RapidIO Master Write Transaction Burstcount and Byteenable (64-Bit Datapath)

RapidIO Values Avalon-MM Values

wrsize

'

bxxxx)

(4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Notes to Table 4–9:

(1) If the maximum burst count is larger than 2, the actual burst count depends on the size of the payload in the

received request packet.

(2) This combination of

allowed by the Avalon-MM specification.

(3) This combination of

declares an error.

wdptr

wdptr

wdptr

(1'bx)

0 1 1000_0000
1 1 0000_1000
0 1 0100_0000
1 1 0000_0100
0 1 0010_0000
1 1 0000_0010
0 1 0001_0000
1 1 0000_0001
0 1 1100_0000
1 1 0000_1100

(2)

0

(2)

1
0 1 0011_0000
1 1 0000_0011

(2)

0

(2)

1
0 1 1111_0000
1 1 0000_1111

(2)

0

(2)

1

(2)

0

(2)

1
0 1 1111_1111
1 2 1111_1111
0 4 1111_1111
1 8 1111_1111

(3)

0
1 16 1111_1111

(3)

0

(3)

1

(3)

0
1 32 1111_1111

and

wrsize

values should be avoided, because the resulting byteenable value is not

and

wrsize

values is reserved. If this combination is received, the RapidIO IP core

Maximum

Burstcount

(1)

Byteenable (8’bxxxxxxxx)

1 1110_0000
1 0000_0111

1 1111_1000
1 0001_1111

1 1111_1100
1 0011_1111
1 1111_1110
1 0111_1111

——

——
——
——

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–40 Chapter 4: Functional Description

sysclk

io_m_rd_waitrequest

io_m_rd_read

io_m_rd_address[31:0]

io_m_rd_readdatavalid

io_m_rd_readerror

io_m_rd_readdata[31:0]

io_m_rd_burstcount[7:0]

00000000

Adr0

Adr1

r0 r1 r2

00

01 02

sysclk

io_m_wr_waitrequest

io_m_wr_write

io_m_wr_address[31:0]

io_m_wr_writedata[31:0]

io_m_wr_byteenable[3:0]

io_m_wr_burstcount[7:0]

AdrA AdrB

w1 w2 w3 w4 w5w0

F

02 04

Logical Layer Modules

Input/Output Avalon-MM Master Module Timing Diagrams

Figure 4–19 shows the timing dependencies on the Avalon-MM master interface for

an incoming RapidIO
on the Avalon-MM master interface for an incoming RapidIO

Both transaction requests are received on the RapidIO link and sent on to the Logical
layer Avalon-MM master module. If the RapidIO link partner is also an Altera
RapidIO IP core, the timing diagrams in “Input/Output Avalon-MM Slave Module

Timing Diagrams” on page 4–52 show the same transactions as they originate on the

Avalon-MM interface of the RapidIO link partner’s Input/Output Avalon-MM slave
module.

Figure 4–19. NREAD Transaction on the Input/Output Avalon-MM Master Interface

NREAD

transaction. Figure 4–20 shows the timing dependencies

NWRITE

transaction.

Figure 4–20. NWRITE Transaction on the Input/Output Avalon-MM Master Interface

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–41

Logical Layer Modules

Input/Output Avalon-MM Slave Module

The I/O Avalon-MM slave Logical layer module transforms Avalon-MM transactions
to RapidIO read and write request packets that are sent through the Transport and
Physical layer modules to a remote RapidIO processing element where the actual read
or write transactions occur and from which response packets are sent back when
required. Avalon-MM read transactions complete when the corresponding response
packet is received. Figure 4–21 on page 4–42 shows a block diagram of the I/O
Avalon-MM Logical layer slave module and its interfaces.

1 The I/O Avalon-MM slave module is referred to as a slave module because it is an

Avalon-MM interface slave.

1 The maximum number of outstanding transactions (I/O Requests) supported is 26 (14

read requests + 12 write requests).

To maintain full-duplex bandwidth, two independent Avalon-MM interfaces are used
in the I/O slave module—one for read transactions and one for write transactions.

When the read Avalon-MM slave creates a read request packet, the request is sent to
both the Pending Reads buffer to wait for the corresponding response packet, and to
the read request transmit buffer to be sent to the remote processing element through
the Transport layer. When the read response is received, the packet’s payload is used
to complete the read transaction on the read Avalon-MM slave.

For a read operation, one of the following responses occurs:

■ The read was successful. After a response packet is received, the read response

and data are passed from the Pending Reads buffer back through the read
Avalon-MM slave interface.

■ The remote processing element is busy and the request packet is resent.

■ An error or time-out occurs, which causes

io_s_rd_readerror

to be asserted on
the read Avalon-MM slave interface and some information to be captured in the
Error Management Extension registers.

How the write request is handled depends on the type of write request sent. For
example, unlike a read request, not all write requests send tracking information to the
Pending Writes buffer.
information to the Pending Writes buffer. Only write requests such as

NWRITE

and

SWRITE

requests do not send write tracking

NWRITE_R

, that
require a response, are sent to both the Pending Writes and Transmit buffers. Write
requests are sent through the Transport and Physical layers to the remote processing
element.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–42 Chapter 4: Functional Description

Data Path

Read

Avalon-MM Bus

32 of 64 bits

Pending Reads

Pending Writes

Read

Avalon-MM Slave

Write

Avalon-MM Slave

Read Request

Buffer

Write Request

Buffer

Tx Interface

From

Transport

Layer

To

Transport

Layer

Sink

Source

Data Path

Write

Avalon-MM Bus

32 of 64 bits

io_s_rd_read
io_s_rd_readdatavalid
io_s_rd_readdata
io_s_rd_address
io_s_rd_burstcount
io_s_rd_readerror
io_s_rd_waitrequest

io_s_wr_write
io_s_wr_writedata
io_s_wr_byteenable
io_s_wr_address
io_s_wr_burstcount
io_s_wr_waitrequest
io_s_wr_chipselect

io_s_rd_chipselect

Logical Layer Modules

An outbound request that requires a response—an
transaction—is assigned a time-out value that is the sum of the

Response Time-Out Control

register (Table 6–7 on page 6–6) and the current value of
a free-running counter. When the counter reaches the time-out value, if the transaction
has not yet received a response, the transaction times out. Refer to Table 6–7 for
information about the duration of the time-out.

Figure 4–21. Input/Output Avalon-MM Slave Logical Layer Block Diagram

NWRITE_R

or an

VALUE

NREAD

field of the

Port

If you turn off the I/O read and write order preservation option in the RapidIO
parameter editor, if a read and a write request arrive simultaneously or one clock
cycle apart on the Avalon-MM interfaces, the order of transaction completion is
undefined. However, if you turn on the I/O read and write order preservation option,
the read requests buffer and the write requests buffer shown in Figure 4–21 are
combined, to preserve the relative order of read and write requests that appear on the
Avalon-MM interface. In Arria 10 variations, the read and write request buffers are
combined.

Keeping Track of I/O Write Transactions

The following three registers are available to software to keep track of I/O write
transactions:

■ The

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Input/Output Slave Avalon-MM Write Transactions

Table 6–49 on page 6–23 holds a count of the write transactions that have been

initiated on the write Avalon-MM slave interface.

register described in

Chapter 4: Functional Description 4–43

Logical Layer Modules

■ The

Input/Output Slave RapidIO Write Requests

register described in

Table 6–50 on page 6–24 holds a count of the RapidIO write request packets that

have been transferred to the Transport layer.

■ The

Input/Output Slave Pending NWRITE_R Transactions

Table 6–48 on page 6–23 holds a count of the

NWRITE_R

register described in

requests that have been

issued but have not yet completed.

In addition, the

Enable

register described in Table 6–47 on page 6–23 controls a maskable interrupt in

the

Input/Output Slave Interrupt

can be generated when the final pending

NWRITE_RS_COMPLETED

register described in Table 6–46 on page 6–22 that

bit of the

NWRITE_R

Input/Output Slave Interrupt

transaction completes.

You can use these registers to determine if a specific I/O write transaction has been
issued or if a response has been received for any or all issued

NWRITE_R

requests.

Input/Output Avalon-MM Slave Address Mapping Windows

Address mapping or translation windows map windows of 32-bit Avalon-MM
addresses to windows of 34-bit RapidIO addresses, and are defined by sets of the
32-bit registers in Tab le 4 –1 0.

Table 4–10. Address Mapping and Translation Registers

Registers Location

Input/Output slave base address Table 6–42 on page 6–21

Input/Output slave address mask Table 6–43 on page 6–21

Input/Output slave address offset Table 6–44 on page 6–21

Input/Output slave packet control information
(for packet header)

Table 6–45 on page 6–22

A base register, a mask register, and an offset register define a window. The control
register stores information used to prepare the packet header on the RapidIO side of
the transaction, including the target device’s destination ID, the request packet's
priority, and selects between the three available write request packet types:

NWRITE_R

and

SWRITE

. Figure 4–22 on page 4–45 illustrates this address mapping.

NWRITE

,

You can change the values of the window-defining registers at any time, even after
sending a request packet and before receiving its response packet. However, you
should disable a window before changing its window-defining registers. A window is
enabled if the window enable (

Mask

register is set, where n is the number of the transmit address translation window.

WEN)

bit of the

Input/Output Slave Mapping Window

n

The number of mapping windows is defined by the parameter Number of transmit
address translation windows; up to 16 windows are supported. Each set of registers
supports one external host or entity at a time. Your variation must have at least one
translation window. Arria 10 variations have 16 transmit address translation
windows.

For each window that is enabled, the least significant bits of the Avalon-MM address
are masked out by the window mask and the resulting address is compared to the
window base. If the addresses match, the RapidIO address in the outgoing request
packet is made of the least significant bits of the Avalon-MM address and the window
offset using the following equation:

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–44 Chapter 4: Functional Description

Let

avalon_address[31:0]

the RapidIO address, in which

rio_addr[31:3]

is the 29-bit wide

implicitly defined by

Let

base[31:0], mask[31:0]

be the 32-bit Avalon-MM address, and

wdptr

rio_addr[33:32]

address

and

rdsize

, and

or

offset[31:0]

is the 2-bit wide

field in the packet, and

wrsize

.

be the values defined by the three

Logical Layer Modules

rio_addr[33:0]

xamsbs

field,

rio_addr[2:0]

be

is

corresponding window-defining registers. The least significant 3 bits of base, mask,
and offset are fixed at

3’b000

regardless of the content of the window-defining

registers.

xamo

Let

be the

Window n Offset

Extended Address MSBits Offset

field in the

Input/Output Slave

register (the two least significant bits of the register).

Starting with window 0, find the first window for which

(({address,Nb’0} & mask) == (base & mask))

where N is 2 in 1x variations and 3 in 2x and 4x variations.

Let

rio_addr [33:3] = {xamo, (offset [31:3] & mask [31:3]) |

({avalon_address,Nb’0} [31:3]])}

If the address matches multiple windows, the lowest number window register set is
used. The Avalon-MM slave interface’s
the values of

wdptr

and

rdsize

or

burstcount

wrsize

and

byteenable

signals determine

, as described in “Avalon-MM Burstcount

and Byteenable Encoding in RapidIO Packets” on page 4–48.

The

priority

and

DESTINATION_ID

fields are inserted from the control register.

If the address does not match any window the following events occur:

■ An interrupt bit, either

Input/Output Slave Interrup

■ The interrupt signal

in the

Input/Output Slave Interrupt Enable

■ The

COMPLETED_OR_CANCELLED_WRITES

Write Requests

register is incremented if the transaction is a write request.

An interrupt is cleared by writing

WRITE_OUT_OF_BOUNDS

t register (Table 6–46 on page 6–22), is set.

sys_mnt_s_irq

is asserted if enabled by the corresponding bit

field of the

1

to the interrupt register’s corresponding bit

or

READ_OUT_OF_BOUNDS

register (Table 6–47 on page 6–23).

Input/Output Slave RapidIO

location.

in the

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–45

Logical Layer Modules

Figure 4–22 shows the I/O slave Logical window translation process.

Figure 4–22. Input/Output Slave Window Translation

RapidIO

Address Space

0x3FFFFFFF8

Avalon-MM

Address Space

{Initial Avalon-MM

Address, Nb’0}

Window Base

Window Mask

Window Offset

Resulting

RapidIO Address

0xFFFFFFF8

Window

Base

0x00000000

31

11111111.........................11

XAMO

31

33

(1)

(1)

Offset

0x000000000

Window Size

023

Don’t Care

000000000000000..............00

Don’t Care

023

Note to Figure 4–22:

(1) These bits must have the same value in the initial Avalon-MM address and in the window base.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–46 Chapter 4: Functional Description

0x00000000

0x3FFFFFFC

0xFFFFFFFC

0x40000000

Avalon-MM

Address Space

RapidIO

Address Space

0x7FFFFFFC

0x80000000

0xBFFFFFFC

0xC0000000

0x000000000

0x03FFFFFF8

0x040000000

0x07FFFFFF8

0x080000000

0x0BFFFFFF8

0x0C0000000

0x0FFFFFFF8

0x100000000

0x3FFFFFFF8

PE 2

PE 1

PE 0PE 0

PE 1

PE 2

Logical Layer Modules

Input/Output Slave Translation Window Example

This section contains an example illustrating the use of I/O slave translation
windows. In this example, a RapidIO IP core with 8-bit device ID communicates with
three other processing endpoints through three I/O slave translation windows. For
this example, the

XAMO

bits are set to

2'b00

for all three windows. The offset value
differs for each window, which results in the segmentation of the RapidIO address
space that is shown in Figure 4–23.

Figure 4–23. Input/Output Slave Translation Window Address Mapping

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

The two most significant bits of the Avalon-MM address are used to differentiate
between the processing endpoints. Figure 4–25 through Figure 4–29 show the address
translation implemented for each window. Each figure shows the value for the
destination ID of the control register for one window.

Translation Window 0

An Avalon-MM address in which the two most significant bits have the value
matches window 0. The RapidIO transaction corresponding to the Avalon-MM
operation has a

DESTINATION_ID

value of

0x55

. This value corresponds to processing

2'b01

endpoint 0.

Chapter 4: Functional Description 4–47

Logical Layer Modules

Figure 4–24 shows address translation window 0.

Figure 4–24. Translation Window 0

2

1

{Avalon Address,Nb’0}

3031

01

29

0x7555999

3

0

Base (register 0x10400)

Mask (register 0x10404)

Offset (register 0x10408)

RapidIO Address [33:0]

Control (register 0x1040C)

Translation Window 1

An Avalon-MM address in which the two most significant bits have a value of
matches window 1. The RapidIO transaction corresponding to the Avalon-MM
operation has a destination ID value of
endpoint 1.

Figure 4–25 shows address translation window 1.

Figure 4–25. Translation Window 1

0

1

11

XAMO

00

1

0000

30313233

1

Don’t Care

000000000000000000..............00

Don’t Care

29

0x7555999

23 16

0x55

Destination ID

0xAA

. This value corresponds to processing

1

R

3

00 0

R

2'b10

023

1

R

3

00 0

1

R

{Avalon Address,Nb’0}

Base (register 0x10410)

Mask (register 0x10414)

Offset (register 0x10418)

RapidIO Address [33:0]

Control (register 0x1041C)

3031

10

1

0

11

XAMO

1000

0

30313233

01

0

29

0x7555999

Don’t Care

000000000000000000..............00

Don’t Care

29

0x7555999

23 16

0xAA

Destination ID

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–48 Chapter 4: Functional Description

Logical Layer Modules

Translation Window 2

An Avalon-MM address in which the two most significant bits have a value of

2'b11

matches window 2. The RapidIO transaction corresponding to the Avalon-MM
operation has a destination ID value of

0xCC.

This value corresponds to processing

endpoint 2.

Figure 4–26 shows address translation window 2.

Figure 4–26. Translation Window 2

023

{Avalon Address, N’b0}

3031

11

29

0x7555999

1

Base (register 0x10420)

Mask (register 0x10424)

Offset (register 0x10428)

RapidIO Address [33:0]

Control (register 0x1042C)

1

1

11

XAMO

1000

1

30313233

01

1

000000000000000000..............00

29

Don’t Care

Don’t Care

0x7555999

23 16

0xCC

Destination ID

1

R

3

00 0

R

Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets

The RapidIO IP core converts Avalon-MM transactions to RapidIO packets. The
Avalon-MM burst count, byteenable, and, in 32-bit variations, address bit 2 values are
translated to the RapidIO packets' read size, write size, and word pointer fields.

For information about the packet size encoding used in the conversion process for
32–bit datapath read requests, refer to Table 4–11. For information about the encoding
for 32-bit datapath write requests, refer to Table 4–12. For information about the
encoding for 64-bit datapath conversion, refer to Table 4–13 and Table 4–14.

Table 4–11. Read Request Size Encoding (32-bit datapath) (Part 1 of 2)

Avalon-MM Values RapidIO Values

burstcount

(1)

address[0]

(2)

(1'bx)

wdptr

(1'bx)

(2)

rdsize

(4'bxxxx)

1 1 0 1000
1 0 1 1000

2 0 0 1011
3–4 0 1 1011
5–8 0 0 1100

9–16 0 1 1100
17–24 0 0 1101
25–32 0 1 1101
33–40 0 0 1110

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–49

Logical Layer Modules

Table 4–11. Read Request Size Encoding (32-bit datapath) (Part 2 of 2)

Avalon-MM Values RapidIO Values

burstcount

(1)

address[0]

(2)

(1'bx)

wdptr

(1'bx)

(2)

rdsize

(4'bxxxx)

41–48 0 1 1110
49–56 0 0 1111
57–64 0 1 1111

Notes to Table 4–11:

(1) For read transfers, the read size of the request packet is rounded up to the next supported size, but only the number

of words corresponding to the requested read burst size is returned.

(2) Burst transfers of more than one Avalon-MM word must start on a double-word aligned Avalon-MM address. If

the slave read burst count is larger than one and
same manner as a failed mapping: the
register is set,

io_s_rd_readerror

sys_mnt_s_irq

for the duration of the burst.

READ_OUT_OF_BOUNDS

is asserted if enabled, and the transfer is marked as errored by asserting

io_s_rd_address[0]

bit in the

is not zero, the transfer completes in the

Input/Output Slave Interrupt

Tab le 4 –1 2 lists the allowed burst count, byteenable, and address bit 2 value

combinations for RapidIO IP core variations with a 32-bit Avalon-MM interface.
Avalon-MM value combinations not listed in Table 4–12 flag interrupts in the RapidIO
IP core. For more information about the relevant interrupts, refer to Table 6–46 on

page 6–22.

Table 4–12. Write Request Size Encoding (32-bit datapath) (Part 1 of 2)

Avalon-MM Values RapidIO Values

burstcount

(1)

byteenable

'

bxxxx)

(4

address [0]

(1'bx)

(2)

wdptr

(1'bx)

1 1000 1 0 0000

1 0100 1 0 0001

1 0010 1 0 0010

1 0001 1 0 0011

1 1000 0 1 0000

1 0100 0 1 0001

1 0010 0 1 0010

1 0001 0 1 0011

1 1100 1 0 0100

1 1110

(3)

1 0 0101

1 0011 1 0 0110

1 1100 0 1 0100

1 0111

(3)

0 1 0101

1 0011 0 1 0110

1 1111 1 0 1000

1 1111 0 1 1000

wrsize

(4'bxxxx)

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–50 Chapter 4: Functional Description

Logical Layer Modules

Table 4–12. Write Request Size Encoding (32-bit datapath) (Part 2 of 2)

Avalon-MM Values RapidIO Values

burstcount

2

(1)

byteenable

'

bxxxx)

(4

address [0]

(1'bx)

(2)

wdptr

(1'bx)

wrsize

(4'bxxxx)

01011

4 1 1011

6 or 8 0 1100

10, 12, 14, 16 1 1100

18, 20, 22, 24 1 1101

1111

(4)

0

26, 28, 30, 32 1 1101

34, 36, 38, 40,
42, 44, 46, 48,
50, 52, 54, 56,

11111

58, 60, 62, 64

Notes to Table 4–12:

(1) For write transfers in variations with 32-bit wide datapaths, odd burst sizes other than 1 are not supported. If one

occurs, the

sys_mnt_s_irq

(2) Burst transfers of more than one Avalon-MM word must start on a double-word aligned Avalon-MM address. If

io_s_wr_burstcount

same manner as a failed mapping: the

register is set and
(3) This is not a legal Avalon-MM byteenable pattern, but the RapidIO IP core supports it if user logic generates it.
(4) For all Avalon-MM write transfers with burstcount larger than 1,

If it is not, the transfer fails: the

register is set and

INVALID_WRITE_BURSTCOUNT

to be asserted if enabled.

is larger than one and

sys_mnt_s_irq

io_s_mnt_irq

WRITE_OUT_OF_BOUNDS

is asserted if enabled.

INVALID_WRITE_BYTEENABLE

is asserted if enabled.

bit in the

Input/Output Slave Interrupt

io_s_wr_address[0]

register is set, causing

is not zero, the transfer completes in the

bit in the

bit in the

Input/Output Slave Interrupt

io_s_wr_byteenable

Input/Output Slave Interrupt

must be set to

4’b1111

.

Tab le 4 –1 3 lists the allowed read-request size encodings for RapidIO IP core variations

with a 64-bit Avalon-MM interface.

Table 4–13. Read Request Size Encoding (64-bit datapath)

Avalon-MM Values

burstcount

(1)

11

21
3–4 1
5–8 1

9–12 1
13–16 1
17–20 1
21–24 1

25–28 1
29–32 1

Note to Tab le 4– 13:

(1) For read transfers, the read size of the request packet is rounded up to the next supported size, but only the number

of words corresponding to the requested read burst size are returned.

wdptr
(1'bx)

'

b0 4'b1011

'

b1 4'b1011

'

b0 4'b1100

'

b1 4'b1100

'

b0

'

b1

'

b0

'

b1

'

b0

'

b1

RapidIO

Values

rdsize

(4'bxxxx)

4

'

b1101

4

'

b1110

'

b1111

4

(1)

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–51

Logical Layer Modules

Tab le 4 –1 4 lists the allowed burst count and byteenable combinations for RapidIO IP

core variations with a 64-bit Avalon-MM interface. Avalon-MM value combinations
not listed in Ta bl e 4 –1 4 flag interrupts in the RapidIO IP core. For more information
about the relevant interrupts, refer to Table 6–46 on page 6–22.

Table 4–14. Write Request Size Encoding (64-bit datapath)

Avalon-MM Values RapidIO Values

burstcount byteenable

'

bxxxx_xxxx)

(8

wdptr

(1'bx)

wrsize
(4'bx)

1 1000_0000 0 0000
1 0100_0000 0 0001
1 0010_0000 0 0010
1 0001_0000 0 0011
1 0000_1000 1 0000
1 0000_0100 1 0001
1 0000_0010 1 0010
1 0000_0001 1 0011
1 1100_0000 0 0101
1 1110_0000

(1)

0 0110
1 0011_0000 0 0111
1 1111_1000

(1)

0 1000
1 0000_1100 1 1000
1 0000_0111

(1)

1 1001
1 0000_0011 1 1001
1 0001_1111

(1)

1 1010
1 1111_0000 0 1000
1 0000_1111 1 1000
1 1111_1100 0 1001
1 0011_1111 1 1001
1 1111_1110
1 0111_1111

(1)

(1)

0 1010

1 1010
1 1111_1111 0 1011
2

1 1011

3–4 0 1100
5–8 1 1100

9–12

13–16

1111_1111

(2)

1 1101

17–20
21–24
25–28

1 1111

29–32

Notes to Table 4–14:

(1) This is not a legal Avalon-MM byteenable pattern, but the RapidIO IP core supports it if user logic generates it.
(2) For all Avalon-MM write transfers with burstcount larger than 1,

8’b1111_1111
Interrupt

. If it is not, the transfer fails: the

register is set and

io_s_mnt_irq

INVALID_WRITE_BYTEENABLE

is asserted if enabled.

io_s_wr_byteenable

must be set to

bit in the

Input/Output Slave

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–52 Chapter 4: Functional Description

sysclk

io_s_rd_chipselect

io_s_rd_waitrequest

io_s_rd_read

io_s_rd_address[31:0]

io_s_rd_readdatavalid

io_s_rd_readdata[31:0]

io_s_rd_burstcount[7:0]

io_s_rd_readerror

Adr0 Adr1

00000000 r0 r1 r2

01 02

sysclk

io_s_wr_chipselect

io_s_wr_waitrequest

io_s_wr_write

io_s_wr_address[31:0]

io_s_wr_writedata[31:0]

io_s_wr_byteenable[3:0]

io_s_wr_burstcount[7:0]

00000000

AdrA

AdrB

w0

w1 w2 w3 w4 w5

F

02 04

Logical Layer Modules

Input/Output Avalon-MM Slave Module Timing Diagrams

Figure 4–27 shows the timing dependencies on the Avalon-MM slave interface for an

outgoing RapidIO
Avalon-MM slave interface for an outgoing
requests originate on the Avalon-MM interface of the slave module. The timing
diagrams in “Input/Output Avalon-MM Master Module Timing Diagrams” on

page 4–40 show the same transactions after they are transmitted on the RapidIO link

and received by an Altera RapidIO IP core link partner, when they are sent out as
Avalon-MM requests by an Input/Output Avalon-MM master module in the partner
RapidIO IP core.

Figure 4–27. NREAD Transaction on the Input/Output Avalon-MM Slave Interface

NREAD

request. Figure 4–28 shows the timing dependencies on the

NWRITE

transaction. Both transaction

Figure 4–28. NWRITE Transaction on the Input/Output Avalon-MM Slave Interface

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide

Chapter 4: Functional Description 4–53

Logical Layer Modules

Doorbell Module

The Doorbell module provides support for Type 10 packet format (

DOORBELL

class)
transactions, allowing users to send and receive short software-defined messages to
and from other processing elements connected to the RapidIO interface.

Figure 4–8 on page 4–23 shows how the Doorbell module is connected to the

Transport layer module. In a typical application the Doorbell module’s Avalon-MM
slave interface is connected to the system interconnect fabric, allowing an Avalon-MM
master to communicate with RapidIO devices by sending and receiving

DOORBELL

messages.

When you configure the RapidIO IP core, you can enable or disable the

DOORBELL

operation feature, depending on your application requirements. If you do not need
the

DOORBELL

feature, disabling it reduces device resource usage. If you enable the
feature, a 32–bit Avalon-MM slave port is created that allows the RapidIO MegaCore
to receive, generate, or both receive and generate RapidIO

DOORBELL

messages.

Doorbell Module Block Diagram

Figure 4–29 illustrates the Doorbell module. This module includes a 32–bit

Avalon-MM slave interface to the user interface. The Doorbell module contains the
following logic blocks:

■ Register and FIFO interface that allows an external Avalon-MM master to access

the Doorbell module’s internal registers and FIFO buffers.

■ Tx output FIFO that stores the outbound

for transmission to the Transport layer module.

DOORBELL

and

response

packets waiting

■ Acknowledge RAM that temporarily stores the transmitted

DOORBELL

packets

pending responses to the packets from the target RapidIO device.

■ Tx time-out logic that checks the expiration time for each outbound Tx

DOORBELL

packet that is sent.

■ Rx control that processes

DOORBELL

packets received from the Transport layer

module. Received packets include the following packet types:

■ Rx

DOORBELL

■ Rx response

■ Rx response

■ Rx response

■ Rx FIFO that stores the received

request.

DONE

to a successfully transmitted

RETRY

to a transmitted

ERROR

to a transmitted

DOORBELL

DOORBELL

DOORBELL

DOORBELL

message.

message.

packet.

messages until they are read by an

external Avalon-MM master device.

■ Tx FIFO that stores

■ Tx staging FIFO that stores

DOORBELL

DOORBELL

messages that are waiting to be transmitted.

messages until they can be passed to the Tx
FIFO. The staging FIFO is present only if you select Prevent doorbell messages
from passing write transactions in the RapidIO parameter editor. Arria 10
variations have a staging FIFO and prevent

DOORBELL

messages from passing write

transactions.

■ Tx completion FIFO that stores the transmitted

received responses. This FIFO also stores timed out Tx

DOORBELL

DOORBELL

messages that have

requests.

August 2014 Altera Corporation RapidIO MegaCore Function

User Guide

4–54 Chapter 4: Functional Description

Sink

Rx Control

Source

Acknowledge

RAM

Doorbell Logical Module

From

Transport

Layer

Module

To

Transport

Layer

Module

To Register Module From I/O Slave Module

Error

Management

Tx Output

FIFO

Rx

FIFO

IRQ

Avalon-MM

Slave

System

Interconnect

Fabric

Tx

FIFO

Tx Staging

FIFO

Tx Completion

FIFO

Tx

Timeout

Register

and

FIFO

Interface

■ Error Management module that reports detected errors, including the following

Logical Layer Modules

errors:

■ Unexpected response (a response packet was received, but its

does not match any pending request that is waiting for a response).

■ Request time-out (an outbound

from the target device).

Figure 4–29. Doorbell Module Block Diagram

DOORBELL

TransactionID

request did not receive a response

Preserving Transaction Order

Your RapidIO IP core Doorbell module has a Tx staging FIFO in any of the following
situations:

■ You se lec t Prevent doorbell messages from passing write transactions in the

RapidIO parameter editor.

■ Your RapidIO IP core targets an Arria 10 device.

If the module has a Tx staging FIFO, each
interface is kept in the Tx staging FIFO until all I/O write transactions that started on
the write Avalon-MM slave interface before this
Doorbell module Avalon-MM interface have been transmitted to the Transport layer.
An I/O write transaction is considered to have started before a
the

io_s_wr_write

io_s_wr_waitrequest

the

drbell_s_write

Tx Doorbell

If you do not select Prevent doorbell messages from passing write transactions in

and

io_s_wr_chipselect

signal is not asserted, on a cycle preceding the cycle on which

and

drbell_s_chipselect

register while the

drbell_s_waitrequest

the RapidIO parameter editor, the Doorbell Tx staging FIFO is not configured in the
RapidIO IP core.

DOORBELL

message from the Avalon-MM

DOORBELL

message arrived on the

DOORBELL

transaction if

signals are asserted while the

signals are asserted for writing to the

signal is not asserted.

RapidIO MegaCore Function August 2014 Altera Corporation
User Guide