2015.05.04
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Quartus Settings File Reference Manual
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Advanced I/O Timing Assignments
BOARD_MODEL_EBD_FAR_END
Specifies the far-end node to be used in the Electronic Board Description (EBD) path description.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to <to> -entity
<entity name> <value>
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
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BOARD_MODEL_EBD_FILE_NAME
BOARD_MODEL_EBD_FILE_NAME
Specifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to <to> -entity
<entity name> <value>
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BOARD_MODEL_EBD_SIGNAL_NAME
Specifies the Electronic Board Description (EBD) path description to be used with an I/O pin. You must
specify the EBD file name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to <to> -entity
<entity name> <value>
BOARD_MODEL_EBD_SIGNAL_NAME
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BOARD_MODEL_FAR_C
BOARD_MODEL_FAR_C
Specifies, in farads, the board trace model far capacitance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_C -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_FAR_C -section_id <section
identifier> <value>
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BOARD_MODEL_FAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model far differential resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id
<section identifier> <value>
BOARD_MODEL_FAR_DIFFERENTIAL_R
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BOARD_MODEL_FAR_PULLDOWN_R
BOARD_MODEL_FAR_PULLDOWN_R
Specifies, in ohms, the board trace model far pull-down resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id <section
identifier> <value>
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BOARD_MODEL_FAR_PULLUP_R
Specifies, in ohms, the board trace model far pull-up resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <section
identifier> <value>
BOARD_MODEL_FAR_PULLUP_R
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BOARD_MODEL_FAR_SERIES_R
BOARD_MODEL_FAR_SERIES_R
Specifies, in ohms, the board trace model far series resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <section
identifier> <value>
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BOARD_MODEL_NEAR_C
Specifies, in farads, the board trace model near capacitance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_C -to <to> -entity <entity
name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <section
identifier> <value>
BOARD_MODEL_NEAR_C
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BOARD_MODEL_NEAR_DIFFERENTIAL_R
BOARD_MODEL_NEAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model near differential resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id
<section identifier> <value>
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BOARD_MODEL_NEAR_PULLDOWN_R
Specifies, in ohms, the board trace model near pull-down resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id
<section identifier> <value>
BOARD_MODEL_NEAR_PULLDOWN_R
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BOARD_MODEL_NEAR_PULLUP_R
BOARD_MODEL_NEAR_PULLUP_R
Specifies, in ohms, the board trace model near pull-up resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <section
identifier> <value>
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BOARD_MODEL_NEAR_SERIES_R
Specifies, in ohms, the board trace model near series resistance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <section
identifier> <value>
BOARD_MODEL_NEAR_SERIES_R
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BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model near transmission line distributed capacitance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -section_id
<section identifier> <value>
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BOARD_MODEL_NEAR_TLINE_LENGTH
Specifies, in inches, the board trace model near transmission line length.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id
<section identifier> <value>
BOARD_MODEL_NEAR_TLINE_LENGTH
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BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model near transmission line distributed inductance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -section_id
<section identifier> <value>
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BOARD_MODEL_TERMINATION_V
Specifies, in volts, the board trace model termination voltage.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <section
identifier> <value>
BOARD_MODEL_TERMINATION_V
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BOARD_MODEL_TLINE_C_PER_LENGTH
BOARD_MODEL_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model far transmission line distributed capacitance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id
<section identifier> <value>
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BOARD_MODEL_TLINE_LENGTH
Specifies, in inches, the board trace model far transmission line length.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to <to> -entity
<entity name> <value>
set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <section
identifier> <value>
BOARD_MODEL_TLINE_LENGTH
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BOARD_MODEL_TLINE_L_PER_LENGTH
BOARD_MODEL_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model far transmission line distributed inductance.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to <to> entity <entity name> <value>
set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id
<section identifier> <value>
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ENABLE_ADVANCED_IO_TIMING
Allows the TimeQuest Timing Analyzer to use Advanced I/O Timing to generate I/O timing results.
Timing results are based on the board trace model specified for each pin, and may differ from the results
currently reported.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING <value>
ENABLE_ADVANCED_IO_TIMING
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OUTPUT_IO_TIMING_ENDPOINT
OUTPUT_IO_TIMING_ENDPOINT
Specifies the node at which output I/O Timing ends.
Type
Enumeration
Values
• Far End
• Near End
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
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set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to <to> -entity
<entity name> <value>
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity <entity name>
<value>
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <value>
Default Value
Near End
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OUTPUT_IO_TIMING_FAR_END_VMEAS
Specifies, in volts, the measurement voltage at the far-end.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to <to> entity <entity name> <value>
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id
<section identifier> <value>
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS <value>
OUTPUT_IO_TIMING_FAR_END_VMEAS
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OUTPUT_IO_TIMING_NEAR_END_VMEAS
OUTPUT_IO_TIMING_NEAR_END_VMEAS
Specifies, in volts, the measurement voltage at the near-end.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to <to> entity <entity name> <value>
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id
<section identifier> <value>
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS <value>
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PCB_LAYER
PCB_LAYER
Specifies which PCB layer the signal breaks out on
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYER -to <to> -entity <entity name>
<value>
set_global_assignment -name PCB_LAYER -section_id <section identifier>
<value>
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PCB_LAYERS
PCB_LAYERS
Specifies the properties of all PCB layers
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYERS -to <to> <value>
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PCB_LAYER_THICKNESS
Thickness of the specific PCB layer
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYER_THICKNESS -to <to> -entity <entity
name> <value>
set_global_assignment -name PCB_LAYER_THICKNESS -section_id <section
identifier> <value>
PCB_LAYER_THICKNESS
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SYNCHRONOUS_GROUP
SYNCHRONOUS_GROUP
A logic option that assigns a synchronous group number for the specified node. This option directs the
SSN Analyzer to view the specified nodes as a synchronous group during SSN voltage noise analysis. This
option can be set in the Assignment Editor.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name SYNCHRONOUS_GROUP -to <to> -entity <entity
name> <value>
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Analysis & Synthesis Assignments
ADV_NETLIST_OPT_ALLOWED
Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level
retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the
Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming
during netlist optimization, only if doing so does not negatively affect the timing or performance of the
design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so
affects the timing or performance of the design. Altera does not recommend using this setting. If this
option is set to 'Never Allow' the Compiler cannot alter the node or entity.
Type
Enumeration
Values
• Always Allow
• Default
• Never Allow
Analysis & Synthesis Assignments
29
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name>
<value>
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity
<entity name> <value>
Example
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg
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ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the
setting specified in the Optimization Technique logic option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP <value>
set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to <to> entity <entity name> <value>
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Default Value
Off
Example
set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on
set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to foo
See Also
Optimization Technique
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ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer RAMs of any size, even if they don't meet the current minimum
requirements.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION <value>
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity
<entity name> <value>
set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <to> entity <entity name> <value>
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
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Default Value
Off
Example
set_global_assignment -name allow_any_ram_size_for_recognition off
set_instance_assignment -name allow_any_ram_size_for_recognition off -to foo
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ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current
minimum size requirements.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION <value>
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity
<entity name> <value>
set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to <to> entity <entity name> <value>
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Default Value
Off
Example
set_global_assignment -name allow_any_rom_size_for_recognition off
set_instance_assignment -name allow_any_rom_size_for_recognition off -to foo
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ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
Allows the Compiler to infer shift registers of any size even if they do not meet the design's current
minimum size requirements.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
<value>
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION entity <entity name> <value>
set_instance_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
-to <to> -entity <entity name> <value>
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Default Value
Off
Example
set_global_assignment -name allow_any_shift_register_size_for_recognition
off
set_instance_assignment -name allow_any_shift_register_size_for_recognition
off -to foo
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ALLOW_CHILD_PARTITIONS
ALLOW_CHILD_PARTITIONS
Specifies whether or not an instance or a section of design hierarchy can contain user partitions.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity <entity name>
<value>
set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to <to> -entity
<entity name> <value>
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Example
set_global_assignment -name allow_child_partitions off
set_instance_assignment -name allow_child_partitions off -to "sub:inst"
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ALLOW_POWER_UP_DONT_CARE
Causes registers that do not have a Power-Up Level logic option setting to power up with a don't care
logic level (X). A don't care setting allows the Compiler to change the power-up level of a register to
minimize the area of the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <value>
ALLOW_POWER_UP_DONT_CARE
35
Default Value
On
Example
set_global_assignment -name allow_power_up_dont_care off
See Also
Power-Up Level
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ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
Allows the Compiler to take shift registers from different hierarchies of the design and put them in the
same RAM.
Type
Enumeration
Values
• Always
• Auto
• Off
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
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Syntax
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
<value>
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
-entity <entity name> <value>
set_instance_assignment -name
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -to <to> -entity <entity name>
<value>
Default Value
Auto
Example
set_global_assignment -name allow_shift_register_merging_across_hierarchies
off
set_instance_assignment -name
allow_shift_register_merging_across_hierarchies off -to foo
See Also
Auto Shift Register Replacement
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ALLOW_SYNCH_CTRL_USAGE
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic
cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might
negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <value>
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <entity name>
<value>
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to <to> -entity
<entity name> <value>
ALLOW_SYNCH_CTRL_USAGE
37
Default Value
On
Example
set_global_assignment -name allow_synch_ctrl_usage off
set_instance_assignment -name allow_synch_ctrl_usage off -to foo
See Also
Force Use of Synchronous Clear Signals
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38
ALLOW_XOR_GATE_USAGE
ALLOW_XOR_GATE_USAGE
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within an
Embedded System Block [ESB] that is set to use Product Term mode). This option is ignored if you select
'LUT' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_XOR_GATE_USAGE <value>
set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity <entity name>
<value>
set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
On
Example
set_instance_assignment -name allow_xor_gate_usage off -to clock
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APEX20K_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,
minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur
Type
Enumeration
Values
• Area
• Balanced
• Speed
Device Support
This setting can be used in projects targeting any Altera device family.
APEX20K_OPTIMIZATION_TECHNIQUE
39
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE -entity <entity
name> <value>
set_instance_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE -to <to> entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name apex20k_optimization_technique speed
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APEX20K_TECHNOLOGY_MAPPER
APEX20K_TECHNOLOGY_MAPPER
Specifies whether to target look-up table (LUT) or Product Term when implementing logic in the device.
The Technology Mapper option allows you to determine whether logic is implemented in LABs or ESBs.
Depending on the setting of this option, other logic options may be ignored. For example, because carry
and cascade chains can only be implemented in LUTs, the Auto Carry Chains and Auto Cascade Chains
options are ignored if the 'Product Term' setting is selected. Similarly, because parallel expanders can only
be implemented in product terms, the Auto Parallel Expander Chains option is ignored if the 'LUT'
setting is selected.
Old Name
TECHNOLOGY_MAPPER, Technology Mapper -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARMbased Excalibur
Type
Enumeration
Values
• LUT
• Product Term
MNL-Q21005
2015.05.04
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER <value>
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER -entity <entity name>
<value>
set_instance_assignment -name APEX20K_TECHNOLOGY_MAPPER -to <to> -entity
<entity name> <value>
Default Value
Lut
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AUTO_CARRY_CHAINS
Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into the
design. This option is also required to recognize carry chains in any design containing MAX+PLUS IIstyle CARRY buffers. The length of the chains is controlled with the Carry Chain Length option. If this
option is turned off, CARRY buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto
Carry Chains option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology
Mapper option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
AUTO_CARRY_CHAINS
41
Syntax
set_global_assignment -name AUTO_CARRY_CHAINS <value>
set_global_assignment -name AUTO_CARRY_CHAINS -entity <entity name> <value>
set_instance_assignment -name AUTO_CARRY_CHAINS -to <to> -entity <entity
name> <value>
Default Value
On
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AUTO_CASCADE_CHAINS
AUTO_CASCADE_CHAINS
Allows the Compiler to create cascade chains automatically by inserting CASCADE buffers into the
design. The length of the chains is controlled with the Cascade Chain Length option. The Auto Cascade
Chains option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology Mapper
option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CASCADE_CHAINS <value>
set_global_assignment -name AUTO_CASCADE_CHAINS -entity <entity name>
<value>
set_instance_assignment -name AUTO_CASCADE_CHAINS -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
On
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AUTO_CLOCK_ENABLE_RECOGNITION
Allows the Compiler to find logic that feeds a register and move the logic to the register's clock enable
input port.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION <value>
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity <entity
name> <value>
set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to <to> entity <entity name> <value>
AUTO_CLOCK_ENABLE_RECOGNITION
43
Default Value
On
Example
set_global_assignment -name auto_clock_enable_replacement off
set_instance_assignment -name auto_clock_enable_replacement off -to reg
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AUTO_DSP_RECOGNITION
AUTO_DSP_RECOGNITION
Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be
replaced with the altmult_accum or the altmult_add megafunction.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_DSP_RECOGNITION <value>
set_global_assignment -name AUTO_DSP_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name AUTO_DSP_RECOGNITION -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
On
Example
set_global_assignment -name auto_dsp_recognition off
set_instance_assignment -name auto_dsp_recognition off -to foo
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AUTO_ENABLE_SMART_COMPILE
Specifies whether the SignalTap II Logic Analyzer should perform a smart compilation if conditions exist
in which SignalTap II with incremental routing is used.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE <value>
AUTO_ENABLE_SMART_COMPILE
45
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46
AUTO_GLOBAL_CLOCK_MAX
AUTO_GLOBAL_CLOCK_MAX
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock
signal that is made available throughout the device on the global routing paths. If you want to prevent the
Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to
'Off' on that signal.
Old Name
Auto Global Clock -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
MNL-Q21005
2015.05.04
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX <value>
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX -entity <entity name>
<value>
set_instance_assignment -name AUTO_GLOBAL_CLOCK_MAX -to <to> -entity
<entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_global_clock_max off
set_instance_assignment -name auto_global_clock_max off -to foo
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AUTO_GLOBAL_OE_MAX
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signal
that is made available throughout the device on the global routing paths. If you want to prevent the
Compiler from automatically selecting a particular signal as global output enable, set the Global Signal
option to 'Off' on that signal.
Old Name
Auto Global Output Enable -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
AUTO_GLOBAL_OE_MAX
47
Syntax
set_global_assignment -name AUTO_GLOBAL_OE_MAX <value>
set_global_assignment -name AUTO_GLOBAL_OE_MAX -entity <entity name> <value>
set_instance_assignment -name AUTO_GLOBAL_OE_MAX -to <to> -entity <entity
name> <value>
Default Value
On
Example
set_global_assignment -name auto_global_oe_max off
set_instance_assignment -name auto_global_oe_max off -to foo
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AUTO_IMPLEMENT_IN_ROM
AUTO_IMPLEMENT_IN_ROM
Allows the Compiler to automatically implement combinatorial logic in ROM (that is, in an embedded
cell within an Embedded System Block [ESB] or Embedded Array Block [EAB] that is set to use ROM
mode), to improve speed or area usage. Using ROM in this way can free up logic cells that would
otherwise be needed to implement the combinatorial logic. This option is ignored if you select 'Product
Term' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
MNL-Q21005
2015.05.04
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM <value>
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM -entity <entity name>
<value>
set_instance_assignment -name AUTO_IMPLEMENT_IN_ROM -to <to> -entity
<entity name> <value>
Default Value
Off
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AUTO_LCELL_INSERTION
Allows the Compiler to insert macrocells into the design. This option is ignored if it is assigned to
anything other than a design entity. If you want to prevent the Compiler from automatically inserting
macrocells into the design, set the Auto Logic Cell Insertion option to 'Off' on that signal.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_LCELL_INSERTION <value>
set_global_assignment -name AUTO_LCELL_INSERTION -entity <entity name>
<value>
set_instance_assignment -name AUTO_LCELL_INSERTION -to <to> -entity <entity
name> <value>
AUTO_LCELL_INSERTION
49
Default Value
On
Example
set_global_assignment -name auto_lcell_insertion off
set_instance_assignment -name auto_lcell_insertion off -to foo
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AUTO_OPEN_DRAIN_PINS
AUTO_OPEN_DRAIN_PINS
Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the
equivalent open-drain buffer.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_OPEN_DRAIN_PINS <value>
set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity <entity name>
<value>
set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
On
Example
set_global_assignment -name auto_open_drain_pins off
set_instance_assignment -name auto_open_drain_pins off -to foo
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AUTO_PARALLEL_EXPANDERS
Allows the Compiler to automatically create chains of parallel expander product terms. Parallel expanders
are available in macrocells, that is, embedded cells within an Embedded System Block [ESB] that is set to
use Product Term mode. The length of the chains is controlled with the Parallel Expander Chain Length
option. The Auto Parallel Expanders option is ignored if you select 'LUT' or 'ROM' as the setting for the
Technology Mapper option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
AUTO_PARALLEL_EXPANDERS
51
set_global_assignment -name AUTO_PARALLEL_EXPANDERS <value>
set_global_assignment -name AUTO_PARALLEL_EXPANDERS -entity <entity name>
<value>
set_instance_assignment -name AUTO_PARALLEL_EXPANDERS -to <to> -entity
<entity name> <value>
Default Value
On
Example
set_instance_assignment -name auto_parallel_expanders on -to clock
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AUTO_PARALLEL_SYNTHESIS
AUTO_PARALLEL_SYNTHESIS
Option to enable/disable automatic parallel synthesis. This option can be used to speed up synthesis
compile time by using multiple processors when available.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS <value>
MNL-Q21005
2015.05.04
Default Value
On
Example
set_global_assignment -name auto_parallel_synthesis on
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AUTO_RAM_BLOCK_BALANCING
Enables the Compiler to automatically use different memory types when using auto RAM blocks and
allows the Compiler to use different RAM partitions with the same memory types.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING <value>
AUTO_RAM_BLOCK_BALANCING
53
Default Value
On
Example
set_global_assignment -name auto_ram_block_balancing off
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54
AUTO_RAM_RECOGNITION
AUTO_RAM_RECOGNITION
Allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the
lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RAM_RECOGNITION <value>
set_global_assignment -name AUTO_RAM_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name AUTO_RAM_RECOGNITION -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
On
Example
set_global_assignment -name auto_ram_recognition off
set_instance_assignment -name auto_ram_recognition off -to foo
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AUTO_RAM_TO_LCELL_CONVERSION
Allows the Compiler to convert small RAM blocks into logic cells.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION <value>
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -entity <entity
name> <value>
set_instance_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -to <to> -entity
<entity name> <value>
AUTO_RAM_TO_LCELL_CONVERSION
55
Default Value
Off
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AUTO_RESOURCE_SHARING
AUTO_RESOURCE_SHARING
Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations
in your HDL source code. If you enable this option, the Compiler will merge compatible addition,
subtraction, and multiplication operations. By merging operations, this may reduce the area required by
your design. Because resource sharing introduces extra muxing and control logic on each shared resource,
it may negatively impact the final fmax of your design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
MNL-Q21005
2015.05.04
set_global_assignment -name AUTO_RESOURCE_SHARING <value>
set_global_assignment -name AUTO_RESOURCE_SHARING -entity <entity name>
<value>
set_instance_assignment -name AUTO_RESOURCE_SHARING -to <to> -entity
<entity name> <value>
Default Value
Off
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AUTO_ROM_RECOGNITION
Allows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom megafunction.
Turning on this option may change the power-up state of the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_ROM_RECOGNITION <value>
set_global_assignment -name AUTO_ROM_RECOGNITION -entity <entity name>
<value>
set_instance_assignment -name AUTO_ROM_RECOGNITION -to <to> -entity <entity
name> <value>
AUTO_ROM_RECOGNITION
57
Default Value
On
Example
set_global_assignment -name auto_rom_recognition off
set_instance_assignment -name auto_rom_recognition off -to foo
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AUTO_SHIFT_REGISTER_RECOGNITION
AUTO_SHIFT_REGISTER_RECOGNITION
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the
altshift_taps megafunction. The shift registers must all use the same clock and clock enable signals, must
not have any other secondary signals, and must have equally spaced taps that are at least three registers
apart.
Type
Enumeration
Values
• Always
• Auto
• Off
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
MNL-Q21005
2015.05.04
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION <value>
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity <entity
name> <value>
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to <to> entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name auto_shift_register_recognition off
set_instance_assignment -name auto_shift_register_recognition off -to foo
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BLOCK_DESIGN_NAMING
Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything
other than a design entity.
Type
Enumeration
Values
• Auto
• MaxPlusII
• QuartusII
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
BLOCK_DESIGN_NAMING
59
Syntax
set_global_assignment -name BLOCK_DESIGN_NAMING -entity <entity name>
<value>
set_instance_assignment -name BLOCK_DESIGN_NAMING -to <to> -entity <entity
name> <value>
set_global_assignment -name BLOCK_DESIGN_NAMING <value>
Default Value
Auto
Example
set_global_assignment -name block_design_naming MaxPlusII
set_instance_assignment -name block_design_naming MaxPlusII -to top
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CARRY_CHAIN_LENGTH
CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized
CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option
also applies to MAX+PLUS II-style CARRY buffers.)
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CARRY_CHAIN_LENGTH <value>
set_global_assignment -name CARRY_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name CARRY_CHAIN_LENGTH -to <to> -entity <entity
name> <value>
MNL-Q21005
2015.05.04
Default Value
48
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CASCADE_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized
CASCADE buffers. Cascade chains that exceed this length are broken into separate chains.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CASCADE_CHAIN_LENGTH <value>
set_global_assignment -name CASCADE_CHAIN_LENGTH -entity <entity name>
<value>
set_instance_assignment -name CASCADE_CHAIN_LENGTH -to <to> -entity <entity
name> <value>
CASCADE_CHAIN_LENGTH
61
Default Value
2
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62
CLKLOCKX1_INPUT_FREQ
CLKLOCKX1_INPUT_FREQ
Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. Turning this option
on is equivalent to instantiating an altclklock megafunction with either of its ClockBoost parameters set to
a value of 1. The CLKLOCKx1 Input Frequency option is provided primarily for backward compatibility
with MAX+PLUS II designs. Altera recommends using the MegaWizard Plug-In Manager to instantiate
PLLs in new designs. This option is ignored if it is assigned to anything other than an input pin or to a
device that does not have the PLL feature.
Type
Frequency
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
MNL-Q21005
2015.05.04
set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to <to> -entity <entity
name> <value>
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CYCLONEII_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,
minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Cyclone II/Cyclone III
Type
Enumeration
Values
• Area
• Balanced
• Speed
Device Support
This setting can be used in projects targeting any Altera device family.
CYCLONEII_OPTIMIZATION_TECHNIQUE
63
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -entity
<entity name> <value>
set_instance_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -to <to> entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name cycloneii_optimization_technique speed
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64
CYCLONE_OPTIMIZATION_TECHNIQUE
CYCLONE_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance,
minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Cyclone
Type
Enumeration
Values
• Area
• Balanced
• Speed
Device Support
This setting can be used in projects targeting any Altera device family.
MNL-Q21005
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Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -entity <entity
name> <value>
set_instance_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -to <to> entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name cyclone_optimization_technique speed
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DEVICE_FILTER_PACKAGE
Package filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PACKAGE <value>
Default Value
DEVICE_FILTER_PACKAGE
65
Any
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DEVICE_FILTER_PIN_COUNT
DEVICE_FILTER_PIN_COUNT
Pin count filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PIN_COUNT <value>
Default Value
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Any
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DEVICE_FILTER_SPEED_GRADE
Speed grade filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE <value>
Default Value
DEVICE_FILTER_SPEED_GRADE
67
Any
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DEVICE_FILTER_VOLTAGE
DEVICE_FILTER_VOLTAGE
Voltage filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_VOLTAGE <value>
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DISABLE_DSP_NEGATE_INFERENCING
Allow you to specify whether to use the negate port on an inferred DSP block.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING -entity <entity
name> <value>
set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING -to <to> entity <entity name> <value>
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING <value>
DISABLE_DSP_NEGATE_INFERENCING
69
Default Value
Off
Example
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING ON
set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING OFF -to dps1
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DISABLE_OCP_HW_EVAL
DISABLE_OCP_HW_EVAL
Turns off OpenCore Plus hardware evaluation feature.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DISABLE_OCP_HW_EVAL <value>
Default Value
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Off
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DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
Specifies whether registers that are in different hierarchies are allowed to be merged if their inputs are the
same.
Type
Enumeration
Values
• Auto
• Off
• On
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
71
Syntax
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
<value>
Default Value
Auto
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DONT_MERGE_REGISTER
DONT_MERGE_REGISTER
When set to On, this option prevents the specified register from merging with other registers, and
prevents other registers from merging with the specified register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DONT_MERGE_REGISTER -entity <entity name>
<value>
set_instance_assignment -name DONT_MERGE_REGISTER -to <to> -entity <entity
name> <value>
MNL-Q21005
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Example
set_instance_assignment -name dont_merge_register on -to foo
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DQS_DELAY
DQS_DELAY
Increases the propagation delay from a DQS I/O pin to the interior of the device. This option is used to
center-align the DQS signal to the DQ data signals and should be selected to ensure the desired setup and
hold margins across process, voltage, and temperature ranges.
Type
Time
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_instance_assignment -name DQS_DELAY -to <to> -entity <entity name>
<value>
73
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DQS_FREQUENCY
DQS_FREQUENCY
Specifies the DQS system clock frequency by which data is transferred between a device and an external
RAM that uses double data rate (DDR). You can specify the desired frequency setting.
Type
Frequency
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_instance_assignment -name DQS_FREQUENCY -to <to> -entity <entity name>
<value>
MNL-Q21005
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DQS_SHIFT
DQS_SHIFT
Specifies the interval of arrival between the DQ data signals and DQS signal during data transfer between
a device and an external RAM that uses double data rate (DDR). This option is ignored if it is applied to
anything other than pins intended for use with the dedicated DDR SDRAM interface.
Type
Enumeration
Values
• Phase of 0 degrees
• Phase of 72 degrees
• Phase of 90 degrees
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
75
Syntax
set_instance_assignment -name DQS_SHIFT -to <to> -entity <entity name>
<value>
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DQS_SYSTEM_CLOCK
DQS_SYSTEM_CLOCK
Specifies the clock input used as a frequency reference for a DQS I/O pin. The clock is the pin that drives
the DDIO circuitry for the dedicated DDR SDRAM interface.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name DQS_SYSTEM_CLOCK -to <to> -entity <entity
name> <value>
MNL-Q21005
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DSE_SYNTH_EXTRA_EFFORT_MODE
Specifies the Design Space Explorer synthesis extra effort mode.
Type
Enumeration
Values
• MODE_1
• MODE_2
• MODE_3
• MODE_4
• MODE_5
• MODE_DEFAULT
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
DSE_SYNTH_EXTRA_EFFORT_MODE
77
None
Syntax
set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE <value>
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DSP_BLOCK_BALANCING
DSP_BLOCK_BALANCING
Allows you to control the conversion of certain DSP block slices during DSP block balancing.
Type
Enumeration
Values
• Auto
• DSP blocks
• Logic Elements
• Off
• Simple 18-bit Multipliers
• Simple Multipliers
• Width 18-bit Multipliers
Device Support
This setting can be used in projects targeting any Altera device family.
MNL-Q21005
2015.05.04
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DSP_BLOCK_BALANCING -entity <entity name>
<value>
set_instance_assignment -name DSP_BLOCK_BALANCING -to <to> -entity <entity
name> <value>
set_global_assignment -name DSP_BLOCK_BALANCING <value>
Default Value
Auto
Example
set_global_assignment -name dsp_block_balancing "dsp blocks"
set_instance_assignment -name dsp_block_balancing "logic elements" -to mult0
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EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
Specifies the third-party EDA tool used for design entry/synthesis
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL <value>
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity <entity
name> <value>
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
79
Default Value
<None>
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EDA_INPUT_DATA_FORMAT
EDA_INPUT_DATA_FORMAT
Specifies the format of the input data read from other EDA design entry/synthesis tools.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id <section
identifier> <value>
set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity <entity name> section_id <section identifier> <value>
Default Value
NONE, requires section identifier
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EDA_INPUT_GND_NAME
Specifies the global high signal used in the files generated by the EDA synthesis tool, which is GND.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_GND_NAME -section_id <section
identifier> <value>
set_global_assignment -name EDA_INPUT_GND_NAME -entity <entity name> section_id <section identifier> <value>
Default Value
GND, requires section identifier
EDA_INPUT_GND_NAME
81
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EDA_INPUT_VCC_NAME
EDA_INPUT_VCC_NAME
Specifies the global power-down signal.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_VCC_NAME -section_id <section
identifier> <value>
set_global_assignment -name EDA_INPUT_VCC_NAME -entity <entity name> section_id <section identifier> <value>
Default Value
VCC, requires section identifier
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EDA_LMF_FILE
Type
Device Support
Notes
Syntax
EDA_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
File name
This setting can be used in projects targeting any Altera device family.
The value of this assignment is case sensitive.
set_global_assignment -name EDA_LMF_FILE -section_id <section identifier>
<value>
set_global_assignment -name EDA_LMF_FILE -entity <entity name> -section_id
<section identifier> <value>
83
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EDA_RUN_TOOL_AUTOMATICALLY
EDA_RUN_TOOL_AUTOMATICALLY
Runs the third-party EDA tool automatically from Quartus II when a design is compiled.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id <section
identifier> <value>
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity <entity
name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
MNL-Q21005
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EDA_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id
<section identifier> <value>
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity <entity
name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_SHOW_LMF_MAPPING_MESSAGES
85
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EDA_VHDL_LIBRARY
EDA_VHDL_LIBRARY
Specifies the logical name of a user-defined VHDL design library : physical name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -section_id
<section identifier> <value>
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -entity <entity
name> -section_id <section identifier> <value>
MNL-Q21005
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ENABLE_IP_DEBUG
Make certain nodes (for example, important registers, pins, and state machines) visible for all the
MegaCore functions in a design. You can use a MegaCore function's nodes to effectively debug the
megafunction, particularly when using the megafunction with the SignalTap II Logic Analyzer. The Node
Finder, using SignalTap II Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes
visible. When making the debugging nodes visible, Analysis & Synthesis can change the fmax and number
of logic cells in MegaCore functions.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
ENABLE_IP_DEBUG
87
set_global_assignment -name ENABLE_IP_DEBUG <value>
Default Value
Off
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ENABLE_M512
ENABLE_M512
Enables the compiler to use M512 memory blocks in a design. Because HardCopy II designs do not
support M512 memory blocks, this option is useful when you migrate a compiled Stratix II design to a
HardCopy II design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_M512 <value>
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Example
set_global_assignment -name enable_m512 off
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EXTRACT_VERILOG_STATE_MACHINES
Allows the Compiler to extract state machines from Verilog Design Files. The Compiler optimizes state
machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler
extracts and optimizes state machines in Verilog Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES <value>
EXTRACT_VERILOG_STATE_MACHINES
89
Default Value
On
Example
set_global_assignment -name extract_verilog_state_machines off
See Also
State Machine Processing Extract VHDL State Machines
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EXTRACT_VHDL_STATE_MACHINES
EXTRACT_VHDL_STATE_MACHINES
Allows the Compiler to extract state machines from VHDL Design Files. The Compiler optimizes state
machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler
extracts and optimizes state machines in VHDL Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES <value>
MNL-Q21005
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Default Value
On
Example
set_global_assignment -name extract_vhdl_state_machines off
See Also
State Machine Processing Extract Verilog State Machines
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FAMILY
Specifies the device family to use for compilation.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FAMILY <value>
FAMILY
91
Default Value
Cyclone V
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FLEX10K_CARRY_CHAIN_LENGTH
FLEX10K_CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized
CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option
also applies to MAX+PLUS II-style CARRY buffers.)
Old Name
Carry Chain Length -- FLEX 10K
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
MNL-Q21005
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Syntax
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH -entity <entity
name> <value>
set_instance_assignment -name FLEX10K_CARRY_CHAIN_LENGTH -to <to> -entity
<entity name> <value>
Default Value
32
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FLEX10K_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or
minimize logic usage.
Old Name
Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K
Type
Enumeration
Values
• Area
• Speed
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
FLEX10K_OPTIMIZATION_TECHNIQUE
93
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE -entity <entity
name> <value>
set_instance_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE -to <to> entity <entity name> <value>
Default Value
Area
Example
set_global_assignment -name flex10k_optimization_technique speed
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FLEX6K_CARRY_CHAIN_LENGTH
FLEX6K_CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized
CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option
also applies to MAX+PLUS II-style CARRY buffers.)
Old Name
Carry Chain Length -- FLEX 6000
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
MNL-Q21005
2015.05.04
Syntax
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH <value>
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH -entity <entity name>
<value>
set_instance_assignment -name FLEX6K_CARRY_CHAIN_LENGTH -to <to> -entity
<entity name> <value>
Default Value
32
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FLEX6K_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or
minimize logic usage.
Old Name
Optimization Technique -- FLEX 6000
Type
Enumeration
Values
• Area
• Speed
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
FLEX6K_OPTIMIZATION_TECHNIQUE
95
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE <value>
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE -entity <entity
name> <value>
set_instance_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE -to <to> entity <entity name> <value>
Default Value
Area
Example
set_global_assignment -name flex6k_optimization_technique speed
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FORCE_SYNCH_CLEAR
FORCE_SYNCH_CLEAR
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this
option helps to reduce the total number of logic cells used in the design, but might negatively impact the
fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FORCE_SYNCH_CLEAR <value>
set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value>
set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity
name> <value>
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Default Value
Off
Example
set_global_assignment -name force_synch_clear on
set_instance_assignment -name force_synch_clear on -to foo
See Also
Allow Synchronous Control Signals
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HDL_INITIAL_FANOUT_LIMIT
Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after
elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then
Integrated Synthesis will issue a warning.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name>
<value>
set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity
<entity name> <value>
HDL_INITIAL_FANOUT_LIMIT
97
Example
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo
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HDL_MESSAGE_LEVEL
HDL_MESSAGE_LEVEL
Specifies the type of HDL messages you want to view, including messages that display processing errors in
the HDL source code. 'Level1' allows you to view only the most important HDL messages. 'Level2' allows
you to view most HDL messages, including warning and information based messages. 'Level3' allows you
to view all HDL messages, including warning and information based messages and alerts about potential
design problems or lint errors.
Type
Enumeration
Values
• Level1
• Level2
• Level3
Device Support
This setting can be used in projects targeting any Altera device family.
MNL-Q21005
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Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_LEVEL <value>
Default Value
Level2
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HDL_MESSAGE_OFF
Specifies the list of HDL message ids you want to turn off for this project.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_OFF <value>
HDL_MESSAGE_OFF
99
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HDL_MESSAGE_ON
HDL_MESSAGE_ON
Specifies the list of HDL message ids you want to turn on for this project.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_ON <value>
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