Altera QDRII SRAM Controller MegaCore Function User Manual

101 Innovation Drive
San Jose, CA 95134
www.altera.com

QDRII SRAM Controller

MegaCore Function User Guide

MegaCore Version: 9.1
Document Date: November 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des­ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
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performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap­plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in­formation and before placing orders for products or services.

UG-IPQDRII-8.1

ii MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide

Contents

Chapter 1. About This MegaCore Function

Release Information ............................................................................................................................... 1–1

Device Family Support ......................................................................................................................... 1–1

Features ................................................................................................................................................... 1–2

General Description ............................................................................................................................... 1–2

OpenCore Plus Evaluation .............................................................................................................. 1–3

Performance and Resource Utilization ............................................................................................... 1–4

Chapter 2. Getting Started

Design Flow ............................................................................................................................................ 2–1

QDRII SRAM Controller Walkthrough .............................................................................................. 2–2

Create a New Quartus II Project .................................................................................................... 2–3

Launch IP Toolbench ....................................................................................................................... 2–4

Step 1: Parameterize ......................................................................................................................... 2–5

Step 2: Constraints ............................................................................................................................ 2–7

Step 3: Set Up Simulation ................................................................................................................ 2–7

Step 4: Generate ................................................................................................................................ 2–8

Simulate the Example Design ............................................................................................................ 2–11

Simulate with IP Functional Simulation Models ....................................................................... 2–11

Simulating With the ModelSim Simulator ................................................................................. 2–11

Simulating With Other Simulators .............................................................................................. 2–12

Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 2–17

Edit the PLL .......................................................................................................................................... 2–18

Compile the Example Design ............................................................................................................ 2–19

Program a Device ................................................................................................................................ 2–21

Implement Your Design ..................................................................................................................... 2–21

Set Up Licensing .................................................................................................................................. 2–21

Chapter 3. Functional Description

Block Description ................................................................................................................................... 3–1

Control Logic .................................................................................................................................... 3–2

Resynchronization & Pipeline Logic ............................................................................................. 3–3

Datapath ............................................................................................................................................ 3–5

OpenCore Plus Time-Out Behavior .................................................................................................. 3–10

Interfaces & Signals ............................................................................................................................. 3–10

Interface Description ...................................................................................................................... 3–10

Signals .............................................................................................................................................. 3–22

Device-Level Configuration ............................................................................................................... 3–26

PLL Configuration ......................................................................................................................... 3–26

Example Design .............................................................................................................................. 3–27

Constraints ...................................................................................................................................... 3–29

Altera Corporation MegaCore Version 9.1 iii

Contents

Parameters ............................................................................................................................................ 3–29

Memory ............................................................................................................................................ 3–30

Board & Controller ......................................................................................................................... 3–31

Project Settings ................................................................................................................................ 3–33

MegaCore Verification ........................................................................................................................ 3–34

Simulation Environment ............................................................................................................... 3–34

Hardware Testing ........................................................................................................................... 3–34

Additional Information

Revision History ............................................................................................................................... Info–i

How to Contact Altera ..................................................................................................................... Info–i

Typographic Conventions .............................................................................................................. Info–ii

iv MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide

1. About This MegaCore Function

Release Information

f For more information about this release, refer to the MegaCore IP Library

Device Family Support

Table 1–1 provides information about this release of the Altera® QDRII

SRAM Controller MegaCore® function.

Table 1–1. Release Information

Item Description

Ver si on 9. 1

Release Date November 2009

Ordering Code IP-SRAM/QDRII

Product ID 00A4

Vendor ID 6AF7

Release Notes and Errata.

Altera verifies that the current version of the Quartus® II software
compiles the previous version of each MegaCore function. The MegaCore

IP Library Release Notes and Errata report any exceptions to this

verification. Altera does not verify compilation with MegaCore function
versions older than one release.

MegaCore functions provide either full or preliminary support for target
Altera device families:

■ Full support means the MegaCore function meets all functional and

timing requirements for the device family and may be used in
production designs

■ Preliminary support means the MegaCore function meets all

functional requirements, but may still be undergoing timing analysis
for the device family; it may be used in production designs with
caution.

Altera Corporation MegaCore Version 9.1 1–1
November 2009

Features

Table 1–2 shows the level of support offered by the QDRII SRAM

Controller MegaCore function to each Altera device family.

Table 1–2. Device Family Support

Device Family Support

HardCopy® II

®

Stratix

Stratix

II Full

Stratix

II GX

Stratix GX Full

Other device families (1) No support

Note to Ta b l e 1– 2 :

(1) For more information on support for Stratix III or Stratix IV devices, contact

Altera.

Preliminary

Full

Full

Features

General Description

■ Support for burst of two and four memory type

■ Support for 8-, 18-, and 36-bit QDRII interfaces

■ Support for two-times and four-times data width on the local side

(four-times for burst of four only)

■ Operates at 300 MHz for QDRII and QDRII+ SRAM

■ Automatic concatenation of consecutive reads and writes (narrow

local bus width mode only)

■ Easy-to-use IP Toolbench interface

■ IP functional simulation models for use in Altera-supported VHDL

and Verilog HDL simulators

■ Support for OpenCore Plus evaluation

The QDRII SRAM Controller MegaCore function provides an easy-to-use
interface to QDRII SRAM modules. The QDRII SRAM Controller ensures
that the placement and timing are in line with QDRII specifications.

The QDRII SRAM Controller is optimized for Altera Stratix series. The
advanced features available in these devices allow you to interface
directly to QDRII SRAM devices.

Figure 1–1 shows a system-level diagram including the example design

that the QDRII SRAM Controller MegaCore function creates for you.

1–2 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

Figure 1–1. QDRII SRAM Controller System-Level Diagram

Example Design

Control Logic

(Encrypted)

Pass

or Fail

Example

Driver

Local

Interface

About This MegaCore Function

Clock

Notes to Figure 1–1:

(1) Optional, for Stratix II devices only.
(2) Non-DQS mode only.

System

PLL

DLL (1)

Fedback

Clock

PLL (

2

)

The IP Toolbench-generated example design instantiates a phase-locked
loop (PLL), an optional DLL (for Stratix II devices only), an example
driver, and your QDRII SRAM Controller custom variation. The example
design is a fully-functional example design that can be simulated,
synthesized, and used in hardware. The example driver is a self-test
module that issues read and write commands to the controller and checks
the read data to produce the pass/fail and test complete signals.

Resynchronization

& Pipeline Logic

(Clear Text)

Datapath

(Clear Text)

QDRII SRAM Controller

QDRII
SRAM

Interface

QDRII SRAM

You can replace the QDRII SRAM controller encrypted control logic in
the example design with your own custom logic, which allows you to use
the Altera clear-text resynchronization and pipeline logic and datapath
with your own control logic.

OpenCore Plus Evaluation

With Altera’s free OpenCore Plus evaluation feature, you can perform
the following actions:

Altera Corporation MegaCore Version 9.1 1–3
November 2009 QDRII SRAM Controller MegaCore Function User Guide

Performance and Resource Utilization

■ Simulate the behavior of a megafunction (Altera MegaCore function

or AMPPSM megafunction) within your system

■ Verify the functionality of your design, as well as evaluate its size

and speed quickly and easily

■ Generate time-limited device programming files for designs that

include megafunctions

■ Program a device and verify your design in hardware

You only need to purchase a license for the megafunction when you are
completely satisfied with its functionality and performance, and want to
take your design to production.

f For more information on OpenCore Plus hardware evaluation using the

QDRII SRAM Controller, refer to “OpenCore Plus Time-Out Behavior”

on page 3–10 and AN 320: OpenCore Plus Evaluation of Megafunctions.

Performance
and Resource
Utilization

Table 1–3 shows typical expected performance for the QDRII SRAM

Controller MegaCore function, with the Quartus II software version 9.1.

1 The example driver, which only demonstrates basic read and

write operation, can limit the performance, particularly in wide
interfaces. To improve performance, replace the example driver
or remove it and use the virtual pins on the controller.

Table 1–3. Performance

(MHz)

Device

Stratix II (EP2S60F1020C3) 300

Stratix II GX (EP2SGX30CF780C3) 300

Stratix (EP1S25F780C5) 200

Stratix II and Stratix II GX devices support QDRII SRAM at up to
300 MHz/1,200 Megabits per second (Mbps). Stratix and Stratix GX
devices support QDRII SRAM at up to 200 MHz/800 Mbps. Tables 1–4
through 1–6 show the clock frequency support for each device family,
with the Quartus II software version 9.1.

f

MAX

1–4 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

About This MegaCore Function

1 These numbers apply to both commercial and industrial

devices.

Table 1–4. QDRII SDRAM Maximum Clock Frequency Support in Stratix II & Stratix II GX Devices (1)

Speed Grade

Frequency (MHz)

DLL-Based Implementation PLL-Based Implementation

–3 300 200

–4 200 167

–5 200 167

Notes to Ta b l e 1– 4 :

(1) This analysis is based on the EP2S90F1020 device. Ensure you perform a timing analysis for your chosen FPGA.

Table 1–5. QDRII SRAM Maximum Clock Frequency Supported in Stratix &
Stratix GX Devices (EP1S10 to EP1S40 & EP1SGX10 to EP1SGX40 Devices)

(1)

Speed Grade Frequency (MHz)

–5 200

–6 167

–7 133

Notes to Ta b l e 1– 5 :

(1) This analysis is based on the EP1S25F1020 device. Ensure you perform a timing

analysis for your chosen FPGA.

Table 1–6. QDRII SRAM Maximum Clock Frequency Supported in Stratix
Devices (EP1S60 to EP1S80 Devices) (1)

Speed Grade Frequency (MHz)

–5 167

–6 167

–7 133

Notes to Ta b l e 1– 6 :

(1) This analysis is based on the EP1S60F1020 device. Ensure you perform a timing

analysis for your chosen FPGA.

Altera Corporation MegaCore Version 9.1 1–5
November 2009 QDRII SRAM Controller MegaCore Function User Guide

Performance and Resource Utilization

Table 1–7 shows typical sizes in combinational adaptive look-up tables

(ALUTs) and logic registers for a QDRII SRAM controller with a burst
length of 4 in narrow mode.

Table 1–7. Typical Size (1)

Device Memory Width (Bits)

Stratix II 9 360 598 – 1

18 369 633 1 –

36 390 708 2 –

72 (2 × 36) 459 880 4 –

Notes to Ta b l e 1– 7 :

(1) These sizes are a guide only and vary with different choices of parameters.

Combinational

ALUTs

Logic

Registers

Memory Blocks

M4K M512

1–6 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

2. Getting Started

Design Flow

To evaluate the QDRII SRAM Controller using the OpenCore Plus
feature, include these steps in your design flow:

1. Obtain and install the QDRII SRAM Controller.

The QDRII SRAM Controller is part of the MegaCore IP Library, which is
distributed with the Quartus II software and downloadable from the
Altera website, www.altera.com.

f For system requirements and installation instructions, refer to Altera

Software Installation and Licensing.

Figure 2–1 shows the directory structure after you install the QDRII

SRAM Controller, where <path> is the installation directory. The default
installation directory on Windows is c:\altera\<version>; on Linux it is
/opt/altera<version>.

Figure 2–1. Directory Structure

<path>

Installation directory.

ip

Contains the Altera MegaCore IP Library and third-party IP cores.

altera

Contains the Altera MegaCore IP Library.

common

Contains shared components.

qdrii_sram_controller

Contains the QDRII SRAM Controller MegaCore function files and documentation.

constraints

Contains scripts that generate an instance-specific Tcl script for each instance of
the QDRII SRAM Controller in various Altera devices.

dat

Contains a data file for each Altera device combination that is used by the
Tcl script to generate the instance-specific Tcl script.

doc

Contains the documentation for the QDRII SRAM Controller MegaCore function.

lib

Contains encrypted lower-level design files and other support files.

2. Create a custom variation of the QDRII SRAM Controller MegaCore
function using IP Toolbench.

Altera Corporation MegaCore Version 9.1 2–1
November 2009

QDRII SRAM Controller Walkthrough

1 IP Toolbench is a toolbar from which you quickly and easily

3. Implement the rest of your design using the design entry method of
your choice.

4. Use the IP Toolbench-generated IP functional simulation model to
verify the operation of your design.

f For more information on IP functional simulation models, refer to the

Simulating Altera IP in Third-Party Simulation Tools chapter in volume 3 of

the Quartus II Handbook.

5. Edit the PLL(s).

6. Use the Quartus II software to add constraints to the example
design and compile the example design.

7. Perform gate-level timing simulation, or if you have a suitable
development board, you can generate an OpenCore Plus
time-limited programming file, which you can use to verify the
operation of the example design in hardware.

view documentation, specify parameters, and generate all
of the files necessary for integrating the parameterized
MegaCore function into your design.

8. Either obtain a license for the QDRII SRAM controller MegaCore
function or replace the encrypted QDRII SRAM controller control
logic with your own logic and use the clear-text data path.

1 If you obtain a license for the QDRII SRAM controller, you

must set up licensing.

9. Generate a programming file for the Altera device(s) on your board.

10. Program the Altera device(s) with the completed design.

QDRII SRAM
Controller
Walkthrough

2–2 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

This walkthrough explains how to create a QDRII SRAM controller using
the Altera QDRII SRAM controller IP Toolbench and the Quartus II
software. When you are finished generating a custom variation of the
QDRII SRAM Controller MegaCore function, you can incorporate it into
your overall project.

1 IP Toolbench only allows you to select legal combinations of

parameters, and warns you of any invalid configurations.

This walkthrough requires the following steps:

Getting Started

■ “Create a New Quartus II Project” on page 2–3

■ “Launch IP Toolbench” on page 2–4

■ “Step 1: Parameterize” on page 2–5

■ “Step 2: Constraints” on page 2–7

■ “Step 3: Set Up Simulation” on page 2–7

■ “Step 4: Generate” on page 2–8

Create a New Quartus II Project

Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the QDRII SRAM Controller user library. To create a
new project, follow these steps:

You need to create a new Quartus II project with the New Project Wizard,
which specifies the working directory for the project, assigns the project
name, and designates the name of the top-level design entity. To create a
new project follow these steps:

1. Choose Programs > Altera > Quartus II <version> (Windows Start
menu) to run the Quartus II software. Alternatively, you can use the
Quartus II Web Edition software.

2. Choose New Project Wizard (File menu).

3. Click Next in the New Project Wizard Introduction page (the
introduction page does not display if you turned it off previously).

4. In the New Project Wizard: Directory, Name, Top-Level Entity
page, enter the following information:

a. Specify the working directory for your project. For example,

this walkthrough uses the c:\altera\temp\qdr_project
directory.

b. Specify the name of the project. This walkthrough uses project

for the project name.

1 The Quartus II software automatically specifies a top-level

design entity that has the same name as the project. Do not
change it.

5. Click Next to close this page and display the New Project Wizard:
Add Files page.

Altera Corporation MegaCore Version 9.1 2–3
November 2009 QDRII SRAM Controller MegaCore Function User Guide

QDRII SRAM Controller Walkthrough

1 When you specify a directory that does not already exist, a

6. If you installed the MegaCore IP Library in a different directory
from where you installed the Quartus II software, you must add the
user libraries:

a. Click User Libraries.

b. Type <path>\ip into the Library name box, where <path> is the

c. Click Add to add the path to the Quartus II project.

d. Click OK to save the library path in the project.

7. Click Next to close this page and display the New Project Wizard:
Family & Device Settings page.

8. On the New Project Wizard: Family & Device Settings page,
choose the target device family in the Family list.

9. The remaining pages in the New Project Wizard are optional. Click
Finish to complete the Quartus II project.

message asks if the specified directory should be created.
Click Yes to create the directory.

directory in which you installed the QDRII SRAM Controller.

You have finished creating your new Quartus II project.

Launch IP Toolbench

To launch IP Toolbench in the Quartus II software, follow these steps:

1. Start the MegaWizard® Plug-In Manager by choosing MegaWizard
Plug-In Manager (Tools menu). The MegaWizard Plug-In Manager
dialog box displays.

1 Refer to Quartus II Help for more information on how to

use the MegaWizard Plug-In Manager.

2. Specify that you want to create a new custom megafunction
variation and click Next.

3. Expand the Interfaces > Memory Controllers directory then click
QDRII SRAM Controller-v8.1.

4. Select the output file type for your design; the wizard supports
VHDL and Verilog HDL.

2–4 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

Getting Started

5. The MegaWizard Plug-In Manager shows the project path that you
specified in the New Project Wizard. Append a variation name for
the MegaCore function output files <project path>\<variation name>.

1 The <variation name> must be a different name from the

project name and the top-level design entity name.

6. Click Next to launch IP Toolbench.

Step 1: Parameterize

To parameterize your MegaCore function, follow these steps:

1. Click Step 1: Parameterize in IP Toolbench.

f For more information on the parameters, refer to “Parameters” on

page 3–29).

2. Set the memory type:

a. Choose the Memory device.

b. Select either QDRII or QDRII+.

c. Set the Clock speed.

d. Choose the Voltage.

e. Choose the Burst length.

f. Choose the Data bus width.

g. Choose the Address bus width.

h. Choose the Memory Latency.

i. Select the Narrow mode or Wide mode to set the local bus

width.

3. Set the memory interface.

a. Set Device width.

b. Set Device depth.

c. Turn off Use ALTDDIO pin, if you are targeting HardCopy II

devices.

Altera Corporation MegaCore Version 9.1 2–5
November 2009 QDRII SRAM Controller MegaCore Function User Guide

QDRII SRAM Controller Walkthrough

4. Click Board & Controller tab or Next.

f For more information on board and controller parameters, refer to

“Board & Controller” on page 3–31.

5. Choose the number of pipeline registers.

6. To set the read latency, turn on Manual read latency setting and
specify the latency at Set latency to clock cycle.

7. Turn on the appropriate capture mode—DQS or non-DQS capture
mode. If you turn off Enable DQS mode (non-DQS capture mode),
you can turn on Use migratable bytegroups.

8. Enter the pin loading for the FPGA pins.

9. Click Project Settings tab or Next.

f For more information on the project settings, refer to “Project Settings”

on page 3–33.

10. Altera recommends that you turn on Automatically apply QDRII
SRAM controller-specific constraints to the Quartus II project so
that the Quartus II software automatically applies the constraints
script when you compile the example design.

11. En sure Update the example design that instantiates the QDRII
SRAM controller variation is turned on, for IP Toolbench to
automatically update the example design file.

12. Turn off Update example design system PLL, if you have edited the
PLL and you do not want the wizard to regenerate the PLL when
you regenerate the variation.

1 The first time you create a custom variation, you must turn

on Update example design system PLL.

13. The constraints script automatically detects the hierarchy of your
design. The constraints script analyzes and elaborates your design
to automatically extract the hierarchy to your variation. To prevent
the constraints script analyzing and elaborating your design, turn
on Enable hierarchy control, and enter the correct hierarchy path to
your variation. The hierarchy path is the path to your QDRII SRAM
controller, without the top-level name. Figure 2–2 shows the
following example hierarchy:

my_system:my_system_inst|sub_system:sub_system_inst|

2–6 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

Figure 2–2. System Naming

QDRII SRAM

Other Logic

PLL

QDRII SRAM

Interface

example_top

Example Design

QDRII SRAM Controller

my_system_inst

System

sub_system_inst

Subsystem

Getting Started

14. IP Toolbench uses a prefix (e.g., qdrii_) for the names of all memory
interface pins. Enter a prefix for all memory interface pins
associated with this custom variation.

15. Click Finish.

Step 2: Constraints

To choose the constraints for your device, follow these steps:

1. Click Step 2: Constraints in IP Toolbench.

2. Choose the positions on the device for each of the QDRII SRAM
byte groups. To place a byte group, select the byte group in the
drop-down box at your chosen position.

1 The floorplan matches the orientation of the Quartus II

floorplanner. The layout represents the die as viewed from

Step 3: Set Up Simulation

An IP functional simulation model is a cycle-accurate VHDL or Verilog
HDL model produced by the Quartus II software. The model allows for
fast functional simulation of IP using industry-standard VHDL and
Verilog HDL simulators.

Altera Corporation MegaCore Version 9.1 2–7
November 2009 QDRII SRAM Controller MegaCore Function User Guide

above. A byte group consists of a cq pin and a number of q
pins (the same number as the data width).

QDRII SRAM Controller Walkthrough

c You may only use these simulation model output files for

To generate an IP functional simulation model for your MegaCore
function, follow these steps:

1. Click Step 3: Set Up Simulation in IP Toolbench.

2. Turn on Generate Simulation Model.

3. Choose the language in the Language list.

4. Some third-party synthesis tools can use a netlist that contains only
the structure of the MegaCore function, but not detailed logic, to
optimize performance of the design that contains the MegaCore
function. If your synthesis tool supports this feature, turn on
Generate netlist.

5. Click OK.

Step 4: Generate

simulation purposes and expressly not for synthesis or any
other purposes. Using these models for synthesis will create a
nonfunctional design.

1. To generate your MegaCore function, click Step 4: Generate in IP
To ol be n ch .

1 The Quartus II IP File (.qip) is a file generated by the

MegaWizard interface, and contains information about a
generated IP core. You are prompted to add this .qip file to the
current Quartus II project at the time of file generation. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the core or system in the
Quartus II compiler. Generally, a single .qip file is generated for
each MegaCore function or system in the Quartus II compiler.

2–8 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

Getting Started

Table 2–1 describes the generated files and other files that may be in your

project directory. The names and types of files specified in the IP
Toolbench report vary based on whether you created your design with
VHDL or Verilog HDL

Table 2–1. Generated Files (Part 1 of 2) (1), (2) & (3)

Filename Description

<variation name>.bsf Quartus II symbol file for the MegaCore function

variation. You can use this file in the Quartus II block
diagram editor.

<variation name>.html MegaCore function report file.

<variation name>.vhd, or .v A MegaCore function variation file, which defines a

VHDL or Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.

<variation name>_bb.v Verilog HDL black-box file for the MegaCore function

variation. Use this file when using a third-party EDA tool
to synthesize your design.

<variation name>_auk_qdrii_sram.vhd or .v File that instantiates the control logic and the datapath.

<variation
name>_auk_qdrii_sram_addr_cmd_reg.vhd or .v

<variation
name>_auk_qdrii_sram_avalon_controller_ipfs_

wrap.vhd or .v

<variation
name>_auk_qdrii_sram_avalon_controller_ipfs_

wrap.vho or .vo

<variation
name>_auk_qdrii_sram_capture_group_wrapper.

vhd or .v

<variation name>_auk_qdrii_sram_clk_gen.vhd or .vThe clock output generators.

The address and command output registers.

File that instantiates the controller.

VHDL or Verilog HDL IP functional simulation model.

File that contains all the capture group modules (CQ and
CQN group modules and read capture registers).

<variation
name>_auk_qdrii_sram_cq_cqn_group.vhd or .v

<variation name>_auk_qdrii_sram_datapath.vhd

or .v

<variation name>_auk_qdrii_sram_dll.vhd or .v DLL.

<variation
name>_auk_qdrii_sram_example_driver

.vhd or .v

<variation
name>_auk_qdrii_sram_read_group.vhd or .v

Altera Corporation MegaCore Version 9.1 2–9
November 2009 QDRII SRAM Controller MegaCore Function User Guide

The CQ and CQN module.

Datapath.

The example driver.

The read capture registers.

QDRII SRAM Controller Walkthrough

Table 2–1. Generated Files (Part 2 of 2) (1), (2) & (3)

Filename Description

<variation
name>_auk_qdrii_sram_pipe_resynch_wrapper.v

hd or .v

<variation
name>_auk_qdrii_sram_pipeline_addr_cmd.vhd

or .v

<variation
name>_auk_qdrii_sram_pipeline_rdata.vhd or .v

<variation
name>_auk_qdrii_sram_pipeline_wdata.vhd or .v

<variation
name>_auk_qdrii_sram_read_group.vhd or .v

<variation
name>_auk_qdrii_sram_resynch_reg.vhd or .v

<variation
name>_auk_qdrii_sram_train_wrapper.vhd or .v

<variation
name>_auk_qdrii_sram_test_group.vhd or .v

<variation
name>_auk_qdrii_sram_write_group.vhd or .v

<variation name>.qip Contains Quartus II project information for your

<top-level name>.vhd or .v (1) Example design file.

add_constraints_for_

qdrii_pll_stratixii.vhd or .v Stratix II PLL.

<variation name>.tcl The add constraints script.

File that includes the write data pipeline and includes the
address and command, read command, write data, and
write command pipeline.

Address and command pipeline.

Read data pipeline.

Write data pipeline.

The read registers.

The resynchronization FIFO buffers.

File that contains all the training group modules.

Training module, which realigns latency.

The write registers.

MegaCore function variations.

Notes to Ta b l e 2– 1 :

(1) <top-level name> is the name of the Quartus II project top-level entity.
(2) <variation name> is the name you give to the controller you create with the Megawizard.
(3) IP Tooblench replaces the string qdrii_sram with qdriiplus_sram for QDRII+ SRAM controllers.

2. After you review the generation report, click Exit to close IP
To ol be n ch .

You have finished the walkthrough. Now, simulate the example design
(refer to “Simulate the Example Design” on page 2–11), edit the PLL(s)
(refer to “Edit the PLL” on page 2–18), and compile (refer to “Compile the

Example Design” on page 2–19).

2–10 MegaCore Version 9.1 Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide November 2009

Getting Started

Simulate the Example Design

f For more information on the testbench, refer to “Example Design” on

This section describes the following simulation techniques:

■ Simulate with IP Functional Simulation Models

■ Simulating With the ModelSim Simulator

■ Simulating With Other Simulators

■ Simulating in Third-Party Simulation Tools Using NativeLink

Simulate with IP Functional Simulation Models

You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.

page 3–27.

You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. The instructions for
the ModelSim simulator are different to other simulators.

Simulating With the ModelSim Simulator

Altera supplies a generic memory model, lib\qdrii_model.v, which
allows you to simulate the example design with the ModelSim simulator.
To simulate the example design with the ModelSim® simulator, follow
these steps:

1. Copy the generic memory model to the <directory name>\testbench
directory.

2. Open the memory model and the testbench (<top-level
name>_vsim.v or .vhd) in a text editor and ensure the signal names
have the same capitalization in both files.

3. Start the ModelSim-Altera simulator.

4. Change your working directory to your IP Toolbench-generated file
directory <directory name>\testbench\modelsim.

5. To simulate with an IP functional simulation model simulation, type
the following command:

source <variation name>_vsim.tcl

Altera Corporation MegaCore Version 9.1 2–11
November 2009 QDRII SRAM Controller MegaCore Function User Guide

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