PCB designers must estimate the number, value, and type of decoupling capacitors
required to develop an efficient PCB decoupling strategy during the early design
phase, without going through extensive pre-layout simulations. The Altera’s Power
Delivery Network (PDN) tool provides these critical pieces of information.
The PDN tool is a Microsoft Excel-based spreadsheet tool used to calculate an
impedance profile based on user inputs. For a given power supply, the spreadsheet
requires only basic design information, such as the board stackup, transient current
information, and ripple specifications to come up with the impedance profile and the
optimum number of capacitors to meet the desired impedance target. The results
obtained through the spreadsheet tool are intended only as a preliminary estimate
and not as a specification. For an accurate impedance profile, Altera
post-layout simulation approach using any of the available EDA tools, such as Sigrity
PowerSI, Ansoft SIWave, Cadence Allegro PCB PI, etc.
®
recommends a
This version of the PDN tool is a general purpose tool for helping with the PCB
decoupling design. Altera has family-specific PDN tools for its FPGA devices that
help reduce over-design in PCB decoupling by taking the effects of device-related
parameters into consideration.
fFor the availability of the PDN tool that targets your device, refer to the Altera website
at www.altera.com.
Application of the Tool
The purpose of the tool is to design a robust power delivery network by determining
an optimum number, type, and value of decoupling capacitors required to meet the
desired target impedance up to the target frequency. This spreadsheet tool is useful
for exploring the various what-if scenarios during the early design phase, without
extensive and time consuming pre-layout analysis.
PDN Decoupling Methodology Review
The PDN tool is based on a lumped equivalent model representation of the power
delivery network topology. Figure 1–1 shows a schematic representation of the circuit
topology, modeled as part of the tool.
PDN Circuit Topology
For first order analysis, the voltage regulator module (VRM) can be simply modeled
as a series-connected resistor and inductor, as shown in Figure 1–1. At low
frequencies, up to approximately 50 KHz, the VRM has a very low impedance and is
capable of responding to the instantaneous current requirements of the FPGA. The
ESR and ESL values can be obtained from the VRM manufacturer.
1–2Chapter 1: Power Delivery Network (PDN) Tool User Guide
Altera FPGA
Device
BGR Via
R and L
Spreading
R and L
Planar
R and C
Rp
Cp
LvRvLsRs
LmntNLmnt3Lmnt2Lmnt1
LcN
CcN
RcN
Lc3
Cc3
Rc3
Lc2
Cc2
Rc2
Lc1
Cc1
Rc1
Decoupling
CAP Model
LvrmRvrm
VRM
VRM Model
Setting Up the PDN Tool
Beyond lower frequencies, the VRM impedance is primarily inductive, making it
incapable of meeting the transient current requirement. The on-board discrete
decoupling capacitors must provide the required low impedance from low to high
frequencies, depending on the capacitor intrinsic parasitics (R
capacitor mounting inductance (L
). The interplanar capacitance between the
mntN
, CcN, LcN) and the
cN
power-ground planes typically has lower inductance than the discrete decoupling
capacitor network, making it more effective at higher frequencies (tens of MHz). The
effectiveness of the decoupling capacitors is limited by the PCB spreading inductance
and the ball grid array (BGA) via inductance that a given capacitor encounters with
respect to the FPGA. To simplify the circuit topology, the PDN tool models the
distributed nature of PCB spreading, BGA inductance, and resistance with a single
lumped inductor and resistor.
Figure 1–1. PDN Circuit Topology
Setting Up the PDN Tool
Figure 1–2 shows the various tabs of the PDN tool spreadsheet.
Figure 1–2. Tabs in the PDN Tool
Tab le 1– 1 describes the PDN tool tabs.
Table 1–1. Description of Tabs in PDN Tool (Sheet 1 of 2)
TabDescription
Release NotesThis tab provides the legal disclaimers, the revision history of the tool, and the user
agreement.
IntroductionThis tab shows the schematic representation of the circuit that is modeled as part of the PDN
tool. The tab also provides a brief Quick Start instruction on using the tool.
Decap SelectionThis tab provides an interface to input the various parameters and observe the resultant
impedance profile. This is the main user interface to the tool.
Chapter 1: Power Delivery Network (PDN) Tool User Guide1–3
Setting Up the PDN Tool
Table 1–1. Description of Tabs in PDN Tool (Sheet 2 of 2)
TabDescription
LibraryThis tab points to various libraries (capacitor, dielectric materials, and so on) that are called
by other tabs. You can change the default values listed as part of these libraries.
BGA ViaThis tab provides an interface to calculate the BGA mounting inductance based on
design-specific via parameters and the number of vias.
Plane Cap This tab provides an interface to calculate the plane capacitance based on design-specific
parameters.
Cap MountThis tab provides an interface to input design-specific parameters for calculating the
capacitor mounting inductance for two different capacitor orientations (Via on Side [VOS]
and Via on End [VOE]).
X2Y MountThis tab provides an interface to input design-specific parameters for calculating the
capacitor mounting inductance for X2Y type capacitors.
BOMThe Bill of Materials (BOM) tab provides a summary of the final capacitor count required to
meet the target impedance.
The PDN tool is designed to provide an accurate estimate on the number and types of
capacitors required to design a robust PDN, regardless of where you are in the design
phase. The accuracy of the results is highly dependent on the user inputs for the
various parameters.
1You can explore the tool by following the Quick Start instructions listed in the
Introduction tab.
In the pre-layout phase of the design cycle, when no specific information about the
board stackup and board layout is known, you can follow the “Pre-Layout
Instructions” on page 1–3 to explore the solution space when finalizing key design
parameters, such as stackup, plane size, capacitor count, capacitor orientation, and so
on.
If you have finalized the board stackup and have access to board database and layout
information, you can step through the various tabs and enter the required information
to arrive at a very accurate decoupling scheme.
Pre-Layout Instructions
In the pre-layout phase, you can ignore the Plane Cap, Cap Mount, X2Y Mount, and
BGA Via tabs and go directly to the Library tab when you do not have layout
information. Figure 1–3 shows the fields located in the Library tab for entering the
various parameters.
If available, enter the values shown in Figure 1–3 in the Library tab. To use the default
values, go directly to the Decap Selection tab to begin the analysis.
1–4Chapter 1: Power Delivery Network (PDN) Tool User Guide
Setting Up the PDN Tool
Figure 1–3. Library Tab
Notes to Figure 1–3:
The numbers in Figure 1–3 correspond to the follwing steps 1, 2, 3, 4, 5.
(1) Enter the ESR, ESL, and L
(2) Enter the effective BGA via (loop) parasitics for the power supply being decoupled.
(3) Enter the plane capacitance seen by the power/ground plane pair on the board for the power supply under Plane Cap.
(4) Enter the VRM parasitics, if available, under the Custom row.
(5) Enter the effective spreading inductance seen by the decoupling capacitors in the Custom row.
values for the capacitors under the Custom field.
mount
For more information on the Decap Selection tab, refer to “Decap Selection Tab” on