Altera POS-PHY Level 4 IP Core User Manual

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DecemberPOS-PHY Level 4 IP Core User Guide

POS-PHY Level 4 IP Core

User Guide

101 Innovation Drive San Jose, CA 95134

www.altera.com

c The POS-PHY Level 4 IP Core is scheduled for product obsolescence and discontinued

support as described in PDN1410. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s

Intellectual Property website.

UG-IPPOSPHY4

Document last updated for Altera Complete Design Suite version:

Document publication date:

December 2014

14.1

Copyright © 2014 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries. All other words and logos identified as trademarks and/or service marks are the property of Altera Corporation or their respective owners. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

The Altera® POS-PHY Level 4 MegaCore® function is an IP core that performs highspeed cell and packet transfers between physical and link-layer devices.

Release Information

Tab le 1– 1 provides information about this release of the Altera® POS-PHY Level 4 IP

core.

Table 1–1. POS-PHY Level 4 IP Core Release Information

Version 14.1

Release Date December 2014

Ordering Code IP-POSPHY4

Product ID 0088

Vendor ID 6AF7

1. About This IP Core

Item Description

f For more information about this release, refer to the MegaCore IP Library Release Notes

and Errata.

Altera verifies that the current version of the Quartus previous version of each IP core. The MegaCore IP Library Release Notes and Errata report any exceptions to this verification. Altera does not verify compilation with IP core versions older than one release.

Device Family Support

IP cores can provide the types of support for target Altera device families described in

Tab le 1– 2.

Table 1–2. Altera IP Core Device Support Levels

Preliminary—The core is verified with preliminary timing models for this device family. The core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final—The core is verified with final timing models for this device family. The core meets all functional and timing requirements for the device family and can be used in production designs.

FPGA Device Families

II software compiles the

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

1–2 Chapter 1: About This IP Core

Features

Tab le 1– 3 shows the level of support offered by the POS-PHY Level 4 IP core to each

Altera device family.

Table 1–3. Device Family Support

Device Family Support

II GX Preliminary

Arria

Arria II GZ Preliminary

Cyclone IV Preliminary

Stratix IV Full

Stratix V Preliminary

Other device families No support

Features

■ Compliant with all applicable standards, including:

■ Optical Internetworking Forum (OIF), System Packet Interface Level 4 (SPI-4)

Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.1, October 2003.

■ PMC-Sierra Inc., POS-PHY

Specification for OC-192 SONET/SDH and 10 GB/s Ethernet Applications, Issue 5

(Draft): June 2000.

Level 4 A Saturn Packet and Cell Interface

■ Stratix III, Stratix IV, and Stratix V device support up to 1,250 Mbps and Stratix II

device support up to 1,040 Mbps, including integrated dynamic phase alignment (DPA) hardware module

■ Cyclone III, device support up to 622 Mbps for 64 bit data path; support up to 250

Mbps for 32-bit data path width

■ Configurable data path width—affecting the IP core size and speed—for various

performance requirements and applications:

■ 128 bits

■ 64 bits

■ 32 bits (quarter rate)

■ Supports up to 256 ports

■ Fixed start of packet (SOP) alignment to the most significant byte lane eases

subsequent packet processing

■ First-in first-out (FIFO) buffer status management and indications

■ Configurable FIFO buffer modes

■ Shared buffer with embedded addressing

■ Individual buffers

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 1: About This IP Core 1–3

FPGA

SPI-4.2 Interface

Switch

Interface

User Packet

Processing

OC-192

POS Framer

10 GbitE MAC

Switch

Fabri c

Atlantic Interface

POS-PHY Level 4

Receiver

POS-PHY Level 4

Transmitter

OC-192 or

10 GbitE

FPGA

Framer or MAC

Logic

Packet Classifier

SPI-4.2 InterfaceAtlantic Interface

POS-PHY Level 4

Receiver

POS-PHY Level 4

Transmitter

General Description

■ Error detection and handling

■ Protocol checking—SPI-4.2 datapath state machine check and repair

■ Atlantic FIFO buffer overflow handling

■ Status framing hysteresis (good and bad thresholds)

■ DIP-4 hysteresis (good and bad thresholds)

■ IP functional simulation models for use in Altera-supported VHDL and Verilog

HDL simulators

■ I-Tested certification

General Description

The packet over SONET/SDH physical layer (POS-PHY) Level 4 interface, first developed by the SATURN

Development Group, was adopted by the Optical

Internetworking Forum (OIF) as the System Packet Interface Level 4—Phase 2 (SPI-

4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.

The POS-PHY Level 4 IP core uses the SPI-4.2 interface for high-speed cell and packet transfers between physical (PHY) and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution) and can be a PHY-link, link-link, linkPHY, or PHY-PHY connection in multi-gigabit applications, including: asynchronous transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel Gigabit and Fast Ethernet.

In compliance with the SPI-4.2 interface specification, the POS-PHY Level 4 IP core allows you to implement transmit and receive functions.

Figure 1–1 shows a full-duplex POS-PHY Level 4 IP core configured for the link layer

in an Altera FPGA device.

Figure 1–1. POS-PHY Level 4 IP Core as Link Layer Configuration

Figure 1–2 shows a full-duplex POS-PHY Level 4 IP core configured for the PHY layer

in an Altera FPGA device.

Figure 1–2. POS-PHY Level 4 IP Core as PHY Layer Configuration

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

1–4 Chapter 1: About This IP Core

Transmitter Source

Receiver

Sink

tsclk

tstat[1:0]

tdclk

tctl

tdat[15:0]

rsclk

rstat[1:0]

rdclk

rctl

rdat[15:0]

General Description

Interfaces & Protocols

The following three interfaces support the POS-PHY Level 4 IP core:

■ SPI-4.2 interface

■ Atlantic

■ Av al on

You can use multiple Atlantic interfaces, but the SPI-4.2 interface only supports a single transmitter and a single receiver.

SPI-4.2 Interface

The SPI-4.2 interface is an external interface protocol developed by the Optical Internetworking Forum (OIF). The SPI-4.2 interface features a high-speed data portion and a FIFO buffer status portion. The high-speed portion comprises a 16-bit data bus, a 1-bit control line, and a double data rate (DDR) clock. The FIFO buffer status portion comprises a 2-bit status channel and a clock.

Figure 1–3 shows a full-duplex SPI-4.2 configuration.

Figure 1–3. SPI-4.2 Top-Level View

™

interface

Memory-Mapped (Avalon-MM) interface.

f For further information on this interface, refer to the System Packet Interface Level 4

(SPI-4) Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices,

available at www.oiforum.com.

Atlantic Interface

The Atlantic interface is an Altera-developed synchronous protocol supporting both packets and cells. The POS-PHY Level 4 IP core is an Atlantic interface slave that transfers packets to or from the user-side logic. The Atlantic interface provides a connection between the FIFO buffer and user logic.

f For further information on this interface, refer to the Atlantic Interface Functional

Specification.

Avalon-MM Interface

The Altera Avalon-MM interface is a simple bus architecture that connects on-chip processors (or external processor interfaces) and peripherals. The Avalon-MM interface specifies the port connections between master and slave components, and specifies the timing by which these components communicate.

All Avalon-MM signals are synchronized to the Avalon-MM clock ( This synchronization simplifies the relevant timing behavior of the Avalon-MM interface and facilitates integration with high-speed peripherals.

rav_clk/tav_clk

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 1: About This IP Core 1–5

IP Core Verification

In this version of the POS-PHY Level 4 IP core, the Avalon-MM module is a discrete unit that is instantiated with the parameter editor, when Asymmetric Port Support is turned on.

f For further information on this interface, refer to the Avalon Interface Specifications.

IP Core Verification

The POS-PHY Level 4 IP core has been rigorously tested and verified in hardware for different platforms and environments. Each environment has individual test suites that are designed to cover the following five categories of testability:

■ Sanity

■ Flow Control

■ Error Management

■ Performance

■ Stress

These test suites contain several testbenches that are grouped and focused on testing specific features of the POS-PHY Level 4 IP core. These individual testbenches set unique parameters for each specific feature test.

Results of the hardware verification tests are gathered in I-tested reports available for different ASSP devices. For example, SPI-4.2 Interoperability with PMC-Sierra’s S/UNI 9953 and SPI-4.2 Interoperability with PMC-Sierra’s S/UNI 10×GE (PM3388).

f For these reports, contact your local Altera sales representative or FAE.

Performance and Resource Utilization

Tab le 1– 4 lists the resources and internal speeds for variations using the shared buffer

with embedded addressing mode.

Tab le 1– 5 lists the resources and internal speeds for a selection of variations using the

individual buffers mode.

All of the results use the Quartus II software version 8.1 for the following devices:

■ Stratix IV GX (EP4SGX70DF29C3 and EP4SGX230DF29C3ES)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

1–6 Chapter 1: About This IP Core

Performance and Resource Utilization

Table 1–4. Performance—Shared Buffer With Embedded Addressing Mode—Stratix IV Devices

Data Flow

Direction

Receiver

Transmitter

Parameters

Data Path

Width (bits)

Number of

Ports

ALUTs

Logic

Registers

Memory

Blocks

(M9K)

EP4SGX70

DF29C3

MAX

clk

(MHz)

32 1 1,190 1,294 6 204 195

64 1 1,387 1,820 16 261 284

128 1 2,215 2,741 30 186 207

32 4 1,198 1,300 6 199 156

64 4 1,398 1,826 16 273 273

128 4 2,221 2,742 30 195 195

32 10 1,138 1,249 7 213 163

64 10 1,396 1,782 18 281 270

128 10 2,273 2,709 33 187 160

32 4 1,049 1,085 5 192 185

64 4 1,032 1,454 9 262 232

128 4 1,178 1,464 17 175 181

32 10 1,023 1,119 5 178 163

64 10 1,057 1,601 9 260 225

128 10 1,331 1,770 17 190 166

EP4SGX230

DF29C3ES

Table 1–5. Performance—Individual Buffers Mode—Stratix IV Devices

Parameters

Logic

Registers

Data Flow

Direction

Data Path

Width (bits)

Number of

ALUTs

Ports

32 4 2,245 2,427 21 182 159

64 4 2,514 2,800 40 270 268

Receiver

128 4 3,833 4,160 78 165 149

32 10 4,070 4,529 45 140 144

64 10 4,823 4,830 88 255 254

32 1 1,155 1,213 6 165 176

64 1 1,309 1,784 10 245 182

128 1 1,710 2,245 18 177 171

Transmitter

32 4 2,563 2,524 18 130 151

64 4 2,726 2,997 34 183 212

128 4 3,430 3,778 66 166 153

32 10 5,210 4,789 42 120 118

64 10 5,733 5,188 82 153 213

Memory

Blocks

(M9K)

EP4SGX70

DF29C3

MAX

clk

(MHz)

EP4SGX230

DF29C3ES

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 1: About This IP Core 1–7

acds

quartus - Contains the Quartus II software

ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

Installing and Licensing IP Cores

The Quartus II software includes the Altera IP Library. The library provides many useful IP core functions for production use without additional license. You can fully evaluate any licensed Altera IP core in simulation and in hardware until you are satisfied with its functionality and performance.

Some Altera IP cores, such as MegaCore separate license for production use. After you purchase a license, visit the Self Service

Licensing Center to obtain a license number for any Altera product. For additional

information, refer to Altera Software Installation and Licensing.

Figure 1–4. IP core Installation Path

1 The default installation directory on Windows is <drive>:\altera\<version number>;

on Linux it is <home directory>/altera/<version number>.

functions, require that you purchase a

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

■ Simulate the behavior of a licensed IP core in your system.

■ Verify the functionality, size, and speed of the IP core quickly and easily.

■ Generate time-limited device programming files for designs that include IP cores.

■ Program a device with your IP core and verify your design in hardware.

OpenCore Plus evaluation supports the following two operation modes:

■ Untethered—run the design containing the licensed IP for a limited time.

■ Tethered—run the design containing the licensed IP for a longer time or

indefinitely. This requires a connection between your board and the host computer.

All IP cores using OpenCore Plus in a design time out simultaneously when any IP core times out.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

1–8 Chapter 1: About This IP Core

Installing and Licensing IP Cores

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Design Flow

Specify Parameters

Compile Design

Program Device

Simulate with

Te st bench

Apply Timing

Constraints

2. Getting Started

Figure 2–1 shows the stages for creating a system with the POS-PHY Level 4 IP core

and the Quartus

Figure 2–1. Design Flow

II software. The sections in this chapter describe each stage.

IP Catalog and Parameter Editor

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

The Quartus II IP Catalog (Too ls > I P C a t a l o g) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

The IP Catalog automatically displays the IP cores available for your target device. Double-click any IP core name to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify your IP variation name, optional ports, architecture features, and output file generation options. The parameter editor generates a top-level .qsys or .qip file representing the IP core in your project. Alternatively, you can define an IP variation without an open Quartus II project. When no project is open, select the Device Family directly in IP Catalog to filter IP cores by device.

1 The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog

includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog.

Use the following features to help you quickly locate and select an IP core:

2–2 Chapter 2: Getting Started

Using the Parameter Editor

■ Filter IP Catalog to Show IP for active device family or Show IP for all device

families.

■ Search to locate any full or partial IP core name in IP Catalog. Click Search for

Partner IP, to access partner IP information on the Altera website.

■ Right-click an IP core name in IP Catalog to display details about supported

devices, installation location, and links to documentation.

Figure 2–2. Quartus II IP Catalog

Search and filter IP for your target device

Double-click to customize, right-click for information

1 The IP Catalog and parameter editor replace the MegaWizard

the Quartus II software. The Quartus II software may generate messages that refer to the MegaWizard Plug-In Manager. Substitute “IP Catalog and parameter editor” for “MegaWizard Plug-In Manager” in these messages.

Using the Parameter Editor

The parameter editor helps you to configure your IP variation ports, parameters, architecture features, and output file generation options:

■ Use preset settings in the parameter editor (where provided) to instantly apply

preset parameter values for specific applications.

■ View port and parameter descriptions and links to detailed documentation.

™

Plug-In Manager in

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 2: Getting Started 2–3

View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

Legacy parameter editors

Upgrading Outdated IP Cores

■ Generate testbench systems or example designs (where provided).

Figure 2–3. IP Parameter Editors

Upgrading Outdated IP Cores

IP cores generated with a previous version of the Quartus II software may require upgrade before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to identify and upgrade outdated IP cores.

The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or unsupported for specific IP cores in your design. Most Altera IP cores support one-click, automatic simultaneous upgrade. You can individually migrate IP cores unsupported by auto-upgrade.

The Upgrade IP Components dialog box also reports legacy Altera IP cores that support compilation-only (without modification), as well as IP cores that do not support migration. Replace unsupported IP cores in your project with an equivalent Altera IP core or design logic.Upgrading IP cores changes your original design files.

Before you begin

■ Migrate your Quartus II project containing outdated IP cores to the latest version

of the Quartus II software. In a previous version of the Quartus II software, click Project > Archive Project to save the project. This archive preserves your original design source and project files after migration. le paths in the archive must be relative to the project directory. File paths in the archive must reference the IP variation .v or .vhd file or .qsys file, not the .qip file.

■ Restore the project in the latest version of the Quartus II software. Click Project >

Restore Archived Project. Click Ok if prompted to change to a supported device

or overwrite the project database.

To upgrade outdated IP cores, follow these steps:

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP core variation.

2–4 Chapter 2: Getting Started

Displays upgrade status for all IP cores in the Project

Upgrades all IP core that support “Auto Upgrade”

Upgrades individual IP cores unsupported by “Auto Upgrade”

Checked IP cores

support “Auto Upgrade”

Successful “Auto Upgrade”

Upgrade unavailable

Double-click to individually migrate

Upgrading Outdated IP Cores

1 File paths in a restored project archive must be relative to the project

directory and you must reference the IP variation .v or .vhd file or .qsys file, not the .qip file.

2. Click Project > Upgrade IP Components. The Upgrade IP Components dialog box displays all outdated IP cores in your project, along with basic instructions for upgrading each core.

3. To simultaneously upgrade all IP cores that support automatic upgrade, click

Perform Automatic Upgrade. The IP cores upgrade to the latest version. The Status and Ve rs i on columns reflect the update.

Figure 2–4. Upgrading IP Cores

Upgrading IP Cores at the Command Line

Alternatively, you can upgrade IP cores at the command line. To upgrade a single IP core, type the following command:

quartus_sh --ip_upgrade -variation_files <my_ip_path> <project>

To upgrade a list of IP cores, type the following command:

quartus_sh --ip_upgrade -variation_files "<my_ip>.qsys;<my_ip>.<hdl>; <project>"

1 IP cores older than Quartus II software version 12.0 do not support upgrade. Altera

verifies that the current version of the Quartus II software compiles the previous version of each IP core. The MegaCore IP Library Release Notes reports any verification exceptions for MegaCore IP. The Quartus II Software and Device Support Release Notes reports any verification exceptions for other IP cores. Altera does not verify compilation for IP cores older than the previous two releases.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 2: Getting Started 2–5

Specify Parameters

To specify the parameters, follow these steps:

1. In the Quartus II software, create a new Quartus II project with the New Project Wizard.

2. In the IP Catalog (Tools > IP Catalog), locate and double-click the POSPHY4 IP core. The parameter editor appears.

3. Click Step 1: Parameterize.

4. Determine your design’s constraints and performance requirements and then parameterize the POS-PHY Level 4 IP core in the parameter editor.

1 Not all parameters are supported by, or are relevant for, every IP core variation.

5. Click Step 2: Set Up Simulation.

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software.

c You may only use these simulation model output files for simulation purposes and

expressly not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

6. Turn on Generate Simulation Model.

7. Choose the language in the Language list.

8. Some third-party synthesis tools can use a netlist that contains only the structure of the IP core, but not detailed logic, to optimize performance of the design that contains the IP core. If your synthesis tool supports this feature, turn on Generate netlist.

9. Click OK.

10. Click Step 3: Generate in IP Toolbench.

Tab le 2– 1 describes the generated files and other files that may be in your project

directory. The names and types of files specified in the IP Toolbench report vary based on whether you created your design with VHDL or Verilog HDL

1 If you want to change your project from a receiver to a transmitter, delete all

the HDL files before you regenerate the IP core.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

2–6 Chapter 2: Getting Started

Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>.html - IP core generation report

<your_ip>_testbench.v or .vhd - Testbench file

<your_ip>.bsf - Block symbol schematic file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist1

<your_ip>_bb - Verilog HDL black box EDA synthesis file

<your_ip>.vo or .vho - IP functional simulation model

<your_ip>.qip - Quartus II IP integration file

<your_ip>.v or .vhd - Top-level HDL IP variation definition

<your_ip>_block_period_stim.txt - Testbench simulation data

<your_ip>-library - Contains IP subcomponent synthesis libraries

Files Generated for Altera IP Cores (Legacy Parameter Editor)

The Quartus II software version 14.0 and previous parameter editor generates the following output file structure for Altera IP cores:

Figure 2–5. IP Core Generated Files (Legacy Parameter Editor)

Table 2–1. Generated Files (Part 1 of 2)

File Description

<variation name>_atlfifo_concat.v

<variation name>_dpa_concat.v

<variation name>_pl4_rx_core_constraints.tcl

<variation name>_refresh_model.tcl

<variation name>_run_modelsim.tcl

<variation name>_rx_data_proc.ocp An OpenCore Plus file, for time limited or tethered hardware evaluation.

<variation name>_rx_modules.v

<variation name>_rx_data_phy_altlvds.v

<variation name>_rx_core.v

variation name>_syn.v or

variation name>_syn.vhd

<variation name>_tb.v A Verilog HDL testbench for the requested parameterization.

<variation name>.bsf

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

An encrypted HDL file for Quartus II synthesis. This file is automatically added to your Quartus II project. You should not modify this file.

A generated HDL file for Quartus II synthesis. This file is automatically added to your Quartus II project. You should not modify this file.

Constraint settings file for Quartus II synthesis. Use this file to specify constraints required to achieve performance requirements.

A Tcl script that regenerates the IP functional simulation model, in both Verilog HDL (.vo) and VHDL (.vho) formats.

A Tcl script that automates the process of running the testbench with the IP functional simulation model.

An encrypted HDL file for Quartus II synthesis. This file is automatically added to your Quartus II project. You should not modify this file.

A generated HDL file for Quartus II synthesis. This file is automatically added to your Quartus II project. You should not modify this file.

A timing and resource netlist for use in some third-party synthesis tools.

Quartus II symbol file for the IP core variation. You can use this file in the Quartus II block diagram editor.

Chapter 2: Getting Started 2–7

Simulate the Design

Table 2–1. Generated Files (Part 2 of 2)

File Description

<variation name>.html The IP core report file.

XML file that describes the IP core pin attributes to the Quartus II Pin Planner. IP

<variation name>.ppf

<variation name>.sdc

<variation name>.v or .vhd

<variation_name>.vo or .vho Verilog HDL IP functional simulation model.

core pin attributes include pin direction, location, I/O standard assignments, and drive strength.

TimeQuest SDC constraint settings file for timing analysis. Use this file to specify constraints required for TimeQuest analysis.

A IP core variation file, which defines a Verilog HDL top-level description of the custom IP core. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.

1. After you review the generation report, click Exit to close the parameter editor.

The custom IP core variation is integrated into your design. You are now ready to simulate and compile.

Simulate the Design

You can simulate your design using the VHDL and Verilog HDL IP functional simulation models.

f For more information on IP functional simulation models, including NativeLink, refer

to “Simulate the Design” on page 2–7 and the Simulating Altera IP in Third-Party

Simulation Tools chapter in volume 3 of the Quartus II Handbook.

Altera provides models you can use for functional verification of the POS-PHY Level 4 IP core within your design. A Verilog HDL testbench, including scripts to run it, is also provided. This testbench, for use with the ModelSim-Altera simulator or other simulator tools via NativeLink, demonstrates how to instantiate a model in a design.

This section tells you how to use the testbench with the ModelSim simulator or with other simulators via NativeLink.

f For a list of the simulators that you can use with NativeLink, refer to the Simulating

Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.

c The testbench is in Verilog HDL, so you require a license to run mixed language

simulations to run the testbench with the VHDL model. If you edit any of your variation’s clear-text Verilog HDL files, you must update the IP functional simulation model before running the simulator. To update the model, run the quartus_sh -t <variation_name>_refresh_model.tcl script in the Quartus II software.

Use the Testbench with the ModelSim Simulator

To use the testbench with IP functional simulation models in the ModelSim simulator, follow these steps:

1. Start the ModelSim simulator.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

2–8 Chapter 2: Getting Started

Simulate the Design

2. In the simulator, change the working directory to the location of the <variation_name>_run_modelsim.tcl file.

3. To run the script type the following command at the simulator command prompt:

source <variation_name>_run_modelsim.tcl

Use the Testbench with NativeLink

To use the testbench with third-party IP functional simulation models using NativeLink, follow these steps:

1. Create a new custom variation in your Quartus II project. Generate your IP core for this variation using the parameter editor.

2. Check that the absolute path to your third-party simulation tool is set. Set the path by clicking Tools > Options > EDA Tool Options.

3. Click Processing > Start > Start Analysis & Elaboration.

1 If the analysis and elaboration is not successful, fix the error before moving

to the next step.

4. Click Assignments > Settings. The Settings dialog box appears. Expand EDA Tool Settings and select Simulation.

5. In Too l n a m e, select a simulator tool from the list.

6. In EDA Netlist Writer options, select VHDL from the list for Format for output netlist.

7. In NativeLink settings, select the Compile test bench option and then click Te s t Benches. The Test Benches dialog box appears.

8. In the Tes t B e n ch es dialog box, click New. The New Test Bench Settings dialog box appears.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 2: Getting Started 2–9

Compile the Design and Program a Device

9. In the New Test Bench Settings dialog box, enter the information described in

Table 2–2 on page 2–9 (refer also to Figure 2–6 on page 2–9). To enter the files

described in the table, browse to the files in your project.

Table 2–2. NativeLink Test Bench Settings

Parameter Setting and File Name

Test bench name <any name>

Top-level module in test bench tb

Design instance name in test bench <variation name>

Run for 100 ns

Test bench files <variation name>_tb.v

Figure 2–6 on page 2–9 shows an example of the testbench settings whxen the

<variation_name> is example.

Figure 2–6. Example of New Test Bench Settings for NativeLink

10. When you have entered the required information for your new testbench, click OK in the New Test Bench Settings dialog box.

11. Click OK in the Test Benches dialog box and then click OK in the Settings dialog box.

12. Click Tools > EDA Simulation Tool, and then click Run EDA RTL Simulation Tool. The simulation now begins with your chosen simulation tool.

Compile the Design and Program a Device

You can use the Quartus II software to compile your design. Refer to Quartus II Help for instructions on compiling your design.

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2–10 Chapter 2: Getting Started

Compile the Design and Program a Device

After you have compiled your design, program your targeted Altera device and verify your design in hardware.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

3. Parameter Settings

You customize the POS-PHY Level 4 IP core by specifying parameters using the parameter editor

c This chapter describes the parameters and how they affect the behavior of the IP core.

Each section corresponds to a tab when you click Parameterize in the parameter editor.

Basic Parameters

Figure 3–1 shows the basic parameters tab.

Figure 3–1. Basic Parameters

in the Quartus®II software.

Device Family

Select the device family. Table 1–3 on page 1–2 shows the device families that the POS- PHY Level 4 IP core supports.

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3–2 Chapter 3: Parameter Settings

Basic Parameters

Tab le 3– 1 shows the maximum LVDS data rates supported by the POS-PHY Level 4 IP

core for each device family.

Table 3–1. Supported LVDS Data Rates

Device Family LVDS Rate (Mbps)

Arria II GX and Arria II GZ 1,000

Cyclone III 622

Cyclone IV 622

Stratix III 1,250

Stratix IV 1,250

Stratix V 1,250

Stratix GX 1,000

The POS-PHY Level 4 IP core operates either as a receiver where data flows from the SPI-4.2 interface to the Atlantic

™

interface, or as a transmitter where data flows from

the Atlantic interface to the SPI-4.2 interface.

1 The receiver and transmitter variations are separate building blocks in a design, with

no dependency on each other, so you select the parameters independently. For the IP core to act as a full-duplex, bidirectional transceiver, instantiate one for each direction. Typical designs may include one or more receivers and one or more transmitters per FPGA.

1 After you have generated a custom variation, you can re-open the parameter editor

and change the parameters. However, do not change a receiver variation to a transmitter variation, or a transmitter variation to a receiver variation, otherwise the Quartus II software generates errors during compilation.

If your receiver design requires dynamic phase alignment (DPA), turn on Dynamic Phase Alignment.

DPA is recommended for data rates exceeding 622 Mbps, and considered essential for high-quality signaling above 800 Mbps, or across connectors at 700 Mbps.

DPA is only available in Stratix III, Stratix II, and Stratix GX devices.

f For further information about DPA, refer to “DPA Channel Aligner

(rx_data_phy_dpa)” on page 4–2.

LVDS Data Rate

For a transmitter, the LVDS d ata r ate specifies the data rate out of the FPGA, on each LVD S pai r.

IP Toolbench uses this parameter to instantiate and configure the ALTLVDS IP core that includes the fast PLL. For example, to configure a transmitter with a data rate of 700 Mbps on the This rate corresponds to a 350 MHz DDR clock on

For a receiver, the LVDS data rate specifies the data rate into the FPGA, on each LVDS pair, and sets the phase-locked loop (PLL) clock rate.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

tdat

line, enter

700

in the LVDS Data Rate field of IP Toolbench.

tdclk

Chapter 3: Parameter Settings 3–3

Basic Parameters

IP Toolbench uses the LVDS data rate to instantiate and parameterize the ALTLVDS IP core that includes the fast PLL. For example, for a receiver with a data rate of 700 Mbps on each 350 MHz double-data rate (DDR) clock on

rdat

line, enter

700

in LVDS data rate. This value corresponds to a

rdclk

PLL Input Frequency

For a transmitter only, you can enter the PLL input frequency. To enter the PLL frequency, you must click Import PLL Frequency, to open the ALTLVDS wizard and view the available input PLL frequencies.

1 When you change the data path width, the PLL input frequency changes. 1 Do not type the PLL frequency into the box.

Data Path Width

The Data path width affects two important aspects of the IP core: size and performance. The IP core offers the following options:

■ 128 bits running at a frequency of 1/8 the LVDS data rate

■ 64 bits running at 1/4 the LVDS data rate

■ 32 bits (quarter rate) running at 1/2 the LVDS data rate (for non-standard

applications at a maximum of 250 Mbps)

f For approximate resource usage and performance of example POS-PHY Level 4

variations, refer to “Performance and Resource Utilization” on page 1–5.

Buffer Mode

The POS-PHY Level 4 IP core supports the following two buffer modes:

■ Shared buffer with embedded addressing

■ Individual buffers

With Shared buffer with embedded addressing, all ports share a single Atlantic buffer with an 8-bit address field that supports up to 256 ports. The data is read from the Atlantic buffer in the same order as it is received. The shared buffer with embedded addressing mode is smaller than the individual buffers mode, and allows you to develop your own buffering and status generation implementation.

With Individual buffers, the POS-PHY Level 4 IP core provides an Atlantic first-in first-out (FIFO) buffer for each port. Therefore, there are as many Atlantic FIFO buffers of the same depth and width—each with a unique Atlantic interface on the user end—as the number of ports that you select. The individual buffers supports up to 16 ports.

1 Timing and routing difficulties may occur when using 16 ports for 128 bit variations;

thus a maximum of 10 ports is recommended for 128-bit variations.

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3–4 Chapter 3: Parameter Settings

Basic Parameters

For transmitters for individual buffers variations, a credit-based scheduler is provided. This scheduler decodes the incoming status channel and decides from which FIFO buffer (port) to transmit.

The individual buffers for transmitters offer the following advantages:

■ A simple user interface

■ Full scheduler

■ No head-of-line blocking

■ Per-port backpressure

f For further information on individual buffers for transmitters, refer to “Individual

Buffers” on page 5–3.

For receivers, the individual buffers offer the following advantages:

■ A simple user interface

■ No head-of-line blocking

■ The POS-PHY Level 4 IP core handles all of the backpressure automatically

f For further information on individual buffers for receivers, refer to “Individual

Buffers” on page 4–6.

The SPI-4.2 protocol supports from 1 to 256 ports. When you select the number of ports, you determine the mode of operation. Single-PHY operation for one port; or multi-PHY for two to 256 ports. For example, when interfacing to a 10-channel Gbit Ethernet MAC device the number of ports is 10.

When you use the shared buffer with embedded addressing, the Number of ports determines the number of port addresses supported by the POS-PHY Level 4 protocol portion of the IP core, such as the status generator and error checker. Port addresses 0 to 255 can always be sent and received when using Shared buffer with embedded addressing.

For the shared buffer with embedded addressing, the Buffer size defines the size of the shared embedded address buffer. For the individual buffers, the Buffer size defines the size of each buffer. The POS-PHY Level 4 IP core supports the following sizes (per buffer):

■ 512 bytes

■ 1,024 bytes

■ 2,048 bytes

■ 4,096 bytes

■ 8,192 bytes

■ 16,384 bytes

■ 32,768 bytes

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 3: Parameter Settings 3–5

Basic Parameters

Atlantic FIFO Buffer Clock

The Atlantic FIFO buffer clock sets the clock mode for the Atlantic FIFO buffers. Two choices are available: Single or Multiple.

With a single Atlantic FIFO buffer clock, the Atlantic FIFO buffers are instantiated as single clock domain buffers that do not include any clock crossing logic and therefore consume fewer logic resources.

With a multiple Atlantic FIFO buffer clocks, the Atlantic FIFO buffers are instantiated as multiple clock domain buffers. Each buffer has two independently operated clock inputs, thus each Atlantic interface has a separate clock input. Multiple Atlantic FIFO buffer clocks consume more logic resources.

Atlantic Interface Width

The Atlantic interface width includes 32, 64, or 128 bits, and depends on the internal data path width. Tab le 3– 2 shows the Atlantic data widths supported for each internal data path width.

1 For the individual buffers mode, all buffers have the same data path width.

Table 3–2. Atlantic Interface Data Width Limitations

Internal Data Path Width (Bits) Supported Atlantic Data Width (Bits)

128 128

64 64 and 128

32 32 and 64

The Status channel clock edge determines on which clock edge—positive (rising), negative (falling), or programmable—the 2-bit status channel is transmitted (by the receiver IP core) in reference to the

tsclk

(for the transmitter) or

rsclk

(for the receiver) pin. When you turn on Programmable Edge, an input pin, (

ctl_ts_statedge

for the transmitter;

ctl_rs_statedge

for the receiver), controls the

status channel clocking edge statically at reset.

1 To ensure proper sampling of the status information, you should typically set this

parameter to be the opposite of the sampling clock edge on the adjacent device.

For the Status channel I/O standard, either LVTTL or LV DS , select LVD S to implement the optional lower bandwidth LVDS status operation (refer to the OIF- SPI4-02.1 specification).

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3–6 Chapter 3: Parameter Settings

Optional Features

Figure 3–2 on page 3–6 shows the Optional Features tab.

Figure 3–2. Receiver Optional Features

These parameters allow you to enable additional features that the IP core provides. Each parameter may increase or decrease the number of logic resources.

Turn on Atlantic error checking to add a packet filtering module to the write side of every Atlantic FIFO buffer. The packet filtering module ensures that only properly formatted packets are passed through the Atlantic FIFO buffer. When you turn off Atlantic error checking, the packet filtering module is not added.

The packet filtering module corrects start-of-packet (SOP) and end-of-packet (EOP) errors before writing packets into the FIFO buffer. For a missing SOP (where data or an EOP is received for a port without first having received a SOP), an error output is asserted, and data is not written to the buffer until a SOP is received. For a missing EOP (where a SOP is received before the previous packet’s EOP), the current packet is terminated by an EOP, and ERR is asserted. The next packet is stored normally.

For individual buffers variations with a large number of ports, the Atlantic error

checking increases the amount of logic.

Atlantic error checking is often desirable for receivers, but less applicable for

transmitters because the incoming user-Atlantic data may be presumed correct.

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Chapter 3: Parameter Settings 3–7

Optional Features

The missing SOP and missing EOP error indicators are always zero if you turn off Atlantic error checking.

Turn on Parity protected memory to protect all Atlantic FIFO buffers in the IP core by byte-lane parity. The parity is calculated across every byte of data that is written to memory in the buffers, and is checked for correctness when it is read. If a parity error is detected, an error signal is raised. Turn off Parity protected memory, to deactivate the parity protection.

1 In the receive direction, the parity error signal is 2 clock cycles delayed (compared to

Atlantic FIFO read data). In the transmit direction, the parity error signal is 1 or 2 clock cycles delayed (compared to Atlantic FIFO read data) depending on the parameters selected.

Transmitter Options

When you turn on Lite transmitter, the transmitter pads packets with

IDLE

characters to a multiple of 16 bytes for 128-bit variations, or 8 bytes for 64-bit variations. Although using the lite transmitter feature lowers the effective bandwidth rate on the SPI-4.2 data bus, it greatly reduces the logic consumption.

When you turn off Lite transmitter, the transmitter packs the packets more tightly together and pads them with

IDLE

characters to a multiple of 4 bytes. SOP, continuation of packet (COP) and EOP may be combined into a single control word, or may be in adjacent control words. Turning off the lite transmitter feature increases the effective bandwidth rate on the SPI-4.2 data bus, but increases the logic consumption.

1 COP means no SOP. COP can be pure continuation (control word bits [15:12] =

4'b1000

word bits [15:12] =

, so no SOP and no EOP, but payload follows) or EOP + continuation (control

4'b1xx0

, so end current packet, but continue other packets).

For the transmitter IP core you can select Pessimistic or Optimistic for the Status interpretation mode.

In the Pessimistic mode, the latest status information is captured and is stored inside the status processor block until a DIP-2 status is received. If the DIP-2 is valid, the buffered status is passed on to the scheduler or user logic. If the DIP-2 is invalid, the scheduler and user logic do not receive an update, and the next incoming status overwrites the errored buffered status.

In the Optimistic mode, the status information is provided to the user logic and scheduler through a clock-crossing buffer as it arrives on the status channel. DIP-2 errors cause the

err_ts_dip2

flag to be asserted, but do not affect the status reception.

1 The Pessimistic mode causes the latency in receiving a valid status message to be

calendar multiplier × calendar length

tsclk

cycles longer than the optimistic mode. This length is significant for systems with large calendar length or large calendar multiplier values.

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3–8 Chapter 3: Parameter Settings

Optional Features

If you turn on Ignore backpressure (only available when you turn on Shared buffer with embedded addressing), the IP core ignores the backpressure from the receiver

and simply sends data whenever the buffer is not empty. The IP core stops reading from the buffer only when the status framer is out of synchronization, when a training pattern is inserted, or when there is not enough data to complete a burst. The user logic is responsible for using the status outputs from the IP core to schedule data writes into the buffer appropriately.

If you turn off Ignore backpressure, a simple scheduling algorithm is employed. If the status received for any port is satisfied, the transmitter stops reading from the buffer on the next EOP or burst unit size boundary. If all ports are hungry or starving, the transmitter sends the data in the buffer. So a satisfied status received for one port prevents transmission for any port, leading to head-of-line blocking.

If you turn on Switch on end-of-packet, the scheduler stops sending from the current port, and switches ports at the end of burst (that is, when the credits have all been consumed), as well as when an EOP is sent. If you turn off Switch on end-of-packet, the scheduler switches ports at the end of the burst (also includes switching when the buffer is empty).

1 This option applies only to the individual buffers mode, and allows you to

parameterize the port switching capabilities of the transmit scheduler.

f For more information, refer to “Individual Buffers Transmit Scheduler (tx_sched)” on

page 5–3.

Turn on Burst Limit Enable, if you want the transmitter to limit the maximum size of bursts it sends. Set the maximum burst value with the Burst Limit option (on the Protocol Parameters tab). At the end of a burst limit a control word is inserted.

Receiver Options

If you turn off Ignore LVDS DPA locked after training, which is only available for Stratix II devices, a loss of sends framing, and there is data loss and the possibility of MSOP/EOP errors. If you turn on Ignore LVDS DPA locked after training, a loss of trigger stop and framing, and data continues to process normally. You must monitor the DIP4 error signal to assess if the data is correct or not and trigger a retrain or not.

1 For Stratix III and Stratix IV devices, the

the IP core behaves as if you turned on Ignore LVDS DPA locked after training.

If the signal

stat_rd_lvds_lock

assumes that the lock is lost due to external conditions such as jitter. This signal goes low if the capture phase of the hardware DPA block changes by two or more phases. The two phases correspond to a amount that is lower than the accepted threshold for the SPI4.2 Specification. When the signal goes low, the IP core states it is out of synchronization and requests a new training sequence.

dpa_lvds_locked

causes the IP core to stop processing data,

dpa_lvds_locked

signal never goes low, so

goes low during operation (after training), the IP core

does not

In some cases, it is better to ignore this signal and rely on the error checking mechanisms or SPI4.2, by checking the DIP4 calculation. You then have to externally request the retraining and unlock the DPA block.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 3: Parameter Settings 3–9

Optional Features

It is normal during the normal data transfer in SPI-4.2 that

dpa_locked

signal can become de-asserted due to some jitter that is still within 0.44 UI of LVDS data. The DPA has a low pass filter that filters out very high frequency jitter from affecting the lock signal and phase of 8 jump in one direction),

rx_clk

. If the jitter is detected to be 0.25 UI (two phases out of

dpa_locked

is de-asserted and it is still within 0.44 UI.

The DIP-4 error marking determines how the receiver handles DIP-4 errors. The receiver uses the following three modes to mark received DIP-4 errors:

■ None—no error marking is performed.

■ Optimistic mode—the receiver IP core marks the preceding and succeeding burst

as errored. If these bursts are payload (that is, if a DIP-4 occurs followed by

IDLE

s), then only the preceding control word payload is marked as errored. Bursts going into the Atlantic FIFO buffer are marked with the Atlantic error signal. If a burst is not an EOP, it is up to the user logic to detect it.

■ Pessimistic mode—the receiver IP core marks all open packets as errored. Packets

going into the Atlantic FIFO buffer are marked with the Atlantic error signal. This feature increases in resource utilization as the number of ports increases.

End-of-packet-based data available controls the FIFO buffer. Turn on so the

aN_arxdav

signal is asserted (high) when at least one EOP is in the buffer, or the fill level is above FIFO threshold low ( the

aN_arxdav

signal is asserted (high) only if the fill level of the FIFO buffer is above

aN_arxdav

signal on the Atlantic

ctl_ax_ftl

). Turn off so

the FIFO threshold low value.

The Status source option applies only to variations using the shared buffer with embedded addressing mode and provides the following two status channel control options:

■ Buffer Fill Level—the status for each channel is controlled by the single buffer’s

status. Every calendar time slot contains the result of the almost empty (AE) and almost full (AF) comparison to the buffer level.

■ User Controlled—to add extra pins, which allows you to directly control the

transmitted buffer status and allows you to send a status irrespective of the fill level of the internal FIFO buffers, which avoids the situation where the FIFO buffer is not emptied quickly enough, and if you still request data, the FIFO buffer overfills.

Turn on Safe External (User Controlled) Status, to ensure the sent status avoids FIFO buffer overflow (refer to Table 3–3). Turn off Safe External (User Controlled) Status, to ensure the sent status is always the user status (refer to Table 3–3), irrespective of buffer fill level.

1 If you turn off Safe External (User Controlled) Status, you can overflow the internal

FIFO buffer.

Table 3–3. User-Controlled Option (Part 1 of 2)

User Status Value FIFO Buffer Status Value Sent Status Value

Starving Starving Starving

Starving Hungry Hungry

Starving Satisfied Satisfied

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3–10 Chapter 3: Parameter Settings

Optional Features

Table 3–3. User-Controlled Option (Part 2 of 2)

User Status Value FIFO Buffer Status Value Sent Status Value

Hungry Starving or Hungry Hungry

Hungry Satisfied Satisfied

Satisfied Any Satisfied

f For more information, refer to “Status Processor” on page 4–7.

FIFO RAM Blocks

The option to select 2 FIFO RAM blocks depends on the parameters you select on the Basic Parameters tab. These parameters affect the FIFO buffer size and FIFO buffer width, both of which play a role in memory utilization.

When you select 2 FIFO RAM blocks, the timing performance of the IP core may decrease (because the memory 4 FIFO RAM blocks). Altera recommends that you do full compilations for both configurations before deciding which one to choose.

rdata

bus is unregistered, as opposed to registered for

1 Use 2 FIFO RAM block only if it gives an improvement in memory utilization and if

your timing requirements are still met.

Tab le 3– 3 shows the support for the 2 FIFO RAM block. 4 FIFO RAM block supports

all configuration.

Table 3–4. 2 RAM Block Support

Data Flow

Direction

Receiver Any Any Any — Yes

Transmitter

Buffer Mode Data Path Width

Shared Buffer with Embedded Addressing

Individual Buffers

128 128 Any No

Any Any Any Yes

Atlantic Interface

Width

32 — No

64 — Yes

64 Any No

128

Lite Transmitter 2 RAM Block Support

Yes Yes

No No

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 3: Parameter Settings 3–11

Optional Features

Each FIFO RAM block is implemented independently in the available device memory (for example, with M512, M4K, or M9K blocks) and each device memory has a fixed number of available configurations. The FIFO RAM block depth for small buffer configurations (such as 128 × 36 of M4K memory) can be smaller than the minimum configurable depth of the memory element, meaning that the remainder of the memory is wasted. By using 2 FIFO RAM blocks instead of 4 you may get better memory utilization. Figure 3–3 shows the comparison of FIFO RAM blocks.

Figure 3–3. Comparison of FIFO RAM Blocks

4 FIFO RAM Blocks

FIFO Block 0

(size = fifo_size/4)

FIFO Block 1

Write Side

2 FIFO RAM Blocks

(size = fifo_size/4)

FIFO Block 2

(size = fifo_size/4)

FIFO Block 3

(size = fifo_size/4)

Read Side

FIFO Block 0

(size = fifo_size/2)

Write Side

FIFO Block 1

(size = fifo_size/2)

Read Side

Both FIFO buffer width and FIFO buffer size affect memory utilization. The improvement for a two block FIFO buffer configuration versus a four block FIFO buffer configuration ranges from half the memory consumption for small buffers, to the same memory consumption for large buffers.

Tab le 3– 5 gives a comparison of the memory utilization for a Stratix II device with 4

FIFO RAM blocks versus 2 FIFO RAM blocks.

Table 3–5. Memory Utilization Comparison (Note 1)

Buffer

Atlantic Interface Width 32 Atlantic Interface Width 64

Size

(bytes)

2 FIFO RAM Blocks 4 FIFO RAM Blocks 2 FIFO RAM Blocks 4 FIFO RAM Blocks

512 4 M4K 4 M4K + 4 M512 4 M4K + 2 M512 8 M4K + 4 M512

1,024 4 M4K 8 M4K 6 M4K 8 M4K + 4 M512

2,048 6 M4K 8 M4K 6 M4K 12 M4K

4,096 12 M4K 12 M4K 10 M4K 12 M4K

8,192 24 M4K 24 M4K 20 M4K 20 M4K

Note to Tab le 3 –5:

(1) Stratix II device, receive (Rx), shared buffer, data path width 32, parity enabled.

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3–12 Chapter 3: Parameter Settings

Protocol Parameters

Figure 3–4 on page 3–12 shows the Protocol Parameters tab.

Figure 3–4. Receiver Protocol Parameters

Select Real-Time Programmable, so most of the protocol parameters on this tab become input pins to the IP core. These input pins allow each parameter to be connected to a user-implemented register, and controlled at run-time.

Select Fixed Value, to enter values for the protocol parameters on this tab. IP Toolbench then fixes these values in the IP core, making the parameters static and the input pins unavailable.

Calendar Options

Turn on Asymmetric Port Support (only available if you select the Real-time programmable) for the calendar to allow asymmetric weighting of calendar entries to

control the allocation of bandwidth to a given SPI-4.2 port. You must program the calendar for the IP core to produce the status channel (refer to Appendix E,

Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface).

A port with twice the calendar entries of all other ports nominally uses twice as much bandwidth on the SPI-4.2 interface depending on the data characteristics. Ports can be disabled by removing them from the calendar.

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Chapter 3: Parameter Settings 3–13

Protocol Parameters

To be effective, the far-end scheduler must handle received status optimistically. As status is received, credits for each port are topped up to MaxBurst1/MaxBurst2 levels.

Turn on Asymmetric Port Support to instantiate an Avalon

Memory-Mapped (Avalon-MM) interface in the IP core. The Aval on- M M in ter fac e programs the values of calendar length, calendar multiplier, and the port numbers for each of the calendar slots.

If you turn on Asymmetric Port Support, the calendar length is programmed from the Avalon-MM interface (refer to Appendix E).

If you turn on Programmable calendar length, a calendar length input pin is added to the IP core. This pin allows you to vary the calendar length value from one to the number of ports without having to recompile. If the programmable calendar length support parameter is turned off, the calendar length is equal to the number of ports.

The calendar length value cannot be greater than the number of ports (except when you turn on Asymmetrical Port Support).

The Calendar multiplier determines the number of times the calendar sequence is repeated before the DIP-2 parity and framing is inserted. Choose a value from 1 to

256.

If the Asymmetric Port Support is turned on, the calendar multiplier value is programmed via the Avalon-MM interface.

1 The calendar multiplier × calendar length value must be set according to the

instructions in Tab le C–1 o n pag e C– 1 of the “Clock Structure” section, otherwise the status channel does not operate correctly.

The Maximum calendar length (only available when you turn on Asymmetric Port Support) defines the maximum number of calendar entries available in the configurable calendar. Choose a value from 32 to 2,048.

When you turn on Hitless B/W Reprovisioning (only available when you turn on Asymmetric Port Support), the receiver can transmit a calendar-select word in the status frame. Active and inactive calendars are tied to the current calendar-select word in the receiver. When the current calendar-select word changes, the active and inactive calendars are swapped at the appropriate time, in the following order:

■ The

■ At the beginning of the next status frame, the calendar-select word is toggled.

■ The receiver toggles the used calendar multiplier, calendar length, and calendar to

CALSEL_REQ

transmit the next status frame.

■ The transmitter receives the first calendar-select word of the new frame and

detects the toggle.

■ The transmitter toggles the used calendar multiplier, calendar length, and

calendar to interpret the next status frame.

For individual buffers far-end transmitter variations, changing calendars does not cause the credit table to be flushed, thus a port may not immediately be disabled if it still has credits. It is up to the user logic to flush the receiver and transmitter buffers prior to changing the calendar-select word. Otherwise, data may become stranded.

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3–14 Chapter 3: Parameter Settings

Protocol Parameters

Each calendar can have independent values for calendar length and calendar multiplier.

Transmitter Options

The Burst unit size sets the unit size in bytes for burst transfers and controls the smallest burst transmitted. The valid range for this parameter is from 16 to 1,024 bytes, in 16-byte granularity.

1 The burst unit size multiplier does not limit the maximum burst length, and does not

force control word insertion. Instead, use the Burst limit parameter.

When the data path width is equal to 128 bits and the lite transmitter feature is turned off, the unit size is 32 bytes, up to 1,024 bytes in 32-byte granularity.

The MaxBurst1 parameter allows you to select the maximum number of credits— burst unit size to 2,032 bytes—that can be transmitted when the adjacent device’s FIFO buffer is starving.

The MaxBurst2 parameter allows you to select the maximum number of credits— burst unit size to 2,032 bytes—that can be transmitted when the adjacent device’s FIFO buffer is hungry.

The MaxBurst1 and MaxBurst2 parameters do not limit the maximum burst length, and do not force control word insertion.

The MaxBurst1 and MaxBurst2 parameters are used by the transmit scheduler, thus they apply only to the individual buffers mode.

1 MaxBurst2 must be less than or equal to MaxBurst1; MaxBurst1 and MaxBurst2 must

be greater than or equal to burst unit size.

f Refer to Figure 3–5 on page 3–16 for the relation of AE and AF.

You c an en ter t he Burst limit only when you turn on Burst Limit Enable. The Burst limit sets the maximum burst size, in bytes, to be sent by the transmitter, and

guarantees that the transmitter does not send bursts longer than the burst limit (a control word is inserted at the end of the burst limit). Burst limit values are restricted to multiples of burst unit size. Depending on other transmitter parameters, the values may be limited to a minimum value. IP Toolbench only allows valid burst limit values.

The Maximum training sequence interval (MaxT) allows you to select the interval at which the training sequence occurs—16 to 65,535 bytes. The training sequence is scheduled to be inserted after the MaxT counter expires, but is not actually inserted until the burst that is sent is complete. Therefore, the time between training pattern insertions is no less than the value of the MaxT parameter, and no more than the value of the MaxT parameter plus the burst unit size.

If MaxT = 0, periodic training patterns are disabled. If the transmitter status framer is out of synchronization, the transmitter sends continuous training patterns regardless of the MaxT (

tdclk

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

parameter. Training patterns always begin on the rising edge of the clock

Chapter 3: Parameter Settings 3–15

Protocol Parameters

For the Training pattern repetition value, the training sequence includes one word, plus

ALPHA(

a) × 20 training words.

ALPHA

is a user-selectable option (0 to 255).

IDLE

Zero (0) is equal to 256 training pattern repetitions.

The training sequence includes one words are separated into ten consecutive followed by ten consecutive

tdat

IDLE

control word, plus a × 20 words. The twenty

words of

tdat

words of

16’hF000

16’h0FFF

with

tctl

with

1’b0

tctl

1’b1

For the Status sync good and Status sync bad threshold values, two 4-bit inputs,

good_level (ctl_ts_sync_good_theshold)

(

ctl_ts_sync_bad_theshold

The

stat_ts_sync

signal is asserted high when a

), are associated with the

status frames are received without frame or DIP-2 errors. The deasserted when a

bad_level

number of DIP-2 errors or frame errors have been

and

bad_level

stat_ts_sync

good_level

signal.

number of consecutive

stat_ts_sync

signal is

received since the last error-free frame.

The FIFO buffer threshold high (FTH) for transmitter variations controls when the

aN_atxdav aN_atxdav

signal is asserted and deasserted for the write side of the FIFO buffer. The

signal indicates when there is room available to write new data into the FIFO buffer, and is asserted whenever the remaining space in the buffer is greater than the FTH value.

This threshold is defined in terms of bytes, with a valid range from N to buffer size bytes, in N-byte increments, where:

■ N = 4 or 8 bytes for 32-bit data path variations

■ N = 8 or 16 bytes for 64-bit data path variations

■ N = 16 or 32 bytes for 128-bit data path variations

The N-byte values depend on the Atlantic interface width and on the Lite transmitter setting. Ta bl e 3 –6 shows the N-byte values, based on the transmitter's settings.

Table 3–6. N-Byte Values

Datapath Width

128 128

Atlantic Interface

Width

32 — 4

64 — 8

128 On or off 16

Lite Transmitter

On 8

Off 16

On 16

Off 32

N Bytes (FTH

Increment)

1 Although the parameter editor allows you to set FTH values as low as one FIFO

buffer element (translated to bytes), a minimum FTH value is used internally. And, depending on the core's configuration, up to four FIFO buffer locations are unusable. For the exact minimum FTH value and number of unusable locations, refer to the parameter editor message that appears while configuring the core.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

3–16 Chapter 3: Parameter Settings

AE AF

Starving Hungry Satisfied

Lmax + ε

Lmax + MaxBurst1+ ε

Lmax + MaxBurst2+ ε

(Empty) (Full)

Protocol Parameters

Receiver Options

The Almost empty (AE) and Almost full (AF) thresholds segregate the receiver FIFO buffer into three states, depending on the fill levels: starving, hungry, and satisfied. The SPI-4 Phase 2 specification defines two-bit status values for starving, hungry, and satisfied. These two-bit values are based on the available space in the FIFO buffer and on the AE and AF parameter settings:

■ Starving—when the number of elements in the FIFO buffer is less than, or equal to,

the AE threshold

■ Hungry—when the number of elements in the FIFO buffer is between the AE

threshold and the AF threshold

■ Satisfied—when the number of elements in the FIFO buffer is greater than the AF

threshold

The starving, hungry, and satisfied conditions are reported to the adjacent transmitter on the

rstat

bus, which operates at up to ¼ of the

rdclk

frequency.

These thresholds are defined in terms of bytes, with a valid range from zero to

size

1 AE must be lower than or equal to AF.

Figure 3–5 illustrates the relationship between the AE and AF thresholds and the

MaxBurst1 and MaxBurst2 values.

Figure 3–5. FIFO Buffer Thresholds

Notes to Figure 3–5:

(1) L

corresponds to the worst-case response time from sending a status update over the FIFO status channel until

MAX

observing the reaction to that update on the corresponding data path.

 corresponds to the difference between the granted credit and the actual data transfer length. This difference arises

(2)

from various protocol overheads.

(3) The MaxBurst1 and MaxBurst2 values are defined by the adjacent device’s transmitter. Determining the optimal

MaxBurst1 and MaxBurst2 values is application-specific, and requires an analysis of the data flows, beyond the scope of this user guide.

buffer

The FIFO buffer threshold low (FTL) value for receiver variations controls when the

aN_arxdav

signal is asserted for the read side of the FIFO buffer. If the fill level of the buffer is higher than the FTL value, the there is a burst of data available.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

1 There is no requirement to wait for the

from the buffer at any time.

aN_arxdav

signal is asserted indicating that

signal to be asserted, you can read

Chapter 3: Parameter Settings 3–17

Protocol Parameters

1 FTL must be greater than zero.

This threshold is defined in terms of bytes, with a valid range from: N to

buffer size

in increments of N bytes, where:

■ N = 4 or 8 bytes for 32-bit data path variations

■ N = 8 or 16 bytes for 64-bit data path variations

■ N = 16 bytes for 128-bit data path variations

The N-byte values for the 32-bit and 64-bit variations depend on the Atlantic interface width. If the Atlantic interface width is greater than the data path width, the larger value for N is used.

For the DIP-4 good and DIP-4 bad threshold values, two 4-bit inputs are associated with the DIP-4 OOS state machine:

bad_level (ctl_rd_dip4_bad_threshold

If the

stat_rd_dip4_oos

signal is high, and all of the DIP-4s in the control words

good_level (ctl_rd_dip4_good_threshold

) and

received in the current clock cycle (up to 8 in 128-bit mode) are good, the good counter is incremented by 1; otherwise it is reset to 0. If the good counter reaches the

good_level

threshold, the

stat_rd_dip4_oos

flag is cleared. A

good_level

of 0 is

invalid.

If the

stat_rd_dip4_oos

signal is low, and all of the DIP-4s in the control words received in the current clock cycle (up to 8 in 128-bit mode) are errored, the bad counter is incremented by 1; otherwise it is reset to 0. If the bad counter reaches the

bad_level

threshold, the

stat_rd_dip4_oos

flag is asserted. A

bad_level

of 0 is

invalid.

1 The receiver may need to receive more control word DIP-4 errors than the DIP-4 bad

threshold parameter set in the wizard, for

stat_rd_dip4_oos

to go high.

f For more information, refer to “DIP-4 Marking” on page 4–16 and “DIP-4 Out of

Service Indication” on page 4–17.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

3–18 Chapter 3: Parameter Settings

Protocol Parameters

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

4. Functional Description—Receiver

Data Receiver

And

Serial-to-Parallel

Converter

DPA Channel

Aligner

Status PHY Status FSM

Status

Status Hold

Status

Calculator

Data

Processor

Atlantic Buffer 0

Atlantic Interface 0

SPI4.2

Interface

rdclk

rxsys_clk

rdint_clk

rav_clk

rsclk

Atlantic Buffer N

Atlantic Interface N

The POS-PHY Level 4 IP core consists of the main SPI-4.2 processing logic, and configurable Atlantic core is configured as a receiver, data flows from the SPI-4 interface to the Atlantic interface.

Features

■ Accepts packets from a SPI-4.2 transmitter

■ Processes control words

■ Detects diagonal interleaved parity (DIP-4) errors

■ Detects SPI-4.2 protocol errors

■ Performs start-of-packet (SOP) alignment and Atlantic conversion

■ Buffers packets on a per-port or per-interface basis

■ Detects buffer fill levels and generates the status channel

Block Description

Figure 4–1 on page 4–1 shows the blocks and clocks that comprise the receiver IP core.

Figure 4–1. Block Diagram—Receiver (Note 1)

™

first-in first-out (FIFO) buffers. When the POS-PHY Level 4 IP

Note to Figure 4–1:

(1) The dotted lines illustrate the clock domain separations.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–2 Chapter 4: Functional Description—Receiver

Block Description

This section describes the top-level blocks of the POS-PHY Level 4 receiver IP core.

Data Receiver and Serial-to-Parallel Converter (rx_data_phy_altlvds)

Data and control words arrive on the

rdclk

. Payload and control words contain two bytes, where bit 15 is the most

rdat

bus, and are sampled on both edges of

significant bit (MSB) and bit 8 is the least significant bit (LSB) of the first byte, and bit 7 is the MSB and bit 0 is the LSB of the second byte.

For 128- and 64-bit variations, an ALTLVDS_RX IP core deserializes the SPI-4.2

rdat/rctl

is derived from the

lines into words at or the

rdclk

input pin, and is the clock that drives the internal logic

rdat

data rate, respectively. The

elements for the receiver.

For 32-bit (quarter-rate) variations, an ALTDDIO_IN IP core deserializes the SPI-4.2

rdat/rctl

For rates above 311 Mbps, the Stratix

lines into words at  the

rdat

data rate.

III, Stratix II, Stratix GX, and Stratix devices include a dedicated SERDES (ALTLVDS IP core) implemented in LVDS I/Os. For rates below 250 Mbps, LVDS I/O pins are used.

1 A fast phase-locked loop (PLL) is required for the ALTLVDS SERDES.

f For more information on the ALTLVDS_RX and ALTDDIO_IN IP cores, refer to

Quartus

II Help, to the SERDES Transmitter/Receiver ALTLVDS IP Core User Guide, or

to the ALTDDIO IP Core User Guide.

DPA Channel Aligner (rx_data_phy_dpa)

rdint_clk

In the Stratix III, Stratix II, and Stratix GX device families, the ALTLVDS_RX IP cores support an optional DPA feature that can compensate for trace length mismatches and variations due to process, voltage, and temperature (PVT).

The DPA feature includes the following functions:

■ Supports data rates from 415 Mbps to 1 Gbps in Stratix GX devices

■ Supports data rates from 415 Mbps to 1,250 Gbps in Stratix III devices and to 1,050

Gbps in Stratix II devices

■ At reset, it performs channel alignment using SPI-4.2 training patterns

compensating for static clock-channel and channel-to-channel skew

■ After reset, it dynamically follows changing clock-channel and channel-to-channel

skew without using SPI-4.2 training patterns

■ Supports a total skew of 4.5 bits, with 0.5 bits of the total allowed after reset in

Stratix GX devices

■ Supports a total skew of 4.4 bits, with 0.4 bits of the total allowed after reset in

Stratix III and Stratix II devices

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–3

ALTLVDS_RX Megafunction

(with DPA)

rx_data_phy_dpa

rdclk

rdat/rctl

Serial

Data

lvds_reset

16+1

align

16+1

data_out

128+/64+

data_out_algn

128+/64+

PLL

clk x 2

data : 2

8:4

Serializer

(2)

128+/64+

Parallel

Data

stat_rd_dpa_locked

ctl_rd_dpa_force_unlock

stat_rd_dpa_lvds_locked (3)

16+1

Status/ Control Signals

err_rd_dpa

Channel

Aligner

16+1

rdint_clk

rxreset_n

Block Description

If the DPA parameter is turned on, the DPA feature consists of an ALTLVDS_RX IP core with DPA enabled, and a channel aligner. For 64-bit data path width variations in Stratix GX devices, this feature also consists of an 8:4 serializer (needed to achieve an overall deserialization factor of 4). Three status signals:

err_rd_dpa ctl_rd_dpa_force_unlock

and

stat_rd_dpa_lvds_locked

are also part of this feature. Figure 4–2 shows the DPA

, and one control signal:

stat_rd_dpa_locked

block diagram.

Figure 4–2. DPA and Channel Aligner Block Diagram

Notes to Figure 4–2:

(1) The width of the data path for the (2) Exists only for Stratix GX devices, if the internal data path width is 64 bits.

stat_rd_dpa_lvds_locked

(3) The

data_out, data_out_algn

signal does not exist in the

altlvds

, and

data:2

signals depends on the deserialization factor.

block for Stratix GX devices. It is tied to a logic 1 inside the receiver IP core.

ALTLVDS_RX IP Core

The ALTLVDS_RX IP core always performs deserialization on the input rdat and rctl high-speed LVDS signals, and divides the DDR rdclk to produce a slower rdint_clk.

When DPA is enabled in the POS-PHY Level 4 IP core, the ALTLVDS_RX IP core has two other features enabled: DPA and bit slip. DPA with respect to ALTLVDS has a different meaning than DPA with respect to the POS-PHY Level 4 IP core. After DPA resets, the ALTLVDS DPA feature tolerates only a small amount of change to the channel-to-channel skew, which compensates for the very small amounts of change in channel-to-channel skew that may occur due to voltage and temperature shifts during system operation. A change in channel-channel skew that is greater than the bit-time tolerance causes one or more of the internal deskew FIFO buffers to underflow or overflow, which the POS-PHY Level 4 IP core detects only as DIP-4 errors. You must use the DIP-4 thresholds and stat_rd_dip4_oos to trigger the DPA reset by

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

asserting ctl_rd_dpa_force_unlock. The stat_rd_dpa_lvds_locked signal indicates when the DPA cannot stay locked

either because of a lack of transitions on the channel, or because of rapid changes in skew. The DPA run length is 6,400 UI for Stratix III, Stratix II, and Stratix GX devices. If the traffic on the SPI-4.2 interface is very sparse, periodic training patterns may be required.

4–4 Chapter 4: Functional Description—Receiver

Block Description

To compensate for large amounts of static channel-to-channel skew, the POS-PHY Level 4 IP core channel aligner state machine uses the bit slip feature (the channel align or data realignment) of the ALTLVDS_RX IP core.

The POS-PHY Level 4 IP core automatically configures and includes the ALTLVDS_RX IP core.

Channel Aligner

The DPA feature of the ALTLVDS_RX IP core provides parallel data sampled correctly and aligned to a single clock. As it does not use a data pattern, it cannot compensate for more than one bit time of channel-to-channel skew which may exist due to trace length mismatches.

The channel aligner sub-block uses the SPI-4.2 training pattern to align the parallel data. Alignment is done once at start-up, and then only when requested by asserting the

ctl_rd_dpa_force_unlock

alignment process once the altlvds_rx IP core asserts the the bits of the which can be detected by looking for the repeating training pattern. For every align pulse, the ALTLVDS_RX IP core sub-block shifts the data on the corresponding channel by one bit, effectively in the serial domain. The actual shift occurs in the serial domain for Stratix III and Stratix II devices, and in the parallel domain for Stratix GX devices.

align[16:0]

signal. The channel aligner state machine begins the

ctl_rd_dpa_force_unlock

stat_rd_dpa_lvds_locked

signal channel by channel until all channels are aligned,

signal is deasserted and the

signal (high). It then pulses

In Stratix III and Stratix II devices, the IP core requires less than 220 training patterns (lock time) before it asserts the signal is tied low.

In Stratix GX devices, the IP core requires less than 700 training patterns (lock time) before it asserts the because of a large skew between data channels, or because the

stat_rd_dpa_lvds_locked

aligner asserts the

stat_rd_dpa_locked

err_rd_dpa

stat_rd_dpa_lvds_locked

signal. If alignment cannot be achieved

signal becomes deasserted during training, the channel

signal.

signal. The

err_rd_dpa

8:4 Serializer

The 8:4 serializer block supports an overall deserialization factor of 4 for 64-bit Stratix GX variations only. It consists of a PLL and a 2:1 multiplexer for each channel.

f For more information on using dynamic phase alignment, refer to Appendix F, Static

and Dynamic Phase Alignment.

Data Processor (rx_data_proc)

The data processor consists of three sub-blocks.

Control Word Processing & DIP-4

The control word processing and DIP-4 block analyses the control words from the data stream, and calculates the running DIP-4 value. It detects the following errors:

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–5

Block Description

■ SOP8 violations. If SOPs occur less than 8 cycles apart, the

err_rd_sop8

signal is asserted but there is no impact on the received data. In 128- and 64-bit variations, the clock-domain crossing buffer may fill faster when SOP8 violations occur.

■ Odd size packet violations. If an odd size packet does not end with the LSB cleared

to zero, the

aN_arxerr

signal is asserted on EOP. The

err_rd_pad_byte_non_zero

signal is also asserted.

■ EOP aborts. If an EOP abort is received, the

The

err_rd_eop_abort

■ DIP-4 errors (refer to “DIP-4 Marking” on page 4–16 and “DIP-4 Out of Service

signal is also asserted.

aN_arxerr

signal is asserted on EOP.

Indication” on page 4–17).

■ Reserved control words—data is dropped.

■ Proper training patterns. The channel aligner block requires proper training

patterns to lock, so if the transmitting device is sending bad training patterns, the

err_rd_tp

1 Whenever the IP core aborts a packet by asserting the

signal is asserted and the IP core does not lock.

aN_arxerr

signal (as in the odd size packet with LSB not cleared), the resulting packet is even sized, except in the DIP-4 optimistic mode.

f For a more complete list of errors detected by the IP core, refer to “Error Flagging and

Handling” on page 4–12.

Clock-Domain Crossing Buffer

This block instantiates a clock-domain crossing buffer called alignment buffer (ABUF) to transfer data from the

rdint_clk

clock domain to the depth of the alignment buffer is fixed at 128; the width is equal to the IP core data path width.

f For a description of the relationship between

“Clock Structure” on page 4–9.

SOP Alignment & Atlantic Conversion

This block moves the SOP for each packet to the first-byte position on the Atlantic interface, and aligns the data to ensure that valid data is contiguous (no IDLEs) before sending it to the Atlantic buffer.

Atlantic Buffers

The Atlantic FIFO buffers provide the following features:

■ Single receive slave-source Atlantic interface on the user end

■ Configurable buffer size

■ Support for crossing clock domains

rdint_clk

rxsys_clk

and

rxsys_clk

clock domain. The

, refer to

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–6 Chapter 4: Functional Description—Receiver

Block Description

■ Buffer status interface

■ Overflow error indication

■ Underflow warning indication

■ Configurable FIFO buffer threshold low (FTL)

■ Optional end-of-packet-based data available (

■ Atlantic interface error checking

■ Missing or spurious SOP/EOP detection and correction

■ Optional overflow handling

aN_arxdav

) signal assertion

Shared Buffer with Embedded Addressing

When the shared buffer with embedded addressing mode is selected, the POS-PHY Level 4 IP core consists of the receiver processor logic and a shared FIFO buffer with embedded addressing.

The shared buffer is a single Atlantic FIFO buffer, where for each data word a tag is carried containing the port number. This means that the Atlantic-side logic cannot selectively pick a port to access. Instead, data bursts from all ports are stored collectively into this one shared physical buffer, and the ordering of the data bursts is maintained in the order in which they were received on the SPI-4.2 bus.

The shared buffer and the logic support up to 256 ports. If Atlantic error checking is enabled, 256 ports are still supported by the IP core, but the logic for error checking uses only the minimum amount of logic required to support the number of ports chosen as a parameter. The port width field remains fixed for 256 ports and unused address bits are passed through unaffected. For example, if a variation has 4 ports, only the lower 2 address bits are used for error checking—data received for port 6 is checked as though it is for port 2. This allows unused upper address bits to be used for packet classification.

The single FIFO buffer with embedded addressing supports interleaved packets. An interleaved packet occurs when, for example, a packet from port 2 is sent, and then a packet from port 3 is sent before port 2 has received the EOP indication. This interleaving is achieved by changing the

aN_arxadr

in the middle of the packet.

The shared buffer with embedded addressing mode is useful if you intend to handle buffering outside of the IP core. To support user-defined external buffering, a fully exposed status interface is provided, but requires that the status channel override (status source parameter) be enabled. Normally, the shared buffer with embedded addressing fill level is compared against the global almost empty (AE) and almost full (AF) values to produce the status information for all ports on the status channel. With the override feature, you can set the FIFO buffer status information values on a perport basis.

Individual Buffers

When the individual buffers mode is selected, the POS-PHY Level 4 IP core consists of the receiver processor logic, and a separate Atlantic FIFO buffer for each port.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–7

Block Description

The advantage of the individual buffers mode is that each Atlantic interface can be accessed in parallel and independently, and the IP core handles the status generation automatically. The disadvantage is that because the number of ports directly increases the logic utilization, the individual buffers mode is not well suited for applications with a large number of ports.

Status Processor

A major component of a SPI-4.2 system is flow control. Flow control is achieved by periodically sending near-end FIFO buffer status to the far-end device’s scheduler over the status channel.

Collectively, the status processor blocks calculate, format, and transmit the status channel.

Starting at the physical interface and working back to the FIFO buffers, the flow control has the following operation.

The status PHY block (

■ In 128-bit variations, the

■ In 64-bit variations, the

■ In 32-bit variations, the

The status PHY block aligns depending on the input value of the implements a clock-crossing FIFO buffer between the

The status FSM block (

rx_stat_phy

rsclk

rstat

) generates

runs at the

runs at 1/2 the

runs at 1/4 of the

to either the positive or negative edge of

ctl_rs_statedge

rx_stat_proc_fsm)

rsclk

given some reference clock:

rdint_clk

rate.

rdint_clk

rate.

rsclk

signal. This block also

rsclk

and

rxsys_clk

domains.

is enabled when the clock-crossing FIFO buffer of the status PHY block has available space. When enabled, this block generates the next words in the status frame.

If the clock-crossing FIFO buffer underflows or overflows because of an incorrect configuration, if the Memory-Mapped (Avalon-MM) interface is set, the finite state machine outputs ‘ continuously and the

ctl_ry_rsfrm

signal is set, or if the

stat_ry_disabled

rsfrm

signal is asserted.

bit in the Avalon®

’

Framing, calendar select word, and DIP are generated locally, but the actual status for each calendar slot is provided on request by the status register ( block, and either the status calculator (

rx_stat_calc

) or status hold (

rx_stat_proc_reg

rx_stat_hold

)

blocks.

Given a calendar slot number, the status register block determines which port's status belongs in the slot according to the calendar that it stores. When the asymmetric port support parameter is turned off, the port number corresponds with the slot number, (that is, slot one is port one, and so on). When the asymmetric port support parameter is turned on, a programmable calendar is stored in memory, and the port corresponding to the slot is looked up.

1 If the asymmetric port support parameter is turned on, the Avalon-MM registers must

be programmed prior to releasing the

rsfrm

bit (refer to Appendix E and the “Avalon-

MM Interface Register Map” on page 4–28).

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4–8 Chapter 4: Functional Description—Receiver

rxsys_clk

ctl_ry_extstat

ctl_ry_extstat_val

ctl_ry_extstat_adr

2'b00 2'b00 2'b00 2'b00 2'b01 2'bxx 2'bxx 2'bxx 2'b01 2'b00 2'b10

8'd0 8'd0 8'd0 8'd1 8'd1 8'd0 8'd0 8'd0 8'd2 8'd3 8'd1

Block Description

The port number is provided with a request signal to both the status calculator and status hold blocks, but only the output of one block, according to the value of the

ctl_ry_fifostatoverride

outgoing status frame. In the individual buffers mode, the

input, is sent to the status FSM block to be inserted into the

ctl_ry_fifostatoverride

input is forced low to always select the calculated value. In the shared buffer with embedded addressing mode, the

ctl_ry_fifostatoverride

input is set according to the option selected in IP Toolbench for the status source parameter. If the usercontrolled option is selected, you must write buffer status per-port into the status hold block via the external status interface. Otherwise, the interface is ignored and the calculated value is used. This external control interface features an 8-bit address bus, a 2-bit status port value, and a valid signal (refer to Figure 4–3).

1 Due to the round trip latency of the status channel, especially at high calendar

lengths, the hysteresis between the AE and AF values (in addition to the possibility of the override capabilities listed above) may be such that a transition from starving to satisfied (and vice versa) can occur. In the event that a transmitting device does not allow these types of transitions (require hungry state to be observed between starving and satisfied), you should ensure that the difference between AE and AF values is greater than the hysteresis between the thresholds.

Figure 4–3. Receiver External Status Timing Diagram

Notes to Figure 4–3:

(1) The external status address does not have to be incrementing. Any value within calendar length can be provided at any time.

2’b00

(2) The calendar status after the last clock cycle shown has: port 0 =

, port 1 =

2’b10

, port 2 =

2’b01

, and port 3 =

2’b00

The external status address you provide does not have to be incrementing or have any set sequence. You can provide any address value, at any time. If the external address provided is for an unprovisioned port, the value is written into the internal RAM at that address, but the internal status block never reads from that location.

The status hold block reads the contents of the memory where you have stored the status of the external FIFO buffer(s).

The status calculator block compares the Atlantic FIFO buffer fill levels to the AE and AF values for the requested port. In the shared buffer with embedded addressing mode, because there is a single Atlantic FIFO buffer, the status for any port is calculated according to the single level as opposed to a per-port basis.

The outgoing status of all ports is forced to satisfied ,if the datapath clock-crossing buffer or Atlantic buffer overflows.

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Chapter 4: Functional Description—Receiver 4–9

Clock Structure

The FIFO buffer status of each port is encoded in 2 bits (refer to Tab le 4 –1 ) and is transmitted synchronous to the

Table 4–1. Status Channel Field Descriptions

MSB LSB Description

1 1 Reserved for framing

Note to Tab le 4 –1:

(1) Worst case, up to MaxBurst1 16-byte units—plus the amount of data in transit due to data and status latency—

may still be received, regardless of the current status transmitted.

SATISFIED—FIFO buffer is almost full. No new credits should be granted in the far end scheduler.

HUNGRY—FIFO buffer is at a midpoint. MaxBurst2 credits should be granted in the far end scheduler.

STARVING—FIFO buffer is almost empty. MaxBurst1 credits should be granted in the far end scheduler. (1)

rsclk

Clock Structure

With the Atlantic FIFO buffer clock mode parameter in IP Toolbench, you can parameterize the receiver in one of the following two clocking structures:

■ Single clock mode

■ Multiple clock mode

The IP core uses a common clocking structure for all data path width variations.

1 All clocks are asynchronous and paths between the domains can be cut.

The receiver has two primary clock domains. The first clock domain is associated with the SERDES and logic directly connected to the SPI-4.2 interface; the second clock domain is associated with the Atlantic interface and the bulk of the receiver logic. The clock for the first domain is derived from the

rdint_clk

, is available as an output from the IP core, and is the output of the PLL for

rdclk

of the SPI-4.2 interface. This clock,

the ALTLVDS block. For Stratix GX devices, an extra PLL generates the clock.

f For advanced information on the requirements of

rxsys_clk

, refer to Appendix C,

Optimum Frequency for rxsys_clk.

Single Clock Mode

In the single clock mode, the Atlantic FIFO buffers are instantiated as single clock domain buffers, thereby consuming fewer logic resources.

rdint_clk

Multiple Clock Mode

If you select the multiple clock domain mode, the logic of the IP core, and the write side of the Atlantic FIFO buffers.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

rxsys_clk

clock clocks the protocol

4–10 Chapter 4: Functional Description—Receiver

Channel

Aligner

DPA/

SERDES

LVDS

PLL

LVTTL

EPLL

(Note 1)

Status

Processor

Data

Processor

Atlantic

Buffer 0

Atlantic Interface 0

a0_arxclk

aN_arxclk (Note 2, 3)

rdclk

rdat[15:0]

rctl

rxsys_clk

rdint_clk

altlvds Megafunction

rsclk (Note 4)

rstat[1:0]

Atlantic Buffer N

Atlantic Interface N

Clock Structure

In multiple clock domain mode, an input clock is instantiated for each Atlantic FIFO buffer in the IP core, which is used for the read side of the buffers. The naming convention for these input clocks is

aN_arxclk

. These clocks are inputs to the IP core and can either be tied together or controlled individually. No specific frequency requirement is specified for the

aN_arxclk

clocks, but they should be fast enough to

ensure that the FIFO buffers do not fill, otherwise backpressure is asserted via the SPI-

4.2 status channel.

Figure 4–4 on page 4–10 shows the multiple clock domain clocking structure for the

receiver IP core, for 128- and 64-bit individual buffers variations. For shared buffer with embedded addressing variations, only Atlantic buffer port 0 is instantiated.

Figure 4–4. Clock Layout Diagram (Full Rate)

Notes to Figure 4–4:

(1) Stratix GX 64-bit DPA only. (2) The single clock mode removes the separate Atlantic clocks. (3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.

rsclk

(4) The

in 128-bit data path source is

rdint_clk

. 64-bit is internally generated (status processor).

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–11

ALTDDIO_IN

ALTDDIO_OUT

EPLL

(Note 4)

Status

Processor

Data

Processor

Atlantic Buffer 0

Atlantic Interface 0

a0_arxclk

aN_arxclk (Note 2, 3)

rdclk

ctl_rx_pll_areset

stat_rx_pll_locked

rdat[15:0]

rctl

rxsys_clk (Note 1)

rdint_clk

rsclk

rstat[1:0]

Atlantic Buffer N

Atlantic Interface N

Clock Structure

In 32-bit (quarter-rate) SPI-4.2 mode, all the above clocks exist. The maximum frequency of the clocks depends on ALTDDIO_IN limitations. To min i miz e clo ck skews, the

rdclk

goes into a PLL where it generates

rdint_clk

(×1). The PLL is required to provide 90 phase shift, so the ALTDDIO_IN IP core samples in the centre of the data eye. A typical system may have a

4.2 data rate is 200 Mbps. Most of the quarter-rate receiver IP core runs off

rdint_clk

of 100 MHz, of which the SPI-

rdint_clk

including all data path processors and the write side of the FIFO buffer. Figure 4–5 shows the clocking structure used by the receiver IP core, for 32-bit (quarter-rate mode) variations that use the ALTDDIO_IN IP core.

Figure 4–5. Clock Layout Diagram (Quarter Rate)

Notes to Figure 4–5:

(1)

rxsys_clk

(2) The single clock mode removes the separate Atlantic clocks. (3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer. (4) In 32-bit (quarter-rate) SPI-4.2 mode, this PLL only provides a phase shift for the incoming

is internally connected to

rdint_clk

in 32-bit shared buffer with embedded addressing mode variations.

Requirements for rxsys_clk

The IP core’s protocol logic and all Atlantic FIFO buffers share a common clock called

rxsys_clk

buffers.

Tab le 4– 2 shows guidelines for the frequency of

Table 4–2. Frequency Guidelines—rxsys_clk

Data Path Width

f For detail on the optimum setting of

Frequency for rxsys_clk.

that clocks both the write and optionally the read side of the Atlantic FIFO

rxsys_clk

(Bits)

Worst Case Frequency Requirement

32 1.0 ×

64 1.25 ×

128 1.6 ×

rxsys_clk

, refer to Chapter C, Optimum

rdclk

rdint_clk

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–12 Chapter 4: Functional Description—Receiver

LVDS Locked

ctl_ry_rsfrm

ctl_rd_dpa_ force_ unlock

aN_arxreset_n

err_rd_abuf_oflw

ctl_rd_abuf_flush

stat_rd_dpa_lvds_locked stat_rd_dpa_locked

stat_rd_rdat_sync

stat_rd_rx_dip4_oos

User Force Frame

err_ry_fifo_oflwN

User Atlantic Reset

err_rd_abuf_oflw

User Buffer Flush

DPA Locked

Receiver Trained

DIP-4 OOS

Atlantic Buffer Ready

Send Framing

RSFRM Control Bit from

Avalon Control Register

DPA Force Unlock

Atlantic Buffer Overview

Atlantic Buffer Reset

Alignment

Buffer Overflow

Alignment Buffer Flush

Counter

Internal SPI-4.2 Receiver Core Example User Side Connections

Delay

Reset Structure

By default, the

rxreset_n

internally metastable hardened and passed to each of the individual clock domains.

Asserting reset deletes all data in the buffers, and resets all state bits.

In addition to the reset, asynchronous reset and locked signals are provided for the internal PLL, if present. The PLL should be reset and stable along with all other clocks before the reset is released.

Error Flagging and Handling

This section describes how the POS-PHY Level 4 receiver IP core responds to various errors.

Figure 4–6 shows an example user configuration for the POS-PHY Level 4 receiver IP

core.

Figure 4–6. Example User Receiver Configuration

signal is the asynchronous global reset for the IP core. It is

Note to Figure 4–6:

(1) The (2) The delay is to ensure the (3) The counter is intended to pulse the

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

ctl_rd_dpa_force_unlock

signal is not asserted until after start up.

signal is asserted for at least one clock cycle.

ctl_rd_dpa_force_unlock

signal after the frame has been out of synchronization for some time.

Chapter 4: Functional Description—Receiver 4–13

Error Flagging and Handling

SPI-4.2 Protocol Errors

The receiver IP core decodes the control words from the incoming SPI-4.2 interface and ensures that they follow the state machine shown in Fig. 6.2. Data Path State Diagram of the SPI-4.2 Specification, and ensures that there are no other errors. Table 4–3 summarizes the SPI-4.2 protocol errors.

Table 4–3. SPI-4.2 Protocol Error Handling (Part 1 of 3) (Note 1), (2)

Error Condition Response

Protocol error

Start-of-packet spacing violation (SOP8)

Start of burst error (SOB)

Training pattern error

8N boundary error (8N_ERR)

A transition on the receiver data path that does not follow

Fig. 6.2. Data Path State Diagram of the SPI-4.2 Specification.

The SPI-4.2 specification states that SOP control words should not be less than 8 cycles apart.

Data or training data is received without a payload control word.

Training pattern errors (

err_rd_tp

) occur when one of the

following conditions occur:

■ Training control portion is too short.

■ Training control portion is too long.

■ Training data portion is too short.

■ Training data portion is too long.

■ Training control word is followed by something other

than another training control word or training data word.

■ Malformed data bus during a data or control word.

■ Missing

IDLE

before training pattern begins. (The

can be an EOP).

A burst that is neither a multiple of 16 bytes, nor an EOP.

■ Assert

err_rd_pr

cycle.

■ Asserts

err_rd_sop8

clock cycle. When this happens, the data is not affected.

■ Assert

err_rd_sob

cycle.

■ Data is dropped until a proper

payload control word is received.

■ Assert

err_rd_tp

the training pattern.

■ Channel aligner may not lock.

■ Some training pattern errors may

result in successive assertions of

err_rd_tp

the

interrupt (for example, Training Control portion > 10 cycles).

IDLE

■ Assert

err_rd_eightn

clock cycle.

■ Packet is marked as errored.

■ Consider error as a missing EOP.

■ Cleanly terminate packet

internally as an EOP-Abort. (3)

■ Process subsequent bursts as

per missing SOP.

for one clock

for one

at the end of

for one

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4–14 Chapter 4: Functional Description—Receiver

Error Flagging and Handling

Table 4–3. SPI-4.2 Protocol Error Handling (Part 2 of 3) (Note 1), (2)

Error Condition Response

Reserved control word

Reserved control words:

■ Reserved control word 0 (

RSV0) = CTL and

DAT[15:12] == 4’b0101

■ Reserved control word 1 (

RSV1

CTL and DAT[15:12] == 4’b0011

■ Extension control (

EXT) =

CTL and DAT[15:12] == 4’b0001

■ End of control word extension (

) =

EOE) = CTL and

■ Ignore reserved control words.

■ Assert the

stat_rd_rsv_cw

notification purposes.

■ The payload following the

reserved control word is not written into the FIFO buffer.

for

DAT[15:12] == 4’b0111

Reserved control words are identified by the assertion of

stat_rd_rsv_cw

the

rdint_clk

single

signal, which pulses high for a

clock cycle when a reserved control word is detected.The payload following the reserved control word is not written into any buffer.

■ Assert

err_rd_dip4

for one

clock cycle.

■ Optionally mark some or all open

packets with an Atlantic error. (Including packets with DIP-4 error at SOP). The packets have

aN_arxerr

asserted (high).

Single DIP-4 error

As part of the SPI-4.2 protocol control word content, the 4bit diagonal interleaved parity (DIP-4) is computed over the current control word and preceding data. A DIP-4 error

rdat

occurs when the DIP-4 calculated over the

line does

not match the DIP-4 value in the control word.

Refer to “DIP-4 Marking” on

page 4–16.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–15

Error Flagging and Handling

Table 4–3. SPI-4.2 Protocol Error Handling (Part 3 of 3) (Note 1), (2)

Error Condition Response

■ IP core asserts

stat_rd_dip4_oos bad_level

of consecutive DIP-4

when a

errors are detected (Refer to

“DIP-4 Out of Service Indication” on page 4–17).

■ Control input signal is provided

ctl_ry_rsfrm

(

) for you to force the receiver status channel logic to cease proper calendar framing

2’b11

and send continuous framing pattern. The transition from proper calendar frame to continuous framing occurs after the current calendar frame is

Burst of DIP-4 errors

Data bus out of alignment (consecutive DIP-4 errors over a programmable threshold)

completed.

■ The

ctl_ry_rsfrm

signal is controlled externally by user logic or software-controlled registers to initiate automatic retraining.

■ Asserting the

ctl_ry_rsfrm

signal does not affect the receiver operation as a SPI-4.2 sink.

■ Any incoming SPI-4.2 traffic

continues to be processed as usual.

■ Atlantic error checking is also

unaffected by the

ctl_ry_rsfrm

signal.

Refer to “DIP-4 Marking” on

page 4–16.

■ Assert

■ In the shared buffer with

err_ry_paddr.

embedded addressing mode, the

Packet address error

A packet address error (

err_ry_paddr

) occurs when a

packet is received with an out-of-range port address.

burst/packet is sent to the user logic, and it is up to the user logic to define and determine the course of action. In the individual buffers mode, the packet/burst is discarded.

Notes to Table 4–3:

(1) More than one error of the same type may occur per internal clock. In such a case, the error is only asserted once. (2) DIP-4 errors and protocol errors are independent. (3) Injection of the EOP-Abort may cause a missing SOP error to occur in the Atlantic FIFO buffer (if error checking is turned on).

When you use DPA, the protocol checker block does not function until the DPA is locked.

The latency from an error occurring on the SPI-4.2 interface to the assertion of the corresponding error signal is unspecified.

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4–16 Chapter 4: Functional Description—Receiver

Error Flagging and Handling

After the optional channel aligner, the training pattern is treated as discarded. The training pattern has no internal function because the data entering the IP core is already byte aligned.

A status flag, cycle at the end of the training pattern to indicate that a correct training pattern has been detected. This flag pulses once for every occurrence of 10 (repeated) training control words followed by 10 (repeated) training data words. This flag does not indicate that the data path has been deskewed.

DIP-4 Marking

The receiver IP core supports three different ways of handling DIP-4 errors. In the first mode, the none mode, the as errored. You should use a higher level CRC or FCS to detect packets with errors. In the second mode, the optimistic mode, the IP core only marks packets that have a high probability of having errors. In the third mode, the pessimistic mode, the IP core assumes the worst case and marks any packet that may have errors. In all modes, if the IP core detects a DIP-4 error, it asserts the

The optimistic and pessimistic modes are discussed further in these sub-sections, where an open packet is a packet for which a SOP but not an EOP has been received when the error was detected.

stat_rd_tp_flag

err_rd_dip4

IDLE

s and

, is also provided. This flag pulses high for one clock

signal is asserted but no packets are marked

err_rd_dip4

signal.

Optimistic Mode

This mode attempts to error individual bursts as opposed to entire packets. Any data burst incoming on the SPI-4.2 interface is marked with an Atlantic error if its starting payload control word contains a DIP-4 error, or its terminating control word contains a DIP-4 error.

If the starting payload control word contains a DIP-4 error, the asserted for as long as the burst is present on the Atlantic interface. If the terminating control word contains a DIP-4 error, the Atlantic data cycle of the burst.

The IP core does not keep track of open packets containing errors that have not been terminated with an EOP. The Atlantic error signal is not held until EOP and it is up to the user logic to ensure that errors are carried across continued packets if required.

1 In cases where the terminating control word contains an EOP, the associated

aN_arxmty

value is not rounded down to the nearest even value.

aN_arxerr

signal is asserted on the last

aN_arxerr

signal is

Pessimistic Mode

In the event of a DIP-4 error, all open packets are marked. All subsequent data for each port is marked until a new SOP for that port is received.

1 Because of the logic required to track open packets per ports, this feature uses a large

amount of logic for systems with many ports.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–17

Error Flagging and Handling

DIP-4 Out of Service Indication

A DIP-4 out-of-service (

stat_rd_dip4_oos

) status signal provides an in-service or outof-service indication based on recent DIP-4 errors. Two 4-bit inputs are associated with this signal: (

ctl_rd_dip4_bad_threshold

Figure 4–7. DIP-4 OOS State Machine

good_level (ctl_rd_dip4_good_threshold

) and

bad_level

If the receiver is in service (the

stat_rd_dip4_oos

errors are detected (up to 8 in 128-bit mode) in the current counter is incremented. If the bad counter reaches the receiver goes out of service by asserting the

is low) and one or more DIP-4

rdint_clk

bad_level

stat_rd_dip4_oos

threshold, the

signal. If any of the

cycle, the bad

DIP-4s received in the current cycle are good, the bad counter is cleared. So if both good and bad DIP-4s are received in the current cycle the bad counter is also cleared. If no control words are received, nothing happens.

If the receiver is in service and the bad threshold is set to 0 or 1, the receiver goes out of service as soon as a single DIP-4 error is detected.

If the receiver is out of service and there are no DIP-4 errors in the current

rdint_clk

clock cycle, the good counter is incremented. If the good counter reaches the

good_level

threshold, the receiver goes in service and asserts. If any DIP-4 errors are received in the current cycle, the counter is cleared. If no control words are received, nothing happens.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–18 Chapter 4: Functional Description—Receiver

Non-control word (payload)

Control word witih good DIP-4

Control word with bad DIP-4

SPI-4.2 Bus

Internal Parallel

Bus (Four-Lane)

Bad DIP-4 Counter

Resets

Counter

Increments by 1

Unchanged

Resets

Counter (1)

Resets

Counter

Resets

Counter

Error Flagging and Handling

The DIP-4 out-of-service status signal does not affect the data portion of the receiver. However, it does affect the status channel portion, causing framing to be sent to the adjacent device.

When reset, the reset is deasserted and a

stat_rd_dip4_oos

good_level

flag is asserted (high). It remains asserted until the

number of consecutive control words that do not

contain DIP-4 errors are received.

Figure 4–8 shows an example of the DIP-4 counter, where the receiver is in service

state and bad threshold is 3.

Figure 4–8. DIP-4 Counter (Note 1)

1 2 2

Notes to Figure 4–8:

(1) Receiving a good and a bad DIP-4 in the same parallel cycle resets the counter (does not increment it), so that OOS

does not trigger.

f For further information on the DIP-4, refer to the System Packet Interface Level 4 (SPI-4)

Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices, available

at www.oiforum.com.

Atlantic Interface Error Detection and Handling

When the Atlantic error checking parameter is turned on, a filtering block—the Atlantic FIFO buffer error checker—is instantiated at the write side of the FIFO buffer to ensure that the IP core does not pass errored packets.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–19

Error Flagging and Handling

Tab le 4– 4 summarizes the errors.

Table 4–4. Atlantic Error Handling (Part 1 of 2)

Error Condition Response

Missing SOP

■ Packet is not open.

■ End of packet (EOP) without

preceding SOP.

■ Data belonging to unopened

packet is discarded.

■ When it detects a missing SOP error, the Atlantic

FIFO buffer error checker block asserts the

err_ry_msopN

■ Data following a missing SOP is ignored for that

flag.

port until an EOP is detected.

■ Drops data not preceded by a SOP (data is not

readable via the Atlantic interface).

Refer to “Missing SOP” on page 4–21.

Missing EOP

■ Multiple packets are open.

■ SOP without a preceding EOP.

■ Data subsequent to the

detection of multiple open packets is discarded until an EOP is detected.

■ Assert

err_ry_meopN

for one clock cycle. When it detects a missing EOP error, the open packet is closed by forcing an EOP into the buffer and marking it with an error. When it is received on the user Atlantic interface side, the

aN_arxeop

and

■ The

stat_ry_mp_erradr

signals are asserted.

signal contains the

aN_arxerr

address of the failing packet.

■ Subsequent data that is rejected until the EOP is

detected is not signaled by the

err_ry_meopN

signal.

■ The

Empty non-zero

aN_arxmty

be zero whenever the

aN_arxeop

asserted.

■ If a new packet with a non-

zero value for MTY is received without an EOP, all subsequent data associated with that address is ignored until an EOP associated with that address is received.

inputs must

signal is not

■ When it detects the error, the open packet is

closed.

■ Assert

err_ry_meopN

for one clock cycle by forcing an EOP into the buffer and marking it with an error. When it is received on the transmit side,

aN_atxerr

the

and

aN_atxeop

signals are

asserted.

■ The signal

stat_ry_mp_erradr

contains the

address of the failing packet.

■ Subsequent data that is rejected until the EOP is

detected is not signaled by the

err_ry_meopN

signal.

■ If an EOP is forced, the

aN_atxerr

output signal is asserted. Generally this signal can be ignored, unless the

aN_atxeop

signal is also asserted.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–20 Chapter 4: Functional Description—Receiver

Error Flagging and Handling

Table 4–4. Atlantic Error Handling (Part 2 of 2)

Error Condition Response

Atlantic buffer overflow

■ The Atlantic FIFO buffer error

checker block also handles overflows

err_ry_fifo_oflwN

(

asserted).

■ If a packet is open when an

overflow occurs, the open packet is closed and all subsequent data associated with that address is ignored until an EOP associated with that address is received.

■ Assert the

err_ry_fifo_oflwN

flag until the

FIFO buffer is flushed.

■ Any open packets are truncated with EOP and

ERR signal. If the last successful write immediately before the overflow was an EOP, then truncation is not necessary.

■ All further writes to the FIFO buffer are discarded

and ignored.

■ The FIFO buffer is drained (due to the assurance

that an EOP is in the FIFO buffer). Draining is accomplished by the Atlantic sink logic (user logic) as it continues to read data from the FIFO buffer. Complete packets already written to the FIFO buffer before the overflow occurred are not corrupted and can be safely read.

■ Once the FIFO buffer is empty, the

err_ry_fifo_oflwN

is deasserted (low). Writes to the FIFO buffer are ignored until a SOP is received on that port.

■ Assert

Atlantic buffer underflow —

■ No loss of data if Atlantic compliant.

stat_aN_fifo_emptyN

FIFO buffer.

for each Atlantic

The Atlantic FIFO buffer error checker block checks for missing SOP and EOP markers, for each port. If these markers are found to be missing, their respective

err_ry_msopN

high for one

and

err_ry_meopN

rxsys_clk

signals are asserted (high). These signals remain

cycle. These error conditions do not correlate directly—in

terms of latency—to the data going into, or coming out of, the FIFO buffer.

1 Altera recommends that you assert the

ctl_ax_fifo_eopdav

signal with the error

checker to ensure the buffer is emptied in the event of an overflow.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–21

Missing SOP

aN_arx

eop

aN_arx

err

aN_arxtclk

aN_arxena

aN_arxsop

err_ry_msopN

aN_arx

eop

aN_arx

err

aN_arxtclk

aN_arxena

aN_arxsop

Error Flagging and Handling

Missing SOP

If incoming data contains one or more EOPs without corresponding SOPs (refer to

Figure 4–9), the block deasserts the enable after the last EOP (refer to Figure 4–10).

This deassertion indicates that the current data between the SOP to EOP transition is a valid packet, and that everything following the EOP is discarded until the next SOP is received. None of the packets are marked as errored, so it is up to the user logic to determine which cells or packets have been dropped.

Figure 4–9. Missing SOP Input Timing Diagram

Figure 4–10. Missing SOP Output Timing Diagram

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4–22 Chapter 4: Functional Description—Receiver

aN_rxclk

aN_arxena

aN_arxsop

aN_arxeop

err_ry_fifo_oflwN

aN_arxdav

Good Packet Interr upted Packet(s) Good Packet

Error Flagging and Handling

Missing EOP

Figure 4–11 and 4–22 show that if a SOP is detected during an open packet, the

err_ry_meop

ignored for that port until an EOP is received.

Figure 4–11. Missing EOP Input Timing Diagram

signal is asserted, an EOP is forced, the

err

signal is asserted, and data is

Packet A

aN_atxtclk

aN_atxena

aN_atxsop

aN_atx

eop

aN_atx

err

Figure 4–12. Missing EOP Output Timing Diagram

aN_arxtclk

aN_arxena

aN_arxsop

eop

aN_arx

err

err_ry_meop

Packet B

Figure 4–13. Overflow

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–23

Signals

Tab le 4– 5 through Table 4–11 list the I/O signals used in the receiver IP core. The

active low signals are suffixed by

Table 4–5. SPI-4.2 Receive Interface

Signal Direction Clock Domain Description

rdclk

rctl

rdat[15:0]

rsclk

rstat[1:0]

LVDS Clock Input

LVDS Input

LVTTL Output

rdclk

rsclk (rdint_clk)

SPI-4.2 differential receive clock. Double-data rate clock

rctl

and

rdat

synchronous to

SPI-4.2 differential receive control.

When set to a logic 1, the word on set to a logic 0, the word on

SPI-4.2 differential receive data bus. Bus carries packets/cells or in-band control words.

SPI-4.2 receive status clock. This signal uses a regular LVTTL data pin instead of a dedicated output clock pin. Derived from

rdclk

. Active if

SPI-4.2 receive status channel. Indicates the downstream device’s FIFO buffers’ fill level to the upstream device’s scheduler.

rdclk

is active.

rdat

is a control word. When

rdat

is a payload word.

Table 4–6. Global

Signal Direction Clock Domain Description

rdint_clk

rxsys_clk

rxreset_n

rxinfo_aot[12:0]

stat_rx_pll_locked

ctl_rx_pll_areset

Output

Input

Input Asynchronous

Output Static

Output Asynchronous

Input Asynchronous

rdint_clk

rxsys_clk

Derived from synchronous to this clock. Active if

System clock. Signals infixed with this clock.

Active low asynchronous reset to all internal logic, including Atlantic FIFO buffers. Refer to “Reset Structure” on

page 4–12.

Fixed output information signal that contains the current AOT number for the release.

Locked signal directly from fast PLL in variations, or enhanced PLL in quarter-rate variations.

Asynchronous reset signal directly to fast PLL in full rate variations, or enhanced PLL in quarter-rate variations.

rdclk

. Signals infixed with

_rd_

are

rdclk

is active.

_ry_

are synchronous to

ALTVDS

for full rate

ALTVDS

for

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–24 Chapter 4: Functional Description—Receiver

Signals

Table 4–7. Atlantic Receive Interface (Slave Source) (Note 1)

Signal Direction Clock Domain Description

Atlantic clock (one for each Atlantic interface). This input is absent

aN_arxclk

Input

and internally connected to

rxsys_clk

selected. Signals prefixed with

if a single clock domain is

aN_

are synchronous to this clock.

Atlantic data available (one for each Atlantic interface). Asserted when

aN_arxdav

Output

the Atlantic FIFO buffer has at least

ctl_ax_ftl

bytes available to

read.

aN_arxena

aN_arxdat[n:0]

aN_arxval

aN_arxsop

aN_arxeop

Input Atlantic enable (one for each Atlantic interface).

Output

Output Atlantic data valid (one for each Atlantic interface).

aN_arxclk

Atlantic data bus (one for each Atlantic interface). The width is set by the Atlantic interface width parameter.

Output Atlantic start of packet (one for each Atlantic interface).

Output Atlantic end of packet (one for each Atlantic interface).

Atlantic empty signal (one for each Atlantic interface). Number of

aN_arxmty[n:0]

aN_arxerr

aN_arxadr[7:0]

Note to Table 4–7:

(1) N is equal to the number of ports for the individual buffers mode; N is equal to zero for the shared buffer with embedded addressing mode.

Output

Output Atlantic error (one for each Atlantic interface).

Output

invalid octets on the upper bits of the Atlantic data bus ( Valid only when

width/8)

aN_arxeop

is asserted. The width is l

Atlantic port address (one for each Atlantic interface). Only present for the shared buffer with embedded addressing mode.

aN_arxdat

og2(Atlantic

Table 4–8. Atlantic FIFO Buffer Control and Status (Part 1 of 2)

Signal Direction Clock Domain Description

ctl_ax_ftl[n:0]

(1) Input

Input –

ctl_ax_fifo_eopdav

err_aN_fifo_parityN

stat_aN_fifo_emptyN

Static reset

Output

aN_arxclk

FIFO buffer threshold low determines when to inform the user logic that data is available via the

aN_arxdav

signal. This threshold applies to all buffers. Units are in bytes. Only change at reset.

dav

Assert to turn on

when there is an end of packet below the FTL threshold. Value applies to all Atlantic buffers. Only change at reset.

Indicates that the FIFO buffer has detected a parity error (one for each Atlantic buffer).

Indicates that the FIFO buffer has underflowed. Asserted for one cycle if a buffer read fails because the buffer is empty (one for each Atlantic interface).

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Chapter 4: Functional Description—Receiver 4–25

Signals

Table 4–8. Atlantic FIFO Buffer Control and Status (Part 2 of 2)

Signal Direction Clock Domain Description

err_ry_fifo_oflwN

ctl_ry_errchk_chkpkt

err_ry_msopN

err_ry_meopN

stat_ry_mp_erradr[7:0]

Output

Input – Static reset

Output

rxsys_clk

Indicates that the FIFO buffer has overflowed, and data has been lost (one for each Atlantic interface).

Atlantic FIFO error checking enable. Disable to ignore missing SOP and missing EOP detection and correction. Value applies to all Atlantic buffer levels. Only change at reset.

Indicates a packet was received on the SPI-4.2 bus with a missing start of packet (one for each Atlantic buffer).

Indicates a packet was received on the SPI-4.2 bus with a missing end of packet (one for each Atlantic buffer).

Address qualifier for

err_ry_meop

and

err_ry_msop

flags. Only present for the shared buffer with embedded addressing mode.

Note to Table 4–8:

(1) For 128-and 64-bit variations, N is equal to log2(buffer size /(data path width × 16). For 32-bit variations, N is equal to log2(buffer size/data

path width×8).

Table 4–9. SPI-4.2 Channel Control and Status (Part 1 of 3)

Signal Direction Clock Domain Description

Almost empty defines starving to hungry threshold.

ctl_ry_ae[n:0]

Input

Units are in bytes. Value applies to all Atlantic buffers. Only change at reset.

Almost full defines hungry to satisfied threshold. Units

ctl_ry_af[n:0]

Input

are in bytes. Value applies to all Atlantic buffers. Only change at reset.

ctl_ry_fifostatoverride

ctl_ry_extstat_val

(1) Input

ctl_ry_extstat_adr[7:0]

ctl_ry_extstat[1:0]

(1) Input

Input Static

(1) Input

rxsys_clk

Asserting this signal allows external logic to control the outgoing status of each port. Only change at reset.

Valid qualifier for the external status input. This value is ignored if

ctl_ry_fifostatoverride

is deasserted.

Port number for the external status value. This value is ignored if

ctl_ry_fifostatoverride

Status for port indicated by This value is ignored if

ctl_ry_fifostatoverride

ctl_ry_extstat_adr

is deasserted.

deasserted.

Input -

ctl_rs_statedge

Static

rsclk

constant

Note to Table 4–9:

(1) The external status address you provide does not have to be incrementing or have any set sequence. You can provide any address value, at any

time. If the external address provided is for an unprovisioned port, the value is written into the internal RAM at that address, but the internal status block never reads from that location.

Controls the edge of

rstat

occur. (1 = positive edge, 0 = negative edge).

rsclk

on which transitions of

Only change at reset.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–26 Chapter 4: Functional Description—Receiver

Signals

Table 4–9. SPI-4.2 Channel Control and Status (Part 2 of 3)

Signal Direction Clock Domain Description

ctl_ry_rsfrm

Input

When asserted, the receiver status channel into framing mode beginning at the end of the next frame. You can use

ctl_ry_rsfrm

signal forces the

ctl_ry_rsfrm

to indicate that the receiver requires retraining.

If you assert

ctl_ry_dip2err_ins

while it is calculating the DIP2, it inverts it. It does not invert the statuses on the way and does not wait for the end of the

ctl_ry_dip2err_ins

Input

calendar to do the inversion. Also, if the error is set for the calendar length (plus 2 cycles, 1 for DIP2 one for FRM), it is only active on one DIP2 calculation. Therefore you should not see two consecutive DIP2 errors.

stat_ry_disabled

stat_ry_dip2state

Output

Indicates that the calendar state machine is disabled, and is transmitting continuous framing.

Indicates that the calendar state machine is in DIP-2 state.

Indicates that the status FIFO buffer has underflowed or overflowed causing the status finite state machine to go

err_ry_stat_fifo

Output

rxsys_clk

into continuous framing state (refer to “Single Clock

Mode” on page 4–9). If the status FIFO buffer regularly

underflows or overflows, ensure the clock relationships meet Altera guidelines.

Sets the length of the calendar in the outgoing status frame. Zero is interpreted as 256. This port is absent if

ctl_ry_callen[7:0]

Input

asymmetric port support is turned on. Only change at reset, or when

ctl_ry_rsfrm

stat_ry_disabled

are both asserted.

and

Sets the number of status calendar repetitions between framing and DIP-2 in the outgoing status frame. If

ctl_ry_calm[7:0]

Input

err_ry_stat_fifo

the number of repetitions. Refer to “Single Clock Mode”

on page 4–9. Zero is interpreted as 256. This port is

is asserted, you need to increase

absent if asymmetric port support is turned on. Only change at reset, or when

stat_ry_disabled

are both asserted.

ctl_ry_rsfrm

and

Indicates the currently selected calendar when hitless

stat_ry_calsel

Output

bandwidth reprovisioning is enabled. It is set to zero otherwise. This port is absent if asymmetric port support is turned off.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–27

Signals

Table 4–9. SPI-4.2 Channel Control and Status (Part 3 of 3)

Signal Direction Clock Domain Description

rav_clk

Input

Avalon-MM clock. Signals prefixed with synchronous to this clock. This port is absent if

rav_

are

asymmetric port support is turned off.

rav_address[3:0]

rav_chipselect

rav_write

rav_read

rav_writedata[15:0]

rav_readdata[15:0]

rav_waitrequest

Note to Table 4–9:

(1) The nominal phase offset between the clock and data is 180, you may want to put some timing constraints between the clock and status block.

You must take into account the trace delay difference between the clock and status block, to compensate for any difference.

Input

Output

rav_clk

Avalon-MM address. This port is absent if asymmetric port support is turned off.

Avalon-MM chip select. This port is absent if asymmetric port support is turned off.

Avalon-MM write enable. This port is absent if asymmetric port support is turned off.

Avalon-MM read enable. This port is absent if asymmetric port support is turned off.

Avalon-MM write data. This port is absent if asymmetric port support is turned off.

Avalon-MM wait request. This port is absent if asymmetric port support is turned off.

Table 4–10. DPA Control and Status

Signal Direction Clock Domain Description

err_rd_dpa

stat_rd_dpa_locked

stat_rd_dpa_lvds_locked[16:0]

ctl_rd_dpa_force_unlock

Output

Input

rdint_clk

Error flag to indicate that the DPA circuitry could not find byte alignment. This port is absent if DPA is turned off.

When this signal is high, it indicates that the DPA aligner has aligned to the training pattern. This port is absent if DPA is turned off.

When this signal is high, it indicates that the DPA PLL has locked. This port is absent if DPA is turned off.

Forces the DPA circuitry and PLL to unlock and retrain. This port is absent if DPA is turned off.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–28 Chapter 4: Functional Description—Receiver

Avalon-MM Interface Register Map

Table 4–11. Data Path Control and Status

Signal Direction Clock Domain Description

stat_rd_rdat_sync

stat_rd_tp_flag

stat_rd_rsv_cw

ctl_rd_dip4_good_ threshold[3:0]

ctl_rd_dip4_bad_ threshold[3:0]

stat_rd_dip4_oos

err_rd_dip4

err_rd_pr

err_rd_tp

err_rd_sob

err_rd_sop8

err_rd_abuf_oflw

ctl_rd_abuf_flush

err_rd_eightn

err_ry_paddr

err_rd_eop_abort

err_rd_pad_byte_ non_zero

Output

Input

Output

rdint_clk

Output

Input

Output

Output Invalid address received.

Output Indicates that the receiver has detected an EOP Abort.

Output

rdint_clk

Main receiver data path sync output signal. Combination of DPA, channel aligner sync, and DIP-4 status.

Indicates that the receiver has detected a training pattern. This signal is for debug purposes only. It does not indicate that the data path is deskewed.

Indicates that the receiver has detected a reserved control word. This signal is provided for information purposes only.

Number of consecutive correct DIP-4s to clear

stat_rd_dip4_oos

Number of consecutive DIP-4 errors to set

stat_rd_dip4_oos

Receiver’s out-of-service flag. When asserted, the IP core is still passing data, but is receiving DIP-4 errors above a threshold.

Each clock cycle asserted indicates that one or more (depending on the data path width parameter) calculated DIP-4 values did not match the received DIP-4 values.

Indicates that the receiver has detected a miscellaneous protocol error. These errors correspond to invalid state transitions in the data path state machine.

Indicates that the receiver has detected an error in the training pattern.

Indicates that the receiver has detected a data burst that does not start on a payload control word.

SOP violation. Two SOPs occurred less than eight cycles apart.

Indicates that an internal buffer has overflowed and data has been lost.

Flushes an internal buffer. While asserted, no data is written to the Atlantic buffer(s). Data continues to be lost until deasserted. The asserted for one assertion has to be done after minimum of approximately 20 cycles, because some ABUF internal signals are sent from one clock domain to another.

Indicates that the receiver has detected a burst that was not a multiple of 16 bytes.

Indicates that the receiver has detected an odd-sized burst (in bytes), and the invalid pad byte was not zero.

. Only change at reset.

ctl_rd_abuf_flush

rdint_clk

cycle only, and any subsequent

rdat

signal must be

Avalon-MM Interface Register Map

Tab le 4– 12 lists the Avalon-MM interface registers.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–29

Avalon-MM Interface Register Map

1 If the hitless bandwidth repositioning (

CALLEN1

1 Only change the

, and

CALMEM_DAT1

registers become reserved.

CALM0, CALLEN0

, and

CALM1, CALLEN1

when the

Table 4–12. Avalon-MM Interface Register Map

Address Bits Name Type Description

27:0

37:0

49:0

59:0

69:0

77:0

87:0

9..15 —

12:0

15:13

AOT_ID

BLOCK_ID

HBWR_EN

RSFRM

CALSEL_REQ

CALSEL_ACT

RSERVED

DISABLED

CALM0

CALM1

CALLEN0

CALLEN1

CALMEM_ADR

CALMEM_DAT0

CALMEM_DAT1

RESERVED

, and

CALMEM_DAT1

CALSEL_ACT

Read write control

Read only status AOT code

Read only status Block ID

Read write control

Read only status

Reserved Reserved.

Read only status Mirror of

Read write control

Read write indirect control

Read write indirect data

Reserved Reserved.

HBWR

) register is not enabled, the

CALMEM_DAT0

CALSEL_ACT

registers when the

HBWR_EN

frame.

RSFRM

framing word next frame boundary. Regular behavior resumes when this bit is cleared. The value of the register is

ctl_ry_rsfrm

the

This bit resets to one. Therefore, you must reprogram the calendar and clear this bit whenever the IP core is reset.

CALSEL_REQ

at the next frame boundary. 0=

CALSEL_ACT

'b01

CALM

when

CALM

when

CALLEN

Refer to

If write, RAM and

If read, RAM, and resulting read data is captured in

CALMEM_DAT0

If write, RAM and

If read, RAM, and resulting read data is captured in

CALMEM_DAT1

registers when the

DISABLED

enables the calendar select word in the status

disables the status finite state machine. The

'b11

is sent continuously starting at the

input.

sets the value of the calendar select word

is the active calendar select word.

, 1=

'b10

stat_ry_disabled

CALSEL_ACT

when

CALSEL_ACT

when

CALSEL_ACT

CALMEM_DAT0

CALMEM_ADR

CALMEM_DAT0

CALMEM_ADR

CALMEM_DAT1

CALMEM_ADR

=0.

=1.

=0.

=1.

and

is applied to the write address of

is applied to the write data.

is applied to read address of

is applied to the write address of

is applied to the write data.

is applied to read address of

CALM1

DISABLED

'b01

, 1=

'b10

CALMEM_DAT1

ed with

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–30 Chapter 4: Functional Description—Receiver

FPGA

Receiver MegaCore Function

SPI-4.2

Buffer 1

Buffer 2

Buffer

Status

Processor

Status

Generator

& Port

Table

Status

Transmit

Data Latency

Status Latency

Receiver Processor

(ALTLVDS, DPA,

CTL Word Processor)

Atlantic Buffer,

Latency Information

The receiver IP cores involve two kinds of latency: data latency and status transmit latency.

Data latency is defined as the latency from the SPI-4.2 LVDS receive pins to the internal Atlantic interface that is writing into the buffer(s). For the shared buffer with embedded addressing mode, it does not include the time the data spends in the buffer.

Status transmit latency is the number of clock cycles from when the status is provided from the user logic or the Atlantic buffer until it is transmitted to the adjacent device, assuming that the status channel is not disabled. It does not include the latency involved in waiting for the previous transmit message to complete, or in waiting for the status for other ports to be sent.

Figure 4–14 on page 4–30 shows a picture of the L

receiver finish gives the receiver L mode.

Figure 4–14. L

) for a receiver using the individual buffers

MAX

Individual Buffers Mode Overview

MAX

contributions (receiver start to

MAX

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 4: Functional Description—Receiver 4–31

Latency Information

Tab le 4– 13 lists the latency numbers for receiver IP cores.

Table 4–13. Receiver Latency

IP core

Data Latency

(Bytes on SPI-4.2 Interface)

Status Transmit Latency

(Bytes on SPI-4.2 Interface)

128-bit shared buffer with embedded addressing 272 320

128-bit individual buffers 288 320

64-bit shared buffer with embedded addressing 152 320

64-bit individual buffers 160 320

32-bit shared buffer with embedded addressing 36 320

32-bit individual buffers 72 320

1 Data latency:

■ The values in Ta bl e 4 –1 3 do not include the latency through the user-side buffers.

■ For 64- and 128-bit data path width variations, the values assume that the clock-

crossing buffer is empty. Additional latency should be added if multiple continue traffic is expected.

■ The DPA adds 32 bytes for a 128-bit data path, and 16 bytes for a 64-bit data path.

For 64-bit variations using Stratix GX devices, the DPA adds an additional 24 bytes due to the extra clocking stage with the PLL.

■ The external support in the shared buffer with embedded addressing mode adds

8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.

1 For status latency, the values do not include waiting for the appropriate time slot in

the status channel for the status to be transmitted.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

4–32 Chapter 4: Functional Description—Receiver

Latency Information

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

5. Functional Description—Transmitter

The POS-PHY Level 4 IP core consists of the main SPI-4.2 processing logic, and one of two first-in first-out (FIFO) buffer options: a single shared buffer with embedded addressing and support for external scheduling, or an individual buffer for each port including a full scheduler.

When the POS-PHY Level 4 IP core is configured as a transmitter, data flows from the Atlantic

™

interface to the SPI-4.2 interface.

Features

■ Sends data packets on the SPI-4.2 interface

■ Inserts control words

■ Generates DIP-4

■ Inserts training sequence

■ Manages the FIFO buffer status

Block Description

Figure 5–1 on page 5–1 shows the blocks and clocks that comprise the transmitter IP

core.

Figure 5–1. Block Diagram—Transmitter (Note 1) and (2)

tdint_clk

tdclk

SPI4.2

Interface

trefclk

Parallel-to-Serial

Converter

Data

Processor

Scheduler

(Note 2)

Atlantic Buffer 0

Atlantic Interface 0

tsclk

Status PHY Status FSM

Status

rav_clk

Scheduler

FIFO Buffer

User FIFO

Buffer

Atlantic Buffer N (Note 2)

Atlantic Interface N

txsys_cl

Notes to Figure 5–1:

(1) The dotted lines illustrate the clock domain separations. (2) These blocks and signals are only present when the individual buffers mode is selected.

This section describes the top-level blocks of the POS-PHY Level 4 transmitter IP core.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–2 Chapter 5: Functional Description—Transmitter

Block Description

Atlantic Buffers

The Atlantic FIFO buffers provide the following features:

■ Slave-sink Atlantic interface on the user side

■ Configurable buffer size

■ Multiple clock domain support

■ Overflow error indication and FIFO buffer empty indication

■ Atlantic interface error checking

■ Missing or spurious start-of-packet (SOP)/end-of-packet (EOP) detection and

correction

■ Optional overflow handling

For a complete single-PHY implementation, two modes are possible: individual buffers with the number of ports = 1, or a shared buffer with embedded addressing with the number of ports = 1. In the individual buffers mode, the credit-based flowcontrol scheduler is included.

1 Only single-PHY applications that require the more sophisticated credit-based

scheduler should select the individual buffers mode, because the shared buffer with embedded addressing mode has a simpler backpressure mechanism.

Shared Buffer with Embedded Addressing

When you turn on turn on Shared Buffer with Embedded Addressing, the POS-PHY Level 4 IP core consists of a shared buffer with embedded addressing, and the transmitter processor logic.

The shared buffer is a single Atlantic FIFO buffer, where for each data word a tag is carried containing the port number. There is no transmit scheduler provided with this mode; the data is simply pulled from the buffer and transmitted in the same order it was pushed in. This means that the order in which data bursts are transmitted on the SPI-4.2 bus is dictated by the order in which the user logic writes data to the FIFO buffer. The user logic is responsible for scheduling the transmit data and pushing it into the transmitter buffers so that it is SPI-4.2 compliant (including ensuring that burst sizes are properly maintained).

The shared FIFO buffer and the logic support up to 256 ports. If the Atlantic error checking feature is turned on, the logic for error checking supports the number of ports chosen as a parameter. The port width field remains fixed for 256 ports, and if packets for ports beyond the number of ports parameter are pushed into the transmit buffer, they are transmitted but are not checked for errors. All address bits are passed through the buffer unaffected

The shared buffer with embedded addressing mode supports two different backpressure mechanisms.

When the ignore backpressure feature is turned on, the transmitter sends packets whenever possible regardless of the incoming status channel. This mode assumes that external logic is properly controlling the scheduling of ports, managing credits (topping up to MaxBurst1 and MaxBurst2 as appropriate), and performing any other related functions. Packets are sent whenever there are at least burst unit size bytes in the Atlantic FIFO buffer, or an EOP.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–3

Block Description

When the ignore backpressure feature is turned off, the transmitter uses the status channel to decide whether or not to transmit. Packets are only sent when none of the ports in the incoming status channel are found to be satisfied, and there are at least burst unit size bytes in the Atlantic FIFO buffer, or an EOP. With this mode, there is a head-of-line blocking limitation, where if one port is satisfied it blocks all ports from transmitting.

Regardless of the mode you select, the scheduling and insertion of the SPI-4.2 training pattern is handled automatically by the IP core.

1 In the shared buffer with embedded addressing mode, the MaxBurst1 and MaxBurst2

parameters are unused because the user logic does the scheduling.

Individual Buffers

When you turn on Individual Buffers, the POS-PHY Level 4 IP core consists of the transmitter processor logic, a credit-based round-robin scheduler, and a separate Atlantic FIFO buffer for each port. Each buffer supports an optional Atlantic error checking block.

The advantages of the individual buffers mode are the included scheduler, and that each Atlantic interface can be accessed in parallel and independently. For individual buffers transmitter variations, scheduling logic decodes the incoming status channel and decides which buffer (port) to serve, and then reads from that buffer.

f For more information, refer to “Individual Buffers Transmit Scheduler (tx_sched)” on

page 5–3.

1 Because the number of ports directly increases the logic usage, the individual buffers

mode is not well suited for applications with a large number of ports.

Individual Buffers Transmit Scheduler (tx_sched)

For individual buffers variations, the transmit scheduler manages the SPI-4.2 per-port credits, and transmits data from the appropriate FIFO buffer.

The scheduler includes a next-credit table that is updated when status is received, and a second credit table that maintains the number of credits left. Each table has n port entries, where each entry is henceforth referred to as a register.

The next-credits register contains the number of credits corresponding to the latest status update. A starving status update loads the next-credit register with MaxBurst1. A hungry status update loads the next-credit register with MaxBurst2. A satisfied status update has no effect on the next-credits register.

Whenever a port is not selected, or exhausts its credit-counter register, the contents of the next-credits holding register are loaded into the credit-counter register, and the next-credits register is cleared. The next-credits register remains at zero until the next status update is received.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–4 Chapter 5: Functional Description—Transmitter

Block Description

As data is transmitted for a selected port, the credit-counter register is decreased. If the credit counter ever has insufficient credits for an entire burst unit size transfer, the scheduler switches to another port. This port cannot send again until the creditscounter register is reloaded with the contents of the next-credits holding register. Therefore, the MaxBurst1 and MaxBurst2 values must be greater than or equal to the burst unit size value.

If the buffer runs out of data before the credit-counter register reaches zero, the scheduler switches to another port. The leftover credits remain available until a new status message causes the credit counter to be overwritten with fresh credits. The port may be selected again before the next status update if the buffers fill again.

Both the next-credits and credits-counter tables are cleared when a loss of status sync (LOSS) occurs, resuming to normal behavior when the LOSS is cleared.

The scheduler normally switches when the credits are exhausted or the port runs out of data. If the scheduler switch on EOP feature is turned on, the scheduler also switches to another port when an EOP is sent.

Data Processor (tx_data_proc)

The data processor consists of two sub-blocks.

Atlantic Conversion

This block packs the data from the Atlantic interface into SPI-4.2 format.

Normally, this block enables data to be transferred from the transmit scheduler to the Atlantic FIFO buffer. If ignore backpressure is disabled, a satisfied status for any port causes the enable to drop at the next burst unit size boundary and data is not transferred. This backpressure mechanism is described in “Shared Buffer with

Embedded Addressing” on page 5–2.

1 The IP core cannot force insertion of control words except when the address changes

or there is insufficient data to send, regardless of the buffer type.

Control Word Insertion, DIP-4, and Training Pattern Insertion

This block inserts control words into the data path, and performs DIP-4 calculation and insertion.

An EOP-abort condition can be generated on the SPI-4.2 interface by asserting

aN_atxerr

one for which the EOP-abort bit is set in the transmitted control word.

This block also inserts the training pattern at the interval defined by the Maximum Training Sequence Interval parameter (MaxT). If the status channel is receiving a continuous framing pattern on the status channel, the IP core sends training patterns continuously.

with a valid

aN_atxeop

on the Atlantic interface. This condition is the only

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–5

Block Description

The training sequence includes one twenty words are separated into ten consecutive

1’b1

, followed by ten consecutive

IDLE

control word, plus

tdat

words of

tdat

words of

16’hF000

ALPHA

with

× 20 words. The

16’h0FFF

tctl

with

1’b0

tctl

. MaxT is defined in terms of bytes. In other words, a MaxT=16 value covers one SPI-4.2 cycle. The range for MaxT is from 0 to 65,535. If MaxT=0, the training pattern is sent only when in LOSS state (when Training patterns always begin on the rising edge of the clock (

If you change the

ALPHA

stat_ts_sync

is deasserted) and is not sent periodically.

tdclk

and MaxT values at run-time, the values update internally after the upcoming training pattern is sent. The only exception is when you change from MaxT=0 to MaxT!= 0. In this case, a training pattern with the new MaxT values is immediately sent out. Thus, you should change the

ALPHA

and

value before

the MaxT value if both values are to be altered during run time.

For control word insertion, two modes are possible: full transmitter or lite transmitter.

The lite transmitter mode is chosen by turning on Lite Transmitter in IP Toolbench. The lite transmitter uses a smaller, less efficient version of the Atlantic converter that allows packets to be padded with

IDLE

characters to a multiple of 16 bytes for 128-bit variations, or of 8 bytes for 64-bit variations. Although turning on Lite Transmitter lowers the effective bandwidth rate on the SPI-4.2 data bus, it greatly reduces the logic consumption.

In IP Toolbench turn off Lite Transmitter for the full transmitter mode. The full transmitter packs packets more tightly, padding with

IDLE

characters to multiples of 4 bytes. Thus SOP, COP, and EOP may be combined into a single control word, or may be in adjacent control words. Turning off Lite Transmitter increases the effective bandwidth rate on the SPI-4.2 data bus, but also increases the logic consumption.

IDLE

control words may be inserted for the following conditions:

■ One or two

■ To meet the SOP8 rule

■ The buffer runs empty or near empty in the shared buffer with embedded address

IDLE

s occur before a training pattern is inserted

mode

■ If no buffer or only one buffer has enough data to start a burst in the individual

buffers mode

Parallel to Serial Converter (tx_data_phy_altlvds)

The parallel to serial converter converts the parallel bus and control signals inside the FPGA into the high-speed SPI-4.2 clock, data, and control signals operating at twice, four times, or eight times the internal frequency.

Data words are sent on the Payload data words contain two bytes: bits [15:8] form the first byte, and bits [7:0] form the second byte. Bit 15 is the most significant bit (MSB), and bit 8 is the least significant bit (LSB) of the first byte. Bit 7 is the MSB, and bit 0 is the LSB of the second byte.

For 128- and 64-bit variations, an ALTLVDS IP core serializes the words into input high-speed

tdat, tctl

, and

tdat

data bus with the rising and falling edges of

tdclk

signals.

tdclk

The

tdclk

pin uses an output data pin, using the SERDES to send a repeating binary

10 pattern, guaranteeing minimal skew between the clock and data.

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5–6 Chapter 5: Functional Description—Transmitter

txsys_clk

stat_ty_extstat

stat_ty_extstat_val

stat_ty_extstat_adr

2'b00 2'b00 2'b00 2'b00 2'b01 2'bxx 2'bxx 2'bxx 2'b01 2'b00 2'b10

8'd0 8'd1 8'd2 8'd3 8'd4 8'dx 8'dx 8'dx 8'd5 8'd6 8'd7

2'b10

8'd0

Block Description

For 32-bit (quarter-rate) variations, an ALTDDIO IP core serializes the and

tctl

Status Processor

The transmitter IP core monitors and decodes the receiver. It handles framing, checking for DIP-2 errors, and extracting status. The status is provided to the transmit scheduler if present, and is always available to the user logic. The clock edge on which the transmitter samples the status channel is programmable.

The re-timed optimistic/pessimistic filtered status appears on the following signals:

■

ctl_ty_extstat_val

■

ctl_ty_extstat_adr

■

ctl_ty_extstat

These signals are synchronous with the positive edge of must be faster than the status clock,

Based on the received status channel, these signals are updated when the finite state machine is not in disable state. It is up to the user logic to ensure these signals are used when

In the individual buffers mode, if these signals are not connected to the user logic, the Quartus II software removes the status FIFO buffer (

lines.

: status

stat_ts_sync

tdclk, tdat

tstat

status channel from the

: asserted when the following two signals are valid

: port

tsclk

txsys_clk.

The

txsys_clk

is asserted.

tx_stat_fifo_user

Figure 5–2. Transmitter Timing Diagram

Note to Figure 5–2:

(1)

val

is negated when the internal status FIFO buffer empties.

Given a calendar slot number, the status processor determines which port's status belongs in the slot according to the calendar that it stores. When Asymmetric Port Support is turned off, the port number corresponds with the slot number (that is, slot one is port one, and so on). When Asymmetric Port Support is turned on, a programmable calendar is stored in memory, and the port corresponding to the slot is looked up.

1 If the Asymmetric Port Support parameter is turned on, the Avalon

MemoryMapped (Avalon-MM) registers must be programmed prior to releasing the (refer to Appendix E and the “Avalon-MM Interface Register Map” on page 5–24).

rsfrm

bit

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Chapter 5: Functional Description—Transmitter 5–7

Block Description

When the ignore backpressure feature is turned off (always off for the individual buffers mode), and the status channel informs the Atlantic converter that one port is satisfied, all ports stop sending.

Status Channel Interpretation Modes

The status FIFO buffers of the transmitter IP core support two status channel interpretation modes: pessimistic and optimistic. The mode is applied to the status sent to the scheduler (individual buffers mode) and to the user logic.

Pessimistic Mode

The last calendar length of the incoming status frame is stored in a FIFO buffer until a DIP-2 is received. If a DIP-2 containing errors is received, the status from that frame is dropped, and the transmit scheduler does not get any new credits. If the DIP-2 is errorless, the status is sent to the user logic and scheduler.

1 The pessimistic mode causes the latency in receiving a valid status message to be

calendar multiplier × calendar length is significant for systems with large calendar length or large calendar multiplier values.

tsclk

cycles longer than the optimistic mode. This

Optimistic Mode

The status information is provided to the user and transmit scheduler as soon as it can pass through the clock-crossing FIFO buffers, before the DIP-2 cycle is even received. DIP-2 errors are flagged, but have no effect on the status provided to the user, or to the scheduler.

1 In either mode, the

stat_ts_dip2state

signal indicates when a DIP-2 has been

received at the finite state machine.

Status Bypass Port

The status bypass port copies the values of the status signals going to the IP core. DIP2 errors are not calculated on this port. The port is output only and can therefore be left unconnected or undeclared. This interface provides the following signals on the

tsclk

■

stat_ts_sync

■

stat_ts_disabled

■

stat_ts_dip2state

■

stat_ts_frmstate

■

stat_ts_extstat_adr

■

stat_ts_extstat

f For more information on the signals, refer to Table 5–7 on page 5–19.

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5–8 Chapter 5: Functional Description—Transmitter

Clock Structure

Figure 5–3 on page 5–8 gives an example of the timing for the status bypass port.

Figure 5–3. Example Timing Diagram for the Status Bypass Port

tsclk

stat_ts_sync

stat_ts_disabled

stat_ts_extstat

stat_ts_extstat_adr

stat_ts_dip2state

stat_ts_frmstate

Clock Structure

With the Atlantic FIFO clock mode parameter in IP Toolbench, you can parameterize the transmitter in one of the following two clocking structures:

■ Single clock domain

■ Multiple clock domain

All data path width variations of the IP core use a common clocking structure.

1 All clocks are asynchronous and paths between the domains can be cut.

The transmitter has three primary clock domains.

The first primary clock domain is associated with the SPI-4.2 transmit status channel and is controlled by the channel processing is controlled by this clock.

33000033000

2'b00 2'b00 2'b00 2'b01 2'b02 2'b03 2'b00 2'b00 2'b00 2'b01 2'b02 2'b03 2'b00

tsclk

input. All of the logic pertaining to the SPI-4.2 status

The second primary clock domain is a a common clock, protocol logic and all Atlantic FIFO buffers share. This write and read sides of the Atlantic FIFO buffers. The core, and is derived from

altlvds

block.

trefclk

via the phase-locked loop (PLL) in the transmit

tdint_clk tdint_clk

tdint_clk

, which the IP core’s

clocks both the

is an output of the IP

The third primary clock domain relays received transmit status channel information to the user logic. This clock domain is controlled by the applications,

txsys_clk

is on the same domain as

txsys_clk

tdint_clk

signal. In most

, but they are separated

for flexibility.

Single Clock Domain

In the single clock domain mode, the Atlantic FIFO buffers are instantiated as single clock domain buffers, thereby consuming fewer logic resources.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–9

Clock Structure

Multiple Clock Domain

In multiple clock domain mode, the and the read side of the Atlantic FIFO buffers.

In multiple clock mode, an extra input clock is instantiated for each Atlantic FIFO buffer in the IP core, which is used for the write side of the buffers. The naming convention for these input clocks is and can either be tied together or controlled individually.

Tab le 5– 1 shows the clock frequency values for a data rate of 800 Mbps on the SPI-4.2

bus.

Table 5–1. Clock Domains

Clock Domain Description

Transmit IP core clock

trefclk/tdint_clk

(

Transmit status channel

tsclk

clock (

System clock (

)

txsys_clk

tdint_clk

aN_atxclk

trefclk

The the output of a fast PLL. The various frequencies. For example, a SPI-4.2 bus rate of 800 Mbps requires a 100 MHz clock for a data path width of 128 bits, a 400 MHz clock for a data path width of 32 bits, and a 200 MHz clock for a data path width of 64 bits.

The SPI-4.2 specification specifies a maximum status clock of ¼ of the This clock may be independent of 100 MHz or less for a data path width of 128 or 64 bits, and of 25 MHz or less for a data path width of 32 bits.

The

)

txsys_clk

transfers status to the external status interface.

clock is the input to the IP core. The

trefclk

frequency must be faster than, or equal to, the

can be generated from multiple possible sources, for

tdclk

clocks the protocol logic of the IP core,

. These clocks are inputs to the IP core

tdint_clk

. For example, it is possible to have a frequency of

clock is an output wire, and is

tdclk

frequency.

tsclk

frequency. This clock

Transmit Atlantic clock

aN_atxclk

(

)

This clock is typically asynchronous to individual buffers mode, there may be as many clock domains as there are ports, and they are all allowed to be of different phase and frequency.

trefclk

, but this is not a restriction. In the

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–10 Chapter 5: Functional Description—Transmitter

Data

ProcessorSERDES

LVD S

PLL

LVTTL

Status

Processor

Atlantic Buffer 0

Atlantic Interface 0

a0_atxclk

tdat[15:0]

tctl

tdclk

txsys_clk

tdint_clk

altlvds Megafunction

tsclk

ctl_ts_statedge

trefclk

tstat[1:0]

Clock Structure

Figure 5–4 on page 5–10 shows the multiple clock domain clocking structure for the

transmitter IP core in full-rate mode.

Figure 5–4. Clock Layout Diagram (Full Rate)

Notes to Figure 5–4:

(1) Stratix and Stratix GX devices use

trefclk

for

tdint_clk

. All other device families use the PLL output clock. (2) The single clock mode removes the separate Atlantic clocks. (3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.

Figure 5–5 on page 5–11 shows the clocking structure for the transmitter IP core, for

32-bit (quarter rate) SPI-4.2 mode variations. For 32-bit variations, the ALTLVDS_TX block is replaced by an ALTDDIO_OUT block and there is no LVDS PLL function that is clocked by

trefclk

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–11

Data

Processor

LVTTL

Status

Processor

Scheduler

Atlantic

Buffer 0

Atlantic Interface 0

a0_atxclk

aN_atxclk (Note 2, 3)

tdat[15:0]

tctl

tdclk

txsys_clk

tdint_clk

altddio_out

tsclk

ctl_ts_statedge

trefclk

tstat[1:0]

Atlantic Buffer N

Atlantic Interface N

Reset Structure

1 The SPI-4.2

tdclk

is not a separate clock domain because it is not on an FPGA clock signal. Instead, alternating 1s and 0s are preloaded into the is generated using the same PLL as the rest of the data, the clock and data are launched at the same time. The same technique applies to the 32-bit data path width, where the ALTLVDS IP core is set to alternating 1s and 0s for the

Figure 5–5. Clock Layout Diagram (Quarter Rate)

tdclk

serializer. As

tdclk

signal.

tdclk

Reset Structure

By default, the internally metastable hardened and passed to each of the individual clock domains.

Asserting reset deletes all data in the buffers and resets all of the state bits in the error checking logic.

Error Flagging and Handling

This section outlines how the POS-PHY Level 4 transmitter IP core responds to various errors.

SPI-4.2 Error Detection and Handling

The transmitter IP core monitors and decodes the SPI-4.2 input status channel. When an error is detected, an error flag is asserted. The flag pulses high for one for each error. Errors occur when the received status channel does not match expectations set by the state machine shown in Figure 6.11 FIFO Status State Diagram (Sending Side) of the SPI-4.2 Specification.

txreset_n

signal is the asynchronous global reset for the IP core. It is

tsclk

period

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5–12 Chapter 5: Functional Description—Transmitter

Error Flagging and Handling

A DIP-2 error occurs when the DIP-2 code locally calculated on the received status message does not match the DIP-2 received in the status message. If a DIP-2 error occurs, the

err_ts_dip2

signal is asserted at the end of the calendar sequence for a

single clock cycle.

A framing status error occurs for three regions:

■ When something other than framing is received when the framing pattern is

expected.

■ When an unexpected reserved (

■ When Hitless B/W reprovisioning is turned on, and a calendar select word is not

‘b01

‘b10

If a framing status error occurs, the

The

stat_ts_sync

signal indicates that the status channel is synchronized. It is

‘b11

) is received.

err_ts_frm

signal is asserted for one cycle.

deasserted under the following conditions:

■ At start up, reset, or user

■ Continuous framing is received

■ The MAximum Calendar Length or Calendar Multiplier parameters of the status

rsfrm

channel are improperly configured

■ Continuous DIP-2 errors are received (more than DIP-2 bad threshold)

Two 4-bit inputs, control the

The

stat_ts_sync

consecutive, non-errored calendar sequences is received. When

ctl_ts_sync_good_theshold

stat_ts_sync

signal.

signal is asserted when a programmed

and

ctl_ts_sync_bad_theshold

good_level

stat_ts_sync

number of

is asserted, the IP core sends status normally, based on the received status. The transmitter’s credit and scheduling logic can send normal traffic (refer to Figure 5–6).

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Chapter 5: Functional Description—Transmitter 5–13

Error Flagging and Handling

The

stat_ts_sync

signal is deasserted when a programmed

bad_level

number of calendar sequences with frame errors or DIP-2 errors is received without a good frame. When the

stat_ts_sync

signal is deasserted, the transmitter stops transmitting data on the nearest burst unit size boundary or at the next EOP, and starts sending the training patterns continuously (refer to Figure 5–6).

Figure 5–6. Status Sync State Machine

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5–14 Chapter 5: Functional Description—Transmitter

Error Flagging and Handling

Tab le 5– 2 summarizes the SPI-4.2 protocol errors.

Table 5–2. SPI-4.2 Protocol Error Handling

Error Condition Response

■ When

■

stat_ts_sync

err_ts_dip2

assert

stat_ts_sync

is asserted,

remains asserted

(high).

Single DIP-2 or frame error has been detected

Assuming the bad_level input is greater

ctl_ts_sync_bad_theshold

than 1 (

Bit error on bus

)

■ Transmit output data (

unaffected.

■ For pessimistic mode, the received

calendar status is ignored, the status is not forwarded to the user logic, and the transmit scheduler is not updated

TDAT

) is

with new credits.

■ For optimistic mode, no action is

taken. An incorrect status value may be extracted and passed on to the scheduler.

Multiple consecutive DIP-2 or frame errors when sync is detected

Causes the bad_level counter to go over the bad level threshold

ctl_ts_sync_bad_theshold)

(

■ Bit errors on bus

■ Incorrect status edge

■ Calendar multiplier and

Maximum calendar length values do not match the far-end values

■ Receiver is sending incorrect

calendar multiplier or calendar length values

■ Receiver sending corrupted

status frames

■ When

stat_ts_sync

is asserted, the

scheduler ignores a value of 11.

■ When

stat_ts_sync

is not asserted, the state machine returns to the disabled state and waits for the next framing pattern.

■ All credits are revoked.

■ Data stops transmitting on the nearest

burst unit size boundary or EOP.

■ Training patterns are sent

continuously.

■ The data in the buffer is untouched.

■ Once the status channel regains sync,

the transmitter restarts, and packet transfers resume from where they left off (that is, continue open packets).

Atlantic Interface Error Detection and Handling

The Atlantic FIFO buffer error checker block checks for missing SOP and EOP markers, for each port. If these markers are found to be missing, their respective

err_aN_msopN

These signals remain high for one correlate directly—in terms of latency—to the data coming out of the FIFO buffer.

When a missing SOP error is detected, the Atlantic FIFO error checker block asserts the

err_aN_msopN

for that port until a SOP is detected.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

and

err_aN_meopN

signals are asserted and the packet is corrected.

aN_atxclk

cycle. These error conditions do not

flag and filters the burst. Data following a missing SOP is ignored

Chapter 5: Functional Description—Transmitter 5–15

err_ry_msopN

aN_atx

eop

aN_atx

err

aN_atxtclk

aN_atxena

aN_atxsop

Error Flagging and Handling

If a SOP is detected during an open packet, then

err_aN_meopN

is asserted. The packet is terminated with an EOP-Abort, and data is ignored for that port until an EOP is received.

If a MTY is non-zero when a missing EOP is not asserted, then

err_aN_meopN

is asserted. The packet is terminated with an EOP-Abort, and data is ignored for that port until a SOP is received.

The Atlantic FIFO buffer error checker block also handles overflows. If an overflow occurs, the error checker block rejects all inputs until the buffer is drained of all of its data (

err_aN_fifo_oflwN

is asserted), however existing internal calendar values are left untouched. Any open packets are truncated with the EOP and ERR signals (this leads to EOP abort on the SPI-4.2 bus). If the last successful write immediately before the overflow was an EOP, then truncation is unnecessary. All writes to the buffer are discarded and ignored. The Atlantic write

aN_atxdav

signal is forced low (to indicate to the user logic to stop writing) during the flushing operation. The buffer is fully flushed out (due to the assurance that no EOP is present in the buffer). Flushing is accomplished by the transmitter IP core as it continues to read data from the buffer. Complete packets already written to the buffer before the overflow occurred are not corrupted and are safely transmitted. Once the buffer is empty, the released and the

err_aN_fifo_oflwN

flag is deasserted low. Writes to the buffer are

aN_atxdav

signal is

ignored until a SOP is received, for each port that had an open packet during the overflow. Refer to Figure 5–11 on page 5–16.

Missing SOP

Figure 5–7 and Figure 5–8 show missing SOP.

Figure 5–7. Atlantic Interface with Missing SOP

aN_atxtclk

aN_atxena

aN_atxsop

aN_atx

eop

aN_atx

err

Missing SOP

Figure 5–8. Output from Atlantic Error Checker Block (Corrected MSOP)

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5–16 Chapter 5: Functional Description—Transmitter

err_ry_meopN

aN_atx

eop

aN_atx

err

aN_atxtclk

aN_atxena

aN_atxsop

aN_atx

eop

err_aN_

fifo_oflwN

aN_atx

dav

Good Packet

Terminated Packet Good Packet

aN_atx

err

aN_atxtclk

aN_atxena

aN_atxsop

Signals

Missing EOP

Figure 5–9 and Figure 5–10 show missing EOP.

Figure 5–9. Atlantic Interface with Missing EOP

aN_atxtclk

aN_atxena

aN_atxsop

aN_atx

eop

aN_atx

err

Packet A

Packet B

Figure 5–10. Output from Atlantic Error Checking Block (Corrected MEOP)

Figure 5–11. Overflow

Signals

Figure 5–11 shows overflow.

Tab le 5– 3 through 5–24 list the transmitter IP core I/O signals. The active low signals

are suffixed by

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–17

Signals

Table 5–3. SPI-4.2 Transmit Interface

Signal Direction

tdclk

tctl

tdat[15:0]

tsclk

tstat[1:0]

Output

Input

Table 5–4. Global

Signal Direction Clock Domain Description

trefclk

tdint_clk

txsys_clk

txreset_n

txinfo_aot[12:0]

stat_tx_pll_locked

ctl_tx_pll_areset

Input

Output

Input

Input Asynchronous

Output Static

Output Asynchronous

Input

Clock

Domain

tdclk

tsclk

(either edge)

trefclk

tdint_clk

txsys_clk

Description

SPI-4.2 differential transmit clock. Double-data rate clock

tctl

and

tdat

synchronous to

SPI-4.2 differential transmit control. When set to logic 1, the word on

tdat

is a control word. When set to logic 0, the word on

tdat

is a payload word.

SPI-4.2 differential transmit data bus. Bus carries packet/cell payload or in-band control words.

SPI-4.2 transmit status clock. All signals infixed by

_ts_

are

synchronous to this clock.

SPI-4.2 transmit status channel. Indicate the downstream device’s FIFO buffers fill levels to the upstream device’s scheduler.

Transmitter reference clock. Typically route to LVDS PLL.

_tr_

Signals infixed by

Derived from

trefclk

are synchronous to this clock.

. Signals infixed by

_td_

are

synchronous to this clock.

System clock. Signals infixed by

_ty_

are synchronous to

this clock.

Active low asynchronous reset to all internal logic, including Atlantic FIFO buffers. Refer to “Reset Structure” on

page 5–11.

Fixed output information signal that contains the value for the current AOT number for the release.

Locked signal directly from fast PLL in

ALTLVDS

for full rate

variations. Absent in quarter-rate variations.

Asynchronous reset signal directly to fast PLL in

ALTLVDS

for

full-rate variations. Absent in quarter-rate variations.

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5–18 Chapter 5: Functional Description—Transmitter

Signals

Table 5–5. Atlantic Transmit Interface (Slave Sink) (Note 1)

Signal Direction

Clock

Domain

Description

Atlantic Clock (one for each Atlantic interface). This input is absent

aN_atxclk

Input

and internally connected to

tdint_clk

selected. Signals prefixed with

if a single clock domain is

aN_

are synchronous to this clock.

Atlantic data available (one for each Atlantic interface). Asserted when

aN_atxdav

Output

the Atlantic FIFO buffer has at least

ctl_atx_fth

bytes of free space

available.

aN_atxena

aN_atxdat[?:0]

aN_atxsop

aN_atxeop

Input Atlantic enable (one for each Atlantic interface).

Input

Input Atlantic start of packet (one for each Atlantic interface).

aN_atxclk

Atlantic data bus (one for each Atlantic interface). The width is set by the Atlantic interface width parameter.

Input Atlantic end of packet (one for each Atlantic interface).

Atlantic empty signal (one for each Atlantic interface). Number of

aN_atxmty[?:0]

Input

invalid octets on the lower bits of

aN_atxeop

is asserted, must be zero otherwise. The width is

log2(Atlantic interface width/8)

aN_atxerr

aN_atxadr[7:0]

Note to Table 5–5:

(1) N is equal to the number of ports for the individual buffers mode; N is equal to zero when you turn on Shared Buffer with Embedded

Addressing.

Input

Atlantic Error (one for each Atlantic interface). Translates to an EOPAbort on the transmit data bus.

Atlantic port address. Only present when you turn on turn on Shared Buffer with Embedded Addressing.

aN_atxdat

. Valid only when

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–19

Signals

Table 5–6. Atlantic Buffer Control and Status

Signal Direction Clock Domain Description

FIFO buffer threshold high determines when to inform the user logic that space is available via the

aN_atxdav

signals. Units are in bytes. Value applies

to all Atlantic buffers. Only change at reset.

Atlantic buffer error checking enable. Disable to bypass missing SOP and missing EOP detection and correction. Value applies to all Atlantic buffer levels. Only change at reset.

Indicates that the FIFO buffer has detected a parity error (one for each Atlantic buffer).

Indicates that the FIFO buffer has underflowed. Asserted for one cycle if a buffer read fails because

ctl_ax_fth[?:0]

ctl_ax_errchk_chkpkt

err_td_fifo_parityN

stat_td_fifo_emptyN

Input Static reset

Output

aN_atxclk

the buffer is empty (one for each Atlantic interface).

err_aN_fifo_oflwN

err_aN_msopN

err_aN_meopN

stat_aN_mp_erradrN[7:0]

Output

Indicates that the FIFO buffer has overflowed, and data has been lost (one for each Atlantic interface).

Indicates a missing start of packet error was detected on the incoming Atlantic interface.

Indicates a missing end of packet error was detected on the incoming Atlantic interface.

Address qualifier for

err_aN_msopN

err_aN_meopN

and

flags. (Shared Buffer with

Embedded Addressing only.)

Table 5–7. SPI-4.2 Status Channel Control and Status (Part 1 of 3)

Signal Direction Clock Domain Description

ctl_ts_status_mode

stat_ty_extstat_val

stat_ty_exstat_adr[7:0]

stat_ty_exstat[1:0]

Input Static reset

tsclk

Output

Output Port number for the received status value.

txsys_clk

Output Received status value.

Controls the filtering of framed status. Set to one to select optimistic processing of status, otherwise set to zero for pessimistic processing of status. Pessimistic behavior only passes status from the last calendar multiplier in error free frames to the user and scheduler. Optimistic behavior has the least latency, passing all status to the user and scheduler before determining if the status frame is error free. Only change at reset.

Valid qualifier for the received status value, after optimistic/pessimistic filtering.

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5–20 Chapter 5: Functional Description—Transmitter

Signals

Table 5–7. SPI-4.2 Status Channel Control and Status (Part 2 of 3)

Signal Direction Clock Domain Description

ctl_ts_statedge

Input Static constant

Controls the edge of

tsclk

on which

tstat

is sampled (1= positive edge; 0= negative edge). Only change at reset.

Number of status frames which must be error free

ctl_ts_sync_good_

threshold[3:0]

Input

(

err_ts_frm

=0 and

stat_ts_sync

err_ts_dip2

=0) to assert

. Zero is interpreted as one. Only

change at reset.

Number of status frames which must be errored

ctl_ts_sync_bad_

threshold[3:0]

Input

tsclk

(

err_ts_frm

=1 and

stat_ts_sync

err_ts_dip2

=1) to deassert

. Zero is interpreted as one. Only

change at reset.

Indicates status frames are well formed, according to

stat_ts_sync

Output

hysteresis with

ctl_ts_bad_threshold

and

ctl_ts_synch_good_threshold

Forces the status state machine into the disabled

ctl_ts_rsfrm

Input

state, beginning at the next frame, at which time

stat_ts_sync stat_ts_disabled

is forced low and

is asserted.

Indicates that the status state machine is in the disabled state. Asserted at startup, after the negative

stat_ts_disabled

Output

stat_ts_sync

edge of

ctl_ts_rsfrm

is asserted. Deasserted when a

, or at a frame boundary if

potentially valid framing pattern is detected. A

‘b11

followed by

stat_ts_dip2state

stat_ts_frmstate

stat_ts_exstat_adr[7:0]

stat_ts_exstat[1:0]

potentially valid framing word is

‘b11

Output

tsclk

anything other than

Indicates that the status state machine is in DIP-2 state.

Indicates that the status state machine is in framing state.

Output Port number for the received status value.

Output Received status value.

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Chapter 5: Functional Description—Transmitter 5–21

Signals

Table 5–7. SPI-4.2 Status Channel Control and Status (Part 3 of 3)

Signal Direction Clock Domain Description

Indicates the frame was malformed. Possible causes are:

■ Calendar did not begin with a framing word.

err_ts_frm

Output

■ Hitless bandwidth repositioning is turned on, and

‘b01

‘b10

calendar select word was not

■ Unexpected framing word was in the calendar

portion of the frame.

Asserted synchronous to

stat_ts_dip2state

Indicates the calculated DIP-2 did not match the DIP-

err_ts_dip2

Output

2 word in the status frame. Asserted synchronous to

stat_ts_dip2state

Sets the expected length of the calendar in the status frame. This port is absent if Asymmetric Port

ctl_ts_callen[7:0]

Input

tsclk

Support is turned on. Only change at reset, or when

ctl_ts_rsfrm

and

stat_ts_disabled

are both

asserted.

Sets the expected number of status calendar repetitions between framing and DIP-2 in the status

ctl_ts_calm[7:0]

Input

frame. This port is absent if Asymmetric Port Support is turned on. Only change at reset, or when

ctl_ts_rsfrm

and

stat_ts_disabled

are both

asserted.

Indicates the currently selected calendar when Hitless B/W reprovisioning is turned on. Zero

stat_ts_calsel

Output

indicates zero when Hitless B/W reprovisioning is turned off.

‘b01

, and one indicates

‘b10

. It is set to

This port is absent if Asymmetric Port Support is turned off.

tav_clk

Input

Avalon-MM clock. Signals prefixed by synchronous to this clock. This port is absent if

tav_

are

Asymmetric Port Support is turned off.

tav_address[3:0]

tav_chipselect

tav_write

tav_read

tav_writedata[15:0]

tav_readdata[15:0]

tav_waitrequest

Input

Output

tav_clk

Avalon-MM address. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM chip select. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM write enable. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM read enable. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM write data. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM read data. This port is absent if Asymmetric Port Support is turned off.

Avalon-MM wait request. This port is absent if Asymmetric Port Support is turned off.

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5–22 Chapter 5: Functional Description—Transmitter

Signals

Table 5–8. Data Path and Control Status (Part 1 of 2)

Signal Direction Clock Domain Description

Head-of-line blocking disable. When set to logic 1, the data path requests data from the scheduler or Atlantic buffer(s) whenever possible. When set to logic 0, status (after error checking) is monitored for

ctl_td_holb_disable

Input- Static reset

all ports, and while any port is satisfied, the transmitter stops requesting data from the scheduler or Atlantic buffer(s), and sends idle control words or training patterns. This input is tied to one in the IP Toolbench top-level file, if you use the individual buffers mode. Only change at reset.

Indicates if the IP core is currently head-of-line blocked. It is never asserted if

ctl_td_holb_disable

is set to logic 1.

stat_td_holb

Output

tdint_clk

Training sequence interval, measured from the end of the last training sequence to the beginning of the next training sequence. The actual interval may be slightly longer to maintain valid bursts according to

ctl_td_maxt[15:0]

Input

ctl_td_burstlen

. Setting to zero disables interval

training insertion. Training is always inserted if

stat_ts_sync

always begin on the positive edge of

is deasserted. Training patterns

tdclk

. Only

change at reset.

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Chapter 5: Functional Description—Transmitter 5–23

Signals

Table 5–8. Data Path and Control Status (Part 2 of 2)

Signal Direction Clock Domain Description

Number of training pattern sequence repetitions. This value only applies to interval training patterns. If a

ctl_td_alpha[7:0]

Input

training pattern is inserted due to

stat_ts_sync

deasserted, the training pattern lasts until

stat_ts_sync

is asserted, and the current 20-cycle

training pattern completes. Setting to zero results in

ALPHA

■ For the individual buffers mode, this input sets the

of 256. Only change at reset.

legal burst unit size, formerly known as burst length. A burst must end on either a non-zero

tdint_clk

multiple of

■ For the shared buffer with embedded addressing

ctl_td_burstlen

, or on an EOP.

mode, this input only limits when the IP core may read data from the buffer. This input enables

ctl_td_burstlen[9:0]

Input

delineating bursts, as in the individual buffers case, only if the user logic pushes bursts into the buffer with the desired delineation.

■ In either mode, this input also delays insertion of

training patterns after MaxT so that bursts are not interrupted.

■ Units are in bytes. Supports M to 1,024 bytes in

increments of M, where M equals 16 or 32 bytes depending on the Atlantic buffer width.

Sets the maximum burst size to be sent by the transmitter. A control word is inserted at the end of the burst limit. Burst limit values are restricted to multiples of burst unit size (set via

ctl_td_burstlimit[10:0]

Input

ctl_td_burstlen[9:0]

transmitter parameters, the values may be limited to

), and depending on other

a minimum value. You can use IP Toolbench to determine the valid values (set Parameter Type to Fixed Value to determine the valid values, and then set back to Real Time Programmable). The units are in bytes.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–24 Chapter 5: Functional Description—Transmitter

Avalon-MM Interface Register Map

Table 5–9. Scheduler Control and Status

Signal Direction Clock Domain Description

Maximum number of bytes that can be transmitted when the downstream FIFO buffer is starving. This number does not

ctl_td_mb1[10:0]

Input

imply that a control word is inserted. Units are in bytes. Supports 0 to 2,032 bytes in 16-byte increments. This port is absent if you turn on Shared Buffer with Embedded Addressing.

Maximum number of bytes that can be transmitted when the downstream FIFO buffer is hungry. This number does not

ctl_td_mb2[10:0]

Input

imply that a control word is inserted. Units are in bytes. Supports 0 to 2,032 bytes in 16-byte increments. This port is absent if you turn on Shared Buffer with Embedded Addressing.

This input determines the port switching behavior of the scheduler.

■ The scheduler always makes a port switch decision when

ctl_td_burstlen

■ Next credits are held in a table for all ports, and are

data is sent, or when an EOP is sent.

incremented by status updates.

■ Current credits are stored in a separate register for a single

tdint_clk

port while it is serviced, and become stale because status updates do not increment the value.

■ A port is only eligible for scheduling if there are greater

than or equal to

ctl_td_burstlen

and greater than or equal to

next credits available,

ctl_td_burstlen

data

available in the corresponding Atlantic FIFO buffer.

ctl_td_

switchmode[1:0]

Input Static reset

■ When ‘00’ (switch on EOP is turned off) the scheduler

switches when less than

ctl_td_burstlen

credits are available, or less than

ctl_td_burstlen

current

data

is available in the Atlantic buffer.

■ When ‘01’ (switch on EOP is turned on), the scheduler

switches when less than

ctl_td_burstlen

credits are available, or less than

ctl_td_burstlen

current

data

is available in the Atlantic buffer, or an EOP is sent.

■ When ‘10’ or ‘11’, the scheduler switches when

ctl_td_burstlen

■ In the IP Toolbench top-level file, the upper bit is always

data is sent, or an EOP is sent.

tied to zero, and the lower bit is tied depending on the value of the switch on end of packet feature. This port is absent if you turn on Shared Buffer with Embedded Addressing. Only change at reset.

Avalon-MM Interface Register Map

Tab le 5– 10 lists the Avalon-MM interface registers.

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–25

Avalon-MM Interface Register Map

1 If the hitless bandwidth repositioning (

CALLEN1, CALMEM_DAT

1 Only change the

equal to 1, or when the

CALLEN1, CALMEM_DAT1 CALSEL_ACT

Table 5–10. Avalon-MM Interface Register Map

Address Bits Name Type Description

27:0

37:0

49:0

59:0

69:0

77:0

8 7:0

9..15 —

12:0

15:13

AOT_ID

BLOCK_ID

HBWR_EN

RSFRM

RESERVED

CALSEL_ACT

SYNC

DISABLED

CALM0

CALM1

CALLEN0

CALLEN1

CALMEM_ADR

CALMEM_DAT0

CALMEM_DAT1

RESERVED

registers become reserved.

CALM0, CALLEN0, CALMEM_DAT0

CALSEL_ACT

registers when the

Read only status AOT code

Read only status Block ID

Read write control

Reserved Reserved.

Read only status

Read only status Mirror of

Read write control

Read write indirect control

Read write indirect data

Reserved Reserved.

HBWR

) register is not enabled, the

registers when the

DISABLED

HBWR_EN

frame.

RSFRM stat_ts_sync

of the current status frame. Regular behavior eventually resumes after this bit is cleared. The value of the register is

This bit resets to one. Therefore, you must reprogram the calendar and clear this bit whenever the IP core is reset.

CALSEL_ACT

CALM

CALLEN

Refer to

If write, then RAM with

If read, then RAM, and resulting read data is captured in

If write, then RAM with

If read, then RAM, and resulting read data is captured in

enables the calendar select word in the status

disables the status finite state machine. This forces

ed with the

'b10

stat_ts_sync

stat_ts_disabled

when

CALSEL_ACT

when

CALSEL_ACT

when

CALMEM_DAT0

CALMEM_ADR

CALMEM_DAT1

CALMEM_ADR

low and

ctl_ts_rsfrm

is the active calendar select word. 0=

CALSEL_ACT

CALMEM_ADR

stat_ts_disabled

input.

=0.

=1.

=0.

=1.

and

CALMEM_DAT1

is applied to the write address of

applied to the write data.

is applied to the read address of

is applied to the write address of

applied to the write data.

is applied to the read address of

CALM1

DISABLED

high at the end

CALMEM_DAT0

CALMEM_DAT1

CALM1

'b01

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–26 Chapter 5: Functional Description—Transmitter

Latency Information

The transmitter IP cores involve two kinds of latency: data latency and status receive latency.

Data latency is defined as the latency from the Atlantic interface that is reading from the buffer to the SPI-4.2 LVDS transmit pins. It does not include the latency through the buffer. For external status, the numbers assume that the the

tsclk

thus ensuring that the clock-crossing FIFO buffer is empty.

Status receive latency is defined as the latency from the point at which the last cycle of a valid status message is received (the DIP-2 error code) to the point at which the user logic or the transmit scheduler can use the status information. It does not include the time spent waiting for a complete, error-free status message.

aN_atxclk

is faster than

Figure 5–12 shows a generic picture of the L

transmitter finish gives the transmitter L

Figure 5–12. L

Top Level Overview

MAX

contributions (transmitter start to

MAX

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 5: Functional Description—Transmitter 5–27

Latency Information

Tab le 5– 11 lists the latency numbers for transmitter variations.

Table 5–11. Transmitter Latency

IP core

Data Latency

(Bytes on SPI-4.2 Interface)

Status Receive Latency

(Bytes on SPI-4.2 Interface)

128-bit shared buffer with embedded addressing 160 256

128-bit individual buffers 160 256

64-bit shared buffer with embedded addressing 128 256

64-bit individual buffers 128 256

32-bit shared buffer with embedded addressing 64 256

32-bit individual buffers 64 256

Data latency:

■ The values in Ta bl e 5 –11 do not include the latency through the user-side buffers.

■ The external support in the shared buffer with embedded addressing mode adds

8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.

Status latency:

■ The values do not include the time spent waiting for a complete error-free status

message. The resultant value also reflects the status channel mode—either optimistic or pessimistic.

■ Tu rni ng on Lite Transmitter adds up to 32 bytes for 128-bit data path widths, or

up to 16 bytes for 64-bit data path widths.

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

5–28 Chapter 5: Functional Description—Transmitter

Latency Information

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

The testbench stimulates the inputs and checks the outputs of the interfaces of the POS-PHY Level 4 IP core, demonstrating basic functionality.

The remainder of this section contains the following information about the testbench:

■ Receiver Testbench Description

■ Receiver Testbench Examples

■ Tr ans mitt er Tes tben ch D e scr i pti on

Receiver Testbench Description

The testbench provided with the receiver variations of the POS-PHY Level 4 IP core tests the following functions:

■ Using the Avalon-MM interface, program the calendar if Asymmetric Port

Support is turned on (refer to Appendix E)

6. Testbench

■ Synchronization of the IP core with the SPI-4.2 training pattern

■ Data integrity from the SPI-4.2 interface through the IP core variation to the

Atlantic back-end interface

■ Ability to send data to multiple ports

■ Verifies that the IP core correctly drives backpressure on the SPI-4.2 interface (this

test can be turned on and off)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

6–2 Chapter 6: Testbench

Packet Generation

POS-PHY Level 4

Atlantic Interface

Data Analyser (one per port)

Clock

Generator

Pin MonitorReset

SPI-4.2

Interface Device Under Test

Atlantic

Interface

POS-PHY

Variation

Level 4

Receiver

Receiver Testbench Description

The testbench consists of three basic modules: packet generation, user receiver variation, and a data analyzer. All testbench modules are in the <variation name>_tb.v file. The testbench also consists of multiple support modules for pin monitoring, clock generation, and reset generation (refer to Figure 6–1). The packet generation module generates SPI-4.2 packets. These packets are received by the receiver IP core, which processes the packets and converts them to Atlantic interface format. Finally, the data analyzer module receives the data from the Atlantic interface and verifies the correctness of the data with an individual monitor for each port.

Figure 6–1. Receiver Testbench

Table 6–1. Packet Format

Packet Byte Format Description

Header byte

Extra length byte

Number byte

Payload bytes

The packet generation module begins by sending the idle pattern ( the training pattern (

16'h0fff,16'hf000

) until the POS-PHY Level 4 receiver IP core is

16'h000f

) and then

synchronized to the data source.

The packet generation module then begins sending packets of lengths defined by the top-level testbench. To allow for automated packet checking, a special packet format is used. Table 6–1 shows the format of each packet.

{0,0,len[5:1],ext}

Contains information about the packet. the packet if the length can be encoded in six bits. If the length is

ext

beyond 32 bits,

is set to indicate that the next byte in the packet

len

represents the length of

contains the length information.

{size[16:0]}

{N[7:0] ^ port_num}

{N++^ port_num}

ext

is 1, the extended expected packet size shows the length of the

size

packet including the header (

Packet number (packet number begins at

XOR

one for each packet)

The following bytes in the packet are incremented by one and with the port number.

ed with the port number.

> 16 bytes) (optional).

'h01

and is incremented by

XOR

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Altera POS-PHY Level 4 IP Core User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Release Information

1. About This IP Core

Device Family Support

Features

General Description

Interfaces & Protocols

SPI-4.2 Interface

Atlantic Interface

Avalon-MM Interface

IP Core Verification

Performance and Resource Utilization

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Design Flow

2. Getting Started

IP Catalog and Parameter Editor

Using the Parameter Editor

Upgrading Outdated IP Cores

Upgrading IP Cores at the Command Line

Specify Parameters

Files Generated for Altera IP Cores (Legacy Parameter Editor)

Simulate the Design

Use the Testbench with the ModelSim Simulator

Use the Testbench with NativeLink

Compile the Design and Program a Device

3. Parameter Settings

Basic Parameters

Device Family

LVDS Data Rate

PLL Input Frequency

Data Path Width

Buffer Mode

Atlantic FIFO Buffer Clock

Atlantic Interface Width

Optional Features

Transmitter Options

Receiver Options

FIFO RAM Blocks

Protocol Parameters

Calendar Options

Transmitter Options

Receiver Options

4. Functional Description—Receiver

Features

Block Description

Data Receiver and Serial-to-Parallel Converter (rx_data_phy_altlvds)

DPA Channel Aligner (rx_data_phy_dpa)

ALTLVDS_RX IP Core

Channel Aligner

8:4 Serializer

Data Processor (rx_data_proc)

Control Word Processing & DIP-4

Clock-Domain Crossing Buffer

SOP Alignment & Atlantic Conversion

Atlantic Buffers

Shared Buffer with Embedded Addressing

Individual Buffers

Status Processor

Clock Structure

Single Clock Mode

Multiple Clock Mode

Requirements for rxsys_clk

Reset Structure

Error Flagging and Handling

SPI-4.2 Protocol Errors

DIP-4 Marking

Optimistic Mode

Pessimistic Mode

DIP-4 Out of Service Indication

Atlantic Interface Error Detection and Handling

Missing SOP

Missing EOP

Signals

Avalon-MM Interface Register Map

Latency Information

5. Functional Description—Transmitter