Altera POS-PHY Level 2 and 3 Compiler User Manual

POS-PHY Level 2 and 3 Compiler

User Guide

The IP described in this document is scheduled for product obsolescence and discontinued support as described in PDN0906. Therefore, Altera® does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

101 Innovation Drive San Jose, CA 95134 www.altera.com

MegaCore Version: 9.1 Document Date: November 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

UG-POSPHY2_3-9.1

Chapter 1. About This Compiler

Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Atlantic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Chapter 2. Getting Started

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

POS-PHY Level 2 & 3 Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Create a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Launch IP Toolbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Step 1: Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Step 2: Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

Step 3: Generate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

IP Functional Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Testbench with the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Testbench with NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Set Up Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Chapter 3. Functional Description

Example Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Example Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

POS-PHY Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Packet Data Width Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Packet FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

‘B’ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

Preliminary

Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

FIFO Buffer & Clock Selector Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Common B Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Parity Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

Pass Through Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

ParErr On Error Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

FIFO Buffer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Atlantic Interface FIFO Buffer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

FIFO Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Address & Packet Available Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

POS-PHY Level 3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

POS-PHY Level 2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15

Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

SX Always . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16

Global Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

POS-PHY Level 3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17

POS-PHY Level 2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22

Atlantic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–29

Signal Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30

Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31

Example Packet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31

MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation

Preliminary

Release Information

Tab le 1– 1 provides information about this release of the Altera® POS-PHY Level 2 and

3 Compiler.

Table 1–1. POS-PHY Level 2 and 3 Compiler Release Information

Version 9.1

Release Date November 2009

Ordering Codes:

■ POS-PHY level 2 PHY

■ POS-PHY level 2 link

■ POS-PHY level 3 PHY

■ POS-PHY level 3 link

Product IDs:

■ POS-PHY level 2 PHY

■ POS-PHY level 2 link

■ POS-PHY level 2 PHY

■ POS-PHY level 2 link

Vendor ID 6AF7

1. About This Compiler

Item Description

IP-POSPHY/P2

IP-POSPHY/L2

IP-POSPHY/P3

IP-POSPHY/L3

0058 0071

0070 0071

0051 0071

0050 0071

f For more information about this release, refer to the MegaCore IP Library Release Notes

and Errata.

Altera verifies that the current version of the Quartus previous version of each MegaCore

and Errata report any exceptions to this verification. Altera does not verify

compilation with MegaCore function versions older than one release."

Device Family Support

MegaCore functions provide either full or preliminary support for target Altera device families:

■ Full support means the MegaCore function meets all functional and timing

requirements for the device family and may be used in production designs

■ Preliminary support means the MegaCore function meets all functional

requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution.

Tab le 1– 2 shows the level of support offered by the POS-PHY Level 2 and 3 Compiler

to each Altera device family.

II software compiles the

function. The MegaCore IP Library Release Notes

Preliminary

1–2 Chapter 1: About This Compiler

Features

Table 1–2. Device Family Support

Device Family Support

™

Arria

GX Full

Arria II GX Preliminary

Cyclone

Full

Cyclone II Full

Cyclone III Full

HardCopy

II Full

HardCopy III Preliminary

HardCopy IV E Preliminary

Stratix

Full

Stratix II Full

Stratix II GX Full

Stratix III Full

Stratix IV Preliminary

Stratix GX Full

Other device families No support

Features

■ Conforms to POS-PHY level 2 and level 3 specifications

■ Link-layer or PHY-layer POS-PHY interfaces

■ Creates bridges between different POS-PHY interfaces

■ Support for traffic up to a rate of 3.2 gigabits per second (Gbps) (POS-PHY level 3)

or 832 megabits per second (Mbps) (POS-PHY level 2), such as SONET OC-48

■ Single-PHY (SPHY) or up to 8-channel multi-PHY (MPHY) operation with polled

and direct packet available options

■ Atlantic

™

interface that allows a consistent interface between all Altera cell and

packet MegaCore functions

■ Selectable POS-PHY interface bus widths (8/16/32 bit) and Atlantic interface bus

widths (8/16/32/64 bit)—allowing translation between different bus types

■ Parity generation/detection

■ Configurable first-in first-out (FIFO) options: selectable FIFO width, depth, and fill

thresholds.

■ Easy-to-use IP Toolbench interface

■ IP functional simulation models for use in Altera-supported VHDL and Verilog

HDL simulators

■ Support for OpenCore Plus evaluation

POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation

Preliminary

Chapter 1: About This Compiler 1–3

MegaCore

Function

MegaCore

Function

Atlantic

Interface

Atlantic

Interface

User

Logic

Atlantic

Interface

User

Logic

Atlantic

Interface

User

Logic

Link

Interface

User

Logic

Atlantic

Interface

PHY

Interface

User

Logic

PHY/Link

Interface

SPHYMPHY

SPHY SPHY

MegaCore

Function

General Description

The POS-PHY Level 2 and 3 Compiler generates MegaCore functions for use in linklayer or physical layer (PHY) devices that transfer data to and from packet over SONET/SDH (POS) devices using the standard POS-PHY bus.

The POS-PHY Level 2 and 3 Compiler comprises separately configurable modules, which can be easily combined via the IP Toolbench to generate a highly parameterized module, allowing POS-PHY compliant interfaces (and non-standard interfaces) to be included in custom designs.

The compiler supports POS-PHY level 3 operating at up to 3.2 Gbps, and level 2 operating at up to 832 Mbps.

The POS-PHY Level 2 and 3 Compiler is compliant with all applicable standards, including:

■ POS-PHY Level 3 Specification, Issue 4, June 2000

■ POS-PHY Level 2 Specification, Issue 5, December 1998

■ Optical Internet working Forum (OIF), System Packet Interface Level 3 (SPI-3)

■ Altera Corporation, Atlantic Interface Specification

This allows efficient translation between the different formats, including mapping between different bus speeds and bus widths, as well as customizable FIFO buffer parameters.

The compiler allows configurations such as PHY-PHY, link-link bridges, or packet multiplexing MegaCore functions, and SPHY and MPHY applications. Figure 1–1 on

page 1–3 shows the possible interfaces. Figure 1–2 on page 1–4 shows the possible

bridges.

Figure 1–1. Interfaces

Preliminary

1–4 Chapter 1: About This Compiler

General Description

Figure 1–2. Bridges

MegaCore

Level 2/3

Link

Interface

SPHY SPH

Level 2/3

PHY

Interface

Function

MegaCore

Function

Level 2/3

Link

Interface

Level 2/3

PHY

Interface

Atlantic Interface

f For more information on the Atlantic interface, refer to FS 13: Atlantic Interface.

SPHY

MPHY

Level 2/3

Link

Interface

MegaCore

Function

Level 2/3 PHY/Link Interface

MegaCore

Function

Level 2/3

PHY

Interface

Level 2/3 PHY/Link

Interface

Level 2/3 PHY/Link

Interface

Level 2/3 PHY/Link

Interface

SPH

SPHY

The Atlantic interface allows a consistent interface between all Altera cell and packet MegaCore functions. The Atlantic interface supports a point-to-point connection.

OpenCore Plus Evaluation

With Altera's free OpenCore Plus evaluation feature, you can perform the following actions:

■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

megafunction) within your system

■ Verify the functionality of your design, as well as evaluate its size and speed

quickly and easily

■ Generate time-limited device programming files for designs that include

megafunctions

■ Program a device and verify your design in hardware

POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation

Preliminary

Chapter 1: About This Compiler 1–5

Performance and Resource Utilization

You only need to purchase a license for the megafunction when you are completely satisfied with its functionality and performance, and want to take your design to production.

f For more information on OpenCore Plus hardware evaluation using the POS-PHY

Level 2 and 3 Compiler, see “OpenCore Plus Time-Out Behavior” on page 3–6 and AN

320: OpenCore Plus Evaluation of Megafunctions.

Performance and Resource Utilization

Tab le 1– 3 through 1–7 show typical expected performance for SPHY and 4-port POS-

PHY MegaCore functions. All results are push-button performance and use a FIFO buffer size of 512 bytes. These results were obtained using the Quartus version for the following devices:

■ Cyclone II (see tables for device details)

■ Cyclone III (EP3C5F256C6 for POS-PHY level 3)

■ Stratix III (EP3SL70F484C2 for POS-PHY level 2; EP3SL50F484C2 for POS-PHY

level 3)

II software

■ Stratix IV (EP4SGX70DF29C2X )

Table 1–3. Performance—POS-PHY Level 2 Link Layer—Cyclone II Device

Memory Blocks

MegaCore Function LEs

(MHz)M4K

MAX

Device: EP2C5F256C6

SPHY receive 416 2 176

SPHY transmit 407 2 149

Device: EP2C15AF484C6

MPHY 4-port receive 1,267 8 167

MPHY 4-port transmit 1,272 8 128

Table 1–4. Performance—POS-PHY Level 2 Link Layer—Stratix III Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

MAX

SPHY receive 177 348 2 344

SPHY transmit 210 326 2 310

MPHY 4-port receive 558 1,051 8 320

MPHY 4-port transmit 624 1,024 8 221

(MHz)M9K

Table 1–5. Performance—POS-PHY Level 2 PHY Layer—Cyclone II Device (Part 1 of 2)

Memory Blocks

MegaCore Function LEs

(MHz)M4K

MAX

Device: EP2C5F256C6

SPHY receive 354 2 174

Preliminary

1–6 Chapter 1: About This Compiler

Performance and Resource Utilization

Table 1–5. Performance—POS-PHY Level 2 PHY Layer—Cyclone II Device (Part 2 of 2)

Memory Blocks

MegaCore Function LEs

(MHz)M4K

MAX

SPHY transmit 285 2 159

Device: EP2C15AF484C6

MPHY 4-port receive 1,175 8 161

MPHY 4-port transmit 1,126 8 139

Table 1–6. Performance—POS-PHY Level 2 PHY Layer—Stratix III Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

MAX

SPHY receive 122 309 2 340

SPHY transmit 123 234 2 346

MPHY 4-port receive 487 995 8 318

MPHY 4-port transmit 529 918 8 293

Table 1–7. Performance—POS-PHY Level 3 Link Layer—Cyclone III Device

Memory Blocks

MegaCore Function LEs

(MHz)M9K

MAX

SPHY receive 379 2 165

SPHY transmit 377 2 139

MPHY 4-port receive 1,202 8 171

MPHY 4-port transmit 1,242 8 164

(MHz)M9K

Table 1–8. Performance—POS-PHY Level 3 Link Layer—Stratix III Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

(MHz)M9K

MAX

SPHY receive 149 330 2 234

SPHY transmit 164 313 2 205

MPHY 4-port receive 522 1,019 8 217

MPHY 4-port transmit 613 1,009 8 178

Table 1–9. Performance—POS-PHY Level 3 Link Layer—Stratix IV Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

(MHz)M9K

MAX

SPHY receive 149 330 2 231

SPHY transmit 164 313 2 180

MPHY 4-port receive 522 1,019 8 254

MPHY 4-port transmit 613 1,009 8 174

POS-PHY Level 2 and 3 Compiler User Guide © November 2009 Altera Corporation

Preliminary

Chapter 1: About This Compiler 1–7

Performance and Resource Utilization

Table 1–10. Performance—POS-PHY Level 3 PHY Layer—Cyclone III Device

Memory Blocks

MegaCore Function LEs

(MHz)M4K

MAX

SPHY receive 350 2 174

SPHY transmit 365 2 173

MPHY 4-port receive 1,175 8 169

MPHY 4-port transmit 1,218 8 143

Table 1–11. Performance—POS-PHY Level 3 PHY Layer—Stratix III Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

MAX

SPHY receive 121 307 2 270

SPHY transmit 160 294 2 287

MPHY 4-port receive 489 999 8 245

MPHY 4-port transmit 587 984 8 231

Table 1–12. Performance—POS-PHY Level 3 PHY Layer—Stratix IV Device

Memory Blocks

Logic

MegaCore Function ALUTs

Registers

MAX

SPHY receive 121 307 2 243

SPHY transmit 160 294 2 286

MPHY 4-port receive 489 999 8 222

MPHY 4-port transmit 587 984 8 260

(MHz)M9K

Preliminary

1–8 Chapter 1: About This Compiler

Performance and Resource Utilization

Preliminary

Design Flow

2. Getting Started

To evaluate the POS-PHY Level 2 and 3 Compiler using the OpenCore Plus feature include these steps in your design flow:

1. Obtain and install the POS-PHY Level 2 and 3 Compiler.

The POS-PHY Level 2 and 3 MegaCore function is part of the MegaCore IP Library, which is distributed with the Quartus from the Altera

website, www.altera.com.

f For system requirements and installation instructions, refer to Quartus II

Installation & Licensing for Windows and Linux Workstations.

Figure 2–1 on page 2–1 shows the directory structure after you install the POS-

PHY Level 2 and 3 Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\90; on Linux it is /opt/altera90.

II software and downloadable

Figure 2–1. Directory Structure

<path>

Installation directory.

Contains the Altera MegaCore IP Library and third-party IP cores.

altera

Contains the Altera MegaCore IP Library.

common

Contains shared components.

posphy_l2_l3

Contains the POS-PHY Level 2 and 3 Compiler files and documentation.

doc

Contains the documentation for the MegaCore function.

lib

Contains encrypted lower-level design files.

sim_lib

Contains the MegaCore function simulation models.

modelsim

Contains the ModelSim simulation models.

testbench

Contains the testbench.

2. Create a custom variation of a POS-PHY Level 2 or 3 MegaCore function using IP Toolbench.

1 IP Toolbench is a toolbar from which you can quickly and easily view

documentation, specify parameters, and generate all of the files necessary for integrating the parameterized MegaCore function into your design.

Preliminary

2–2 Chapter 2: Getting Started

POS-PHY Level 2 & 3 Walkthrough

3. Implement the rest of your design using the design entry method of your choice.

4. Use the IP Toolbench-generated IP functional simulation model to verify the operation of your design.

f For more information on IP functional simulation models, refer to the Simulating

Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.

5. Use the Quartus II software to compile your design.

1 You can also generate an OpenCore Plus time-limited programming file,

which you can use to verify the operation of your design in hardware.

6. Purchase a license for the POS-PHY Level 2 and 3 Compiler.

After you have purchased a license for the POS-PHY Level 2 and 3 compiler, the design flow requires these additional steps:

1. Set up licensing.

2. Generate a programming file for the Altera

device(s) on your board.

3. Program the Altera device(s) with the completed design.

4. Perform design verification.

POS-PHY Level 2 & 3 Walkthrough

This walkthrough explains how to create a POS-PHY Level 2 or 3 MegaCore function using the Altera POS-PHY Level 2 and 3 Compiler IP Toolbench and the Quartus II software. When you finish generating a POS-PHY Level 2 or 3 MegaCore function, you can incorporate it into your overall project.

1 IP Toolbench only allows you to select legal combinations of parameters, and warns

you of any invalid configurations.

This walkthrough involves the following steps:

■ Create a New Quartus II Project

■ Launch IP Toolbench

■ Step 1: Parameterize

■ Step 2: Set Up Simulation

■ Step 3: Generate

Create a New Quartus II Project

You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project follow these steps:

Preliminary

Chapter 2: Getting Started 2–3

POS-PHY Level 2 & 3 Walkthrough

1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can also use the Quartus II Web Edition software.

2. Choose New Project Wizard (File menu).

3. Click Next in the New Project Wizard Introduction page (the introduction does not display if you turned it off previously).

4. In the New Project Wizard: Directory, Name, Top-Level Entity page, enter the following information:

a. Specify the working directory for your project. For example, this walkthrough

uses the c:\altera\projects\pl2pl3_project directory.

1 The Quartus II software automatically specifies a top-level design entity

that has the same name as the project. This walkthrough assumes that the names are the same.

b. Specify the name of the project. This walkthrough uses example for the project

name.

5. Click Next to close this page and display the New Project Wizard: Add Files page.

6. Click Next to close this page and display the New Project Wizard: Family &

7. On the New Project Wizard: Family & Device Settings page, choose the target

8. The remaining pages in the New Project Wizard are optional. Click Finish to

You have finished creating your new Quartus II project.

Launch IP Toolbench

To launch IP Toolbench in the Quartus II software, follow these steps:

1. Start the MegaWizard

1 When you specify a directory that does not already exist, a message asks if

the specified directory should be created. Click Yes to create the directory.

Device Settings page.

device family in the Family list.

complete the Quartus II project.

Plug-In Manager by choosing MegaWizard Plug-In

Manager (Tools menu). The MegaWizard Plug-In Manager dialog box displays.

1 Refer to the Quartus II Help for more information on how to use the

MegaWizard Plug-In Manager.

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2–4 Chapter 2: Getting Started

POS-PHY Level 2 & 3 Walkthrough

Figure 2–2. MegaWizard Plug-In Manager

2. Specify that you want to create a new custom megafunction variation and click Next.

3. Expand the Communications > POS-PHY directory then click POS-PHY Level 2 & 3 Compiler.

4. Select the output file type for your design; the wizard supports VHDL, and Ver il og HD L.

5. The MegaWizard Plug-In Manager shows the project path that you specified in the New Project Wizard. Append a variation name for the MegaCore function output files <project path>\<variation name>. Figure 2–3 shows the wizard after you have made these settings.

Figure 2–3. Select the Megafunction

6. Click Next to launch IP Toolbench.

Preliminary

Chapter 2: Getting Started 2–5

POS-PHY Level 2 & 3 Walkthrough

Step 1: Parameterize

To parameterize your MegaCore function, follow these steps:

1. Click Parameterize in the IP Toolbench (see Figure 2–4 on page 2–5).

Figure 2–4. IP Toolbench—Parameterize

2. Select your architecture options where the POS-PHY ‘A’ interface is a data source or sink (see Figure 2–5).

1 Source indicates that interface ‘A’ is an output from the MegaCore function.

Sink indicates that interface ‘A’ is an input to the MegaCore function.

Figure 2–5. Select the ‘A’ Interface Direction

3. In a MPHY architecture there is a ‘B’ interface for each supported channel (maximum eight). Select the number of supported channels that you require.

1 To create a design that supports source and sink data directions, you must

run IP Toolbench twice, to create the source and sink designs separately.

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POS-PHY Level 2 & 3 Walkthrough

4. Click Next.

5. Select your interface types (see Figure 2–6).

a. Select interface ‘A’ using the radio buttons.

b. Choose ‘B’ interfaces using the drop-down menus.

Figure 2–6. Select the Interface Types

6. Click Next.

7. Choose the interface settings (see Figure 2–7 on page 2–6).

1 POS-PHY Level 3 Specification, Issue 4, June 2000 supports an 8- or 32-bit

interface. Additionally this MegaCore function supports a 16-bit interface for POS-PHY level 3.

1 POS-PHY Level 2 Specification, Issue 5, December 1998 supports a 16 bit

interface. Additionally, this MegaCore function supports 8- and 32-bit interfaces for POS-PHY level 2.

1 The Atlantic interface can be 8-, 16-, 32-, or 64-bits wide.

Figure 2–7. Choose the Interface Settings

Preliminary

Chapter 2: Getting Started 2–7

POS-PHY Level 2 & 3 Walkthrough

8. Click Next.

9. Select the parity settings of the interfaces (see Figure 2–8).

1 If parity is used the polarity setting must be the same for all interfaces.

Figure 2–8. Select the Parity Settings

f For more information on the parity settings, see “Parity Settings” on page 3–8.

10. Click Next.

11. Choose the first-in first-out (FIFO) buffer settings (see Figure 2–9).

Figure 2–9. Choose the FIFO Buffer Settings

If you select the Fixed Burst option, you must also set the burst size by entering a value in the Burst field. Data is then sent in bursts of the specified burst size only, or in bursts containing an end of packet.

Preliminary

+ 43 hidden pages

Altera POS-PHY Level 2 and 3 Compiler User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Release Information

1. About This Compiler

Device Family Support

Features

General Description

Atlantic Interface

OpenCore Plus Evaluation

Performance and Resource Utilization

Design Flow

2. Getting Started

POS-PHY Level 2 & 3 Walkthrough

Create a New Quartus II Project

Launch IP Toolbench

Step 1: Parameterize