Altera PHYLite User Manual

2015.01.16

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Altera PHYLite for Parallel Interfaces IP Core User

Guide

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The Altera PHYLite for Parallel Interfaces IP core controls the strobe-based capture I/O elements in Arria® 10 devices. Use each instance of the IP core to support an interface with up to 18 individual data/ strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic.

Device Family Support

The Altera PHYLite for Parallel Interfaces IP core supports Arria® 10 devices only. For Arria V, Cyclone® V, and Stratix® V devices, use the ALTDQ_DQS2 IP core instead.

Related Information

• ALTDQ_DQS2 IP Core User Guide

For more information about the ALTDQ_DQS2 IP core

Features

The Altera PHYLite for Parallel Interfaces IP core:

• Supports input, output, and bidirectional data channels

• Supports DQS-group based data capture, with up to 48 I/Os (including strobes) per group and DQS gating/ungating circuitry for strobe-based interfaces

• Supports output delays via interpolator

• Supports dynamic on-chip termination (OCT) control

• Supports quarter-rate to half-rate and half-rate to full-rate conversions. Also supports input, output, and read/DQS/OCT enable paths

• Supports single data rate (SDR) and double data rate (DDR) at the I/Os

• Supports PHY clock tree

• Supports dynamically reconfigurable delay chains using Avalon interface

• Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains

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Note:

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

The non-PVT compensated component of the input delay is not set in the Quartus II software version 14.1 and will only be set in a future release of the Quartus II software.

ISO 9001:2008 Registered

I/O Bank

I/O AUX

Overview

The Arria 10 I/O subsystem is located in the I/O columns. Each column consists of up to 13 I/O banks and one I/O aux.

Figure 1: I/O Column for Arria 10 Devices

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Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane.

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Transceiver Block

HSSI Column

I/O Column

Tile Control

I/O Column

Individual I/O Banks

LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair

SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA

I/O Lane

LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair

SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA

I/O Lane

I/O Center

I/O PLL

Hard Memory Controller

and

PHY Sequencer

I/O DLL I/O CLK

OCT VR

LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair

SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA

I/O Lane

LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair LVDS I/O Buffer Pair

SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA SERDES & DPA

I/O Lane

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Figure 2: 48-I/O Banks in Arria 10 Devices

This figure shows a detailed view of the I/O bank in Arria 10 devices.

Clocks

Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank.

Related Information

• Placement Restrictions on page 15

For more information about placement restrictions

• Functional Description—Arria 10 EMIF

For more information about the architecture

Clocks

The Altera PHYLite for Parallel Interfaces IP core uses four clock domains for the output and input paths. Refer to Figure 4 for the clock domain boundaries.

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VCO Clock Frequency : External Memory Clock Frequency : Core/PHY Clock Frequency

VCO Frequency Multiplier User Specified Core Clock Rate

Clock Frequency Relationships

Clock Domain Description

Core clock This clock is generated internally by the IP core and output to the core to be used for

all transfers between the FPGA core and the IP core.

PHY Clock This clock is used internally by the IP core for PHY circuitry running at the same

frequency as the core clock. The PHY circuitry ensures that this clock is kept in phase with the core clock for core-to-periphery and periphery-to-core transfers.

VCO clock This clock is generated internally by the PLL. It is used by both the input and output

paths to generate PVT compensated delays.

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External Memory Clock

This is the user specified frequency at which the FPGA I/Os connected to the external device operate.

Clock Frequency Relationships

Figure 3: Clock Frequency Relationships

VCO Frequency Multiplication Factor

The relationship between the VCO clock frequency and the user specified external memory clock frequency is calculated during generation of the IP core based on the this table.

Table 1: VCO Frequency Multiplication Factor

VCO

Frequency

Multiplication

Factor

Speed Grade -1 Speed Grade -2 Speed Grade -3

Minimum

Frequency

Maximum

Frequency

Minimum

Frequency

Maximum

Frequency

Minimum

Frequency

1 600 800 600 800 550 800 2 300 600 300 600 275 550 4 150 300 150 300 137.5 275 8 100 150 100 150 100 137.5

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PLL

I/O Lane

Tile Control

I/O Lane

VCO/Interpolator

phy_clk

phy_clk_phs

core_clk_out

data_in/out/io

Data to/from Core

Group

ref_clk

Reference Clock Core Clock

PHY Clock ExternalClock

Legend

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Interface

Figure 4: Top-Level Interface

Interface

This figure shows the top-level diagram of the Altera PHYLite for Parallel Interfaces IP core interface.

The Altera PHYLite for Parallel Interfaces IP core consists of the following interfaces:

• Clocks and Reset

• Core Data and Control (broken down into input and output paths)

• I/O (broken down into input and output paths)

• Avalon Configuration Bus

Related Information

• Output Path on page 5

For more information about the output path

• Input Path on page 8

For more information about the input path

• Signals on page 37

For more information about core data, control, and I/O interfaces signals

Output Path

The output path consists of a FIFO and an interpolator.

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Write FIFO

data_io data_out

oe_out

oct_out

Interpolator

interpolator_clk

data_from_core

oe_from_core

phy_clk

VCO clock

output_strobe_in

output_strobe_en

strobe_out strobe_io

Output Path

Figure 5: Output Path

This figure shows the output path for the Altera PHYLite for Parallel Interfaces IP core.

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Table 2: Blocks in Output Path

This table lists the blocks in the output path.

FIFO Serializes the output data from the core with a serialization factor of up to 8

Interpolator Works with the FIFO block to generate the desired output delay. You can

Block Description

(in DDR quarter-rate).

dynamically configure the delay through the Avalon interface. For more information, refer to Dynamic Reconfiguration on page 20.

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Figure 6: Output Path - Write Latency 0

Figure 7: Output Path - Write Latency 3

These figures show the waveform diagrams for the output path.

Output Path Data Alignment

Related Information

Output Path Signals on page 38

For more information about output path signals

Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices, which are broken down into the individual pins in the group. The first time slice is on the LSBs of the busses, which matches the Altera PHY interface (AFI) bus ordering of the Arria 10 External Memory Interfaces IP core.

{...,time2,time1,time0}

Where time0 = {...,pin1,pin0}

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Read FIFO DDIO

Delay Chain

(PVT)

data_to_core

data_in

phy_clk

strobe_in

dqs

Delay Chain

(PVT)

dqs_clean

pstamble_reg

FIFO

Interpolator

interpolator_clk

dqs_enable

phy_clk_phs

VFIFO

read_enable

dqs_enable

rdata_en

phy_clk

rdata_valid

data_io

strobe_io strobe_in_n

5 5

Input Path

Figure 8: Example Output for Quarter Rate DDR

Related Information

• External Memory Interface Handbook

For more information about the AFI 3.0 specification

Input Path

Figure 9: Input Path

This figure shows the input path of the IP core.

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The input path of the IP core consists of a data path, a strobe path, and read enable path.

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Table 3: Blocks in Data, Strobe, and Read Enable Paths

This table lists the information about these paths.

Path Description

Data Path Consists of a PVT compensated delay chain, a DDIO and a read FIFO.

• PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated delay chain over Avalon-MM interface. For more information, refer to Dynamic Reconfiguration.

• DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zerocycle transfer.

The IP core supports SDR input by dropping every other bit of data going to the core.

Strobe Path Consists of pstamble_reg (a gating component) and a PVT compensated delay chain.

• pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are used.

• PVT compensated delay chain—Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs).

Input Path

Read Enable Path Consists of VFIFO, FIFO, and an interpolator.

• VFIFO—takes the rdata_en signal from the core and delays it separately for two outputs, one for the read enable on the read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. Individual control is not necessary, but if you are modifying these delays you can do so individually using dynamic reconfiguration.

• FIFO and interpolator—used for the strobe enable delay, the FIFO and interpo‐ lator are identical to the FIFO and interpolator circuitry in the output path. The FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = 0). During dynamic reconfiguration, the FIFO and interpolator can be used for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read latency parameter for the group.

Table 4: Read Operation Sequence

A read operation is performed as listed in this table.

Legend in Figure 9 Operation

1 The core asserts the read_en signal (and the external device is issued a read

command)

2 The strobe enable is delayed through the two FIFOs by the programmed read latency

(which should match the latency of the external device)

3 The strobe signal is ungated by the strobe enable signal as valid data enters the read

path

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Input Path Data Alignment

Legend in Figure 9 Operation

4 The strobe is optionally delayed to create a phase offset between the strobe and the

input data (for example, 90° phase shift for DDR center-alignment) 5 The data is clocked into the DDIO and read FIFO by the strobe 6 The VFIFO asserts the read enable on the read FIFO and the rdata_valid signal to

the core simultaneously. This outputs the captured data and the associated valid signal

to the core.

Figure 10: Input Path Waveform

This figure shows a waveform diagram of the input path.

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Related Information

Input Path Signals on page 40

For more information about input path signals

Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.

The rdata_valid delay is always set by the IP core to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Unaligned reads will result in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs.

Figure 11: Example Input (Quarter Rate DDR) - Aligned

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Figure 12: Example Input (Quarter Rate DDR) - Unaligned

I/O Standards

The Altera PHYLite for Parallel Interfaces IP core allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

When you select an I/O standard in the I/O standard parameter, the reference clock assigns the I/O standard as a single-ended input. For a differential reference clock, override the single-ended Quartus II IP File (.qip) setting in the .qsf.

If you want to assign I/O standards manually at the system level (in the .qsf), then set the I/O standard to

none, which will not output any I/O standard related .qip assignments from the IP generation.

Table 5: I/O Standards

I/O Standard Valid Input

Terminations (Ω)

Valid Output

(1)

Terminations

(Ω)

RZQ

(Ω)

(1)

Differential/Complementary I/O

SSTL-12 60, 120 40, 60 240 Yes SSTL-125 20, 30, 40, 60, 120 34, 40 240 Yes SSTL-135 20, 30, 40, 60, 120 34, 40 240 Yes SSTL-15 20, 30, 40, 60, 120 34, 40 240 Yes SSTL-15 Class I 0, 50 0, 50 100 Yes SSTL-15 Class II 0, 50 0, 25 100 Yes SSTL-18 Class I 0, 50 0, 50 100 Yes SSTL-18 Class II 0, 50 0, 25 100 Yes

1.2-V HSTL Class I 0, 50 0, 50 100 Yes

1.2-V HSTL Class II 0, 50 0, 25 100 Yes

1.5-V HSTL Class I 0, 50 0, 50 100 Yes

1.5-V HSTL Class II 0, 50 0, 25 100 Yes

Support

1.8-V HSTL Class I 0, 50 0, 50 100 Yes

1.8-V HSTL Class II 0, 50 0, 25 100 Yes

(1)

0 is equivalent to none.

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Input Buffer Reference Voltage (VREF)

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I/O Standard Valid Input

Terminations (Ω)

1.2-V POD 34, 40, 48, 60, 80,

Valid Output

(1)

Terminations

(Ω)

(1)

RZQ

(Ω)

Differential/Complementary I/O

34, 40, 48, 60 240 Yes

120, 240

1.2-V — — — No

1.5-V — — — No

1.8-V — — — No

Input Buffer Reference Voltage (VREF)

The 1.2-V POD I/O standard allows a configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings

(including GPIOs).

Table 6: VREF_MODE Description

Support

VREF Mode Description

EXTERNAL Use the external VREF. This is the default. CALIBRATED Use internal VREF generated using VREF codes from the Avalon reconfiguration bus. VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCN VCCIO_50 Use internal VREF generated using static VREF code. VREF is 50% of VCCN VCCIO_55 Use internal VREF generated using static VREF code. VREF is 55% of VCCN VCCIO_65 Use internal VREF generated using static VREF code. VREF is 65% of VCCN VCCIO_70 Use internal VREF generated using static VREF code. VREF is 70% of VCCN VCCIO_75 Use internal VREF generated using static VREF code. VREF is 75% of VCCN

(1)

0 is equivalent to none.

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Input Buffer

Vref

VCCN

Internal VREF

6 bits binary weighted resistors dividor

6 bits Static VREF Code

6 bits calibrated VREF code from Avalon bus

VREF Calibration Block

VCCN

External VREF

Resistor

Ladder

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Figure 13: VREF

Calibrated VREF Settings

Table 7: Calibrated VREF Settings

This table lists the calibrated VREF settings that you can set over the Avalon calibration bus.

avl_writedata[5:0] % of VCCN

000000 60.00% 000001 60.64% 000010 61.28% 000011 61.92% 000100 62.56%

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Calibrated VREF Settings

avl_writedata[5:0] % of VCCN

000101 63.20% 000110 63.84% 000111 64.48% 001000 65.12% 001001 65.76% 001010 66.40% 001011 67.04% 001100 67.68% 001101 68.32% 001110 68.96% 001111 69.60% 010000 70.24% 010001 70.88%

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010010 71.52% 010011 72.16% 010100 72.80% 010101 73.44% 010110 74.08% 010111 74.72% 011000 75.36% 011001 76.00% 011010 76.64% 011011 77.28% 011100 77.92% 011101 78.56% 011110 79.20% 011111 79.84% 100000 80.48%

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100001 81.12% 100010 81.76% 100011 82.40%

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Placement Restrictions

avl_writedata[5:0] % of VCCN

100100 83.04% 100101 83.68% 100110 84.32% 100111 84.96% 101000 85.60% 101001 86.24% 101010 86.88% 101011 87.52% 101100 88.16% 101101 88.80% 101110 89.44% 101111 90.08% 110000 90.72%

110001 91.36% 110010 92.00%

110011 -> 111111 Reserved

Related Information

Dynamic Reconfiguration on page 16

For more information on the Avalon bus usage

Placement Restrictions

Group Pin Placement

Place each group in the interface into a set of lanes in the same bank, the number of which depends on the number of pins used by the group. All groups in an interface must be placed across a contiguous set of banks.

Table 8: Group Pin Placement

Number of Pins in Group Valid DQS Group in a Bank Valid Indices in a Bank

1-12 DQS for X8/X9 {0-11}/{12-23}/{24-35}/{36-47} 13-24 DQS for X16/X18 {0-23}/{24-47} 24-48 DQS for X32/X36 {0-47}

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Reference Clock

Related Information

• Device Pin-Out File

For specific DQS group numbers refer to the specific device Pin-Out file

Reference Clock

The reference clock must be placed on a clock input in one of the banks used by the interface. If the reference clock is used for multiple interfaces (consisting of a combination of EMIF and Altera PHYLite for Parallel Interfaces IPs), it can be placed in any bank used by any of the interfaces, but the banks for all interfaces must be contiguous.

Constraining Multiple Altera PHYLite for Parallel Interfaces to One I/O Bank

To constrain groups from separate Altera PHYLite for Parallel Interfaces IP core instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings.

Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the Arria 10 External Memory Interfaces and Altera PHYLite for Parallel Interfaces IP cores in the same I/O column must share the

reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.

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Related Information

Daisy Chain on page 20

Describes the daisy chain connectivity

Timing

The Quartus II software version 14.1 generates the required timing constraints to analyze the timing of the Altera PHYLite for Parallel Interfaces IP core on the Arria 10 device.

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Timing Components

Table 9: Timing Components

Timing Components

Circuit Category Timing

Source Synchronous

Read Path Memory and optionally calibrated

Source Synchronous

(2)

Write Path FPGA DQ/ and optionally calibrated

(2)

Paths

Source Destination Description

Device

DQ Capture

Source synchronous timing paths— paths where clock and data signals are passed from the transmitting devices to the receiving devices.

Optionally calibrated paths—paths

DQS

Memory

Device

with delay elements that are dynamically reconfigurable to achieve timing closure, especially at higher frequency, and to maximize the timing margins. You can calibrate these paths by implementing an algorithm and turning on the optional dynamic reconfiguration feature. An example of the calibrated path is the FPGA to memory device write path, in which you can dynamically reconfigure the delay elements to, for instance, compensate the skew due to process voltage temperature variation.

Internal FPGA Core to

PHYLite

Core

Registers

Path

Internal FPGA PHYLite to

Read FIFO Core

Core

Timing Constraints and Files

To enable you to successfully timing constrain the Altera PHYLite for Parallel Interfaces IP core, the IP core generates a set of timing files. You can locate these timing files in the <variation_name> directory:

• <variation_name> .sdc

• <variation_name> _ip_parameters.tcl

• <variation_name> _pin_map.tcl

(2)

Can be optionally calibrated by using dynamic reconfiguration.

Write FIFO

The internal FPGA paths are paths in the FPGA fabric. The TimeQuest timing analyzer reports the corresponding timing margins.

Registers

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<variation_name>.sdc

You can find the location of the <variation_name>.sdc file in the .qip, which is generated during the IP generation. The <variation_name>.sdc allows the Fitter to optimize timing margins with timing driven compilation and allows the TimeQuest timing analyzer to analyze the timing of your design.

The IP core uses <variation_name>.sdc for the following operations:

• Creating clocks on PLL inputs

• Creating generated clocks

• Calling derive_clock_uncertainty

• Creating set_output_delay and set_input_delay constraints to analyze the timing of the read and write paths

<variation_name>_ip_parameters.tcl

The <variation_name>_ip_parameters.tcl file lists the Altera PHYLite for Parallel Interfaces IP core parameters and is read by the <variation_name>.sdc.

<variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl is a TCL library of functions and procedures that <variation_name>.sdc uses.

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Timing Analysis

Table 10: Timing Analysis

This table lists the timing analysis performed in the I/O and FPGA for the Altera PHYLite for Parallel Interfaces IP core.

Location Description

I/O The Altera PHYLite for Parallel Interfaces IP core generation creates the appropriate

generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format:

• Clock name for read strobe—<pin_name>_IN.

• Clock name for the write path—<pin_name> for positive strobe.

• Clock name for the write path—<pin_name>_neg for negative strobe. The set_false_path, set_input_delay and set_output_delay constraints are also

generated to ensure proper timing analysis of the Altera PHYLite for Parallel Interfaces IP core.

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Location Description

FPGA The Altera PHYLite for Parallel Interfaces IP core generation creates the clock settings for the

user core clock and the periphery clock in the following formats:

• user core clock—<variation_name>_usr_clk

• periphery clock— <variation_name>_phy_clk* The user core clock is for user core logic and the periphery clock is the clock for the PHYLite

periphery hardware. With these clock settings, the TimeQuest Timing Analyzer analyzes the timing of the Altera PHYLite for Parallel Interfaces IP core interface transfer and within core transfer correctly.

Timing Closure Guidelines

Timing Closure: Dynamic Reconfiguration

You can dynamically reconfigure the delay elements in the I/O to optimize process, voltage, temperature variations by implementing a calibration algorithm that modifies the input and output delays (refer to

Dynamic Reconfiguration on page 20).

Timing Closure Guidelines

The SDC cuts the I/O transfer paths and you must verify the reconfiguration algorithm to ensure that your I/O transfers are working. The Quartus II software issues the following critical warning:

Dynamic Reconfiguration is ON but user has not set var(dynamic_reconfiguration_algorithm_verified) to 1. Please set to 1 after calibration algorithm is extensively verified. I/O timing analysis may not represent the system.

After verifying the algorithm, you can disable the critical warning by editing the .sdc file and set the following variable to 1:

var(dynamic_reconfiguration_algorithm_verified)

Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, modify the timing settings of the group to match the system. Convert input strobe phase shift to nanosecond and subtract it from Input Strobe Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters.

If the input data is center-aligned with the input strobe, subtract the 90° phase shift from the Input Strobe Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters in the

<variation_name>.sdc. For example, if the memory speed is 800 MHz and the value of the Input Strobe Setup Delay Constrain parameter is 0.1, change the value to 0.1-1.25*(90/360) = -0.2125.

Note:

Ensure that you make the changes in the Input Strobe Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters.

I/O Timing Violation

At high frequency configuration, it is difficult to achieve timing closure at I/O. Consider using the Arria 10 External Memory Interface IP core or the dynamic reconfiguration feature to calibrate the I/O path.

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+ 42 hidden pages

Altera PHYLite User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Device Family Support

Features

Overview

Clocks

Clock Frequency Relationships

VCO Frequency Multiplication Factor

Interface

Output Path

Output Path Data Alignment

Input Path

Input Path Data Alignment

I/O Standards

Input Buffer Reference Voltage (VREF)

Calibrated VREF Settings

Placement Restrictions

Group Pin Placement

Reference Clock

Constraining Multiple Altera PHYLite for Parallel Interfaces to One I/O Bank

Dynamic Reconfiguration

Timing

Timing Components

Timing Constraints and Files

<variation_name>.sdc

<variation_name>_ip_parameters.tcl

<variation_name>_pin_map.tcl

Timing Analysis

Timing Closure Guidelines

Timing Closure: Dynamic Reconfiguration

Timing Closure: Non Edge-Aligned Input Data

I/O Timing Violation