Altera Phase-Locked Loop Reconfiguration IP Core User Manual

Phase-Locked Loop Reconfiguration

(ALTPLL_RECONFIG) Megafunction

UG-032405-6.0 User Guide

Features

This user guide describes the features and behavior of the ALTPLL_RECONFIG
megafunction that you can configure through the parameter editor in the Quartus

®

software.

f This user guide assumes that you are familiar with megafunctions and how to create

them. If you are unfamiliar with Altera megafunctions or the parameter editor, refer
to the Introduction to Megafunctions User Guide.

Phase-locked loops (PLLs) use divide counters and voltage-controlled oscillator
(VCO) phase taps to perform frequency synthesis and phase shifts. In enhanced and
fast PLLs, you can reconfigure the counter settings as well as phase shift the PLL
output clock in real time. You can also change the charge-pump and loop-filter
components, which dynamically affect the PLL bandwidth. The ALTPLL_RECONFIG
megafunction implements reconfiguration logic to facilitate dynamic real-time
reconfiguration of PLLs in Altera devices. You can use the megafunction to update the
output clock frequency, PLL bandwidth, and phase shifts in real time, without
reconfiguring the entire FPGA.

The ALTPLL_RECONFIG megafunction offers the following additional features to the
ALTPLL megafunction:

■ Reconfiguration of pre-scale counter (N) parameters.

II

101 Innovation Drive
San Jose, CA 95134

www.altera.com

■ Reconfiguration of feedback counter (M) parameters.

■ Reconfiguration of post-scale output counter (C) parameters.

■ Reconfiguration of delay element or phase shift of each counter. For Stratix

Stratix IV, Cyclone

®

Arria

■ Dynamic adjustment of the charge-pump current and loop-filter components to

II GX devices, use the ALTPLL megafunction to access this feature.

®

III, Cyclone IV, HardCopy®III, HardCopy IV, and

®

facilitate dynamic reconfiguration of the PLL bandwidth. This feature is available
only in Arria GX, HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV
devices.

■ Reconfiguration from multiple configuration files using external read-only

memory (ROM) in user mode. This feature is available only in Stratix III, Stratix IV,
Cyclone III, Cyclone IV, and Arria II GX devices. The ALTPLL_RECONFIG
supports reconfiguration from Memory Initialization File (.mif) and Hexadecimal
File (.hex).

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their

respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.

9001:2008

Registered

III,

ISO

February 2012 Altera Corporation

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Page 2 Common Applications

f For more details about these features, refer to the Clock Networks and PLLs chapter of

the respective device handbook.

Common Applications

Use the ALTPLL_RECONFIG megafunction in designs that must support dynamic
changes in the frequency and phase shift of clocks and other frequency signals. The
megafunction is also useful in prototyping environments because it allows you to
sweep PLL output frequencies and dynamically adjust the output clock phase. For
example, a system generating test patterns is required to generate and transmit
patterns at 50 or 100 MHz, depending on the device under test. Reconfiguring the PLL
components in real-time allows you to switch between two such output frequencies
within a few microseconds. You can also adjust the clock-to-output (tCO) delays in
real-time by changing the output clock phase shift. This approach eliminates the need
to regenerate a configuration file with the new PLL settings.

Reconfigurable PLLs are very useful in DDR 2 and DDR 3 interfaces to implement the
dynamic data path (via the ALTMEMPHY megafunction). The PLL is needed to drive
the DLL used in the dynamic external memory interface operation. This operation
requires dynamic phase-shifting.

f For more information about dynamic phase-shifting in DDR 2 and DDR 3 interfaces,

refer to the ALTMEMPHY Megafunction User Guide.

In addition, you can dynamically configure Stratix III, Stratix IV, Cyclone III,
Cyclone IV, and Arria II GX PLLs by using multiple configuration files stored on the
external ROM.

Device Family Support

The megafunction supports the Stratix series (excluding Stratix V), HardCopy series,
Arria GX series, and Cyclone series devices.

Resource Utilization and Performance

For details about the resource usage and performance of the ALTPLL_RECONFIG
megafunction in various devices, refer to the compilation reports in the Quartus II
software.

To view the compilation reports for the ALTPLL_RECONFIG megafunction in the
Quartus II software, follow these steps:

1. On the Processing menu, click Start Compilation to run a full compilation.

2. After compiling the design, on the Processing menu, click Compilation Report.

3. In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.

4. Under Fitter, expand Resource section, and select Resource Usage Summary to
view the resource usage information.

5. Under Fitter, expand Resource section, and select Resource Utilization by Entity
to view the resource utilization information.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Parameter Settings Page 3

Parameter Settings

Altera recommends that you configure the megafunction using the MegaWizard™
Plug-In Manager. This section describes the parameters in the ALTPLL_RECONFIG
parameter editor.

Expert users may choose to instantiate and configure the megafunction using the clear
box generator.

Tab le 1 lists the parameter settings for the ALTPLL_RECONFIG megafunction.

Table 1. ALTPLL_RECONFIG Parameter Settings

Page Options Description

Currently Selected
Device Family

Which scan chain
type will you be
using?

Parameter
Settings

Do you want to
specify the initial
value of the scan
chain?

Add ports to write
to the scan chain
from external
ROM during run
time

Specifies the chosen device family.

Scan chain is serial shift register chain that is used to store settings. It acts like a
cache. When you assert the reconfig signal, the PLL is reconfigured with the values
in the cache. The type of scan chain must follow the type of PLL to be reconfigured.

For Arria GX, Stratix II, Stratix II GX, and HardCopy II devices—Specifies the scan
chain type as either Enhanced or Fast.

For Stratix and Stratix GX devices—Specifies the scan chain type as either Long
chain or Short chain.

For Stratix III, Stratix IV, HardCopy III, and HardCopy IV devices—Specifies the
scan chain type as either Top/Bottom or Left/Right. For Cyclone III, Cyclone IV, and
Arria II GX devices—The scan chain type has a default value of Left/Right.

Specifies the initial value of the scan chain. Select No, leave it blank to not specify
a file or select Yes, use this file for the content data to browse for a .hex or .mif
file.

For Arria GX, Arria II GX, Stratix, Stratix GX, Stratix II, Stratix II GX,Stratix III,
Stratix IV, HardCopy II, HardCopy III, and HardCopy IV devices—You can also
choose to initialize from ROM by turning on Do not use pre-initialized RAM -
initialize from ROM instead.

For Cyclone III and Cyclone IV devices—The option to initialize from a ROM is not
available. However, you can choose to add ports to write to the scan chain from an
external ROM during runtime by turning on Add ports to write to the scan chain
from external ROM during run time.

This option is only available for Stratix III, Stratix IV, Cyclone III, Cyclone IV,
HardCopy III, HardCopy IV, and Arria II GX devices. This option takes advantage of
cycling multiple configuration files, which are stored in external ROMs during user
mode. This capability is demonstrated in the functional description section,

“Functional Description—Implementing Multiple Reconfiguration Using an
External ROM” on page 6.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 4 Parameter Settings

Table 1. ALTPLL_RECONFIG Parameter Settings

Page Options Description

Specifies the libraries needed for functional simulation.

EDA

Generate netlist

Specifies whether to turn on the option to generate synthesis area and timing
estimation netlist.

Specifies the types of files to be generated. A gray checkmark indicates a file that is
automatically generated; a red checkmark indicates an optional file.

Choose from the following types of files:

■ AHDL Include file (<function name>.inc)

■ VHDL component declaration file (<function name>.cmp)

Summary

■ Quartus II symbol file (<function name>.bsf)

■ Instantiation template file (<function name>_inst.v or <function

name>_inst.vhd

■ Verilog HDL block box file (<function name>_bb.v)

If Generate netlist option is turned on, the file for that netlist is also available
(<function name>_syn.v).

You c a n op e n a .mif in a text editor to make use of the comments embedded within
the file. These comments show you the scan chain values and positions based on your
design parameterization (see Figure 1). If you open a .mif in the Quartus II software,
you can regenerate the .mif in the ALTPLL parameter editor to restore the comments.

Figure 1. MIF file

f For more information about implementing PLL reconfiguration in the supported

Stratix series, refer to AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX

Devices, AN 367: Implementing PLL Reconfiguration in Stratix II Devices and AN 454:
Implementing PLL Reconfiguration in Stratix III Devices.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Checking Design Violations With the Design Assistant Page 5

Checking Design Violations With the Design Assistant

The Design Assistant is a design rule checking tool that allows you to check for design
issues early in the design flow. When you run the Design Assistant in the Quartus II
software for the ALTPLL_RECONFIG megafunction, you might receive the warning
message shown in Figure 2.

Figure 2. Warning Message in Design Assistant

This message appears because there is a combinational logic in the megafunction that
connects the synchronous signal to the asynchronous external reset signal. To fix the
issue, you must synchronize the external reset signal outside the megafunction.

To synchronize the external reset signal, use the sample Verilog HDL code shown in

Example 1. In the example, the input of

reset pin, and the output of

sync_reset_dffe2

sync_reset_dffe1

is connected to the

is connected to the external

reset

input port of

the ALTPLL_RECONFIG megafunction.

Example 1. Code to Synchronize External Reset Signal

module synch_reg (reset, reconfig_clk, sync_reset_dffe2);

input reset, reconfig_clk;
output sync_reset_dffe2;
reg sync_reset_dffe1, sync_reset_dffe2;
always @(posedge reconfig_clk)
begin

sync_reset_dffe1 = reset;
end
always @(posedge reconfig_clk)
begin

sync_reset_dffe2 = sync_reset_dffe1;

end

endmodule

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 6 Simulation

Simulation

You can perform functional and gate-level timing simulations of the megafunction.

f For more information, refer to the appropriate chapter in the Simulation section in

volume 3 of the Quartus II Handbook.

If phase-shifting occurs after a PLL reconfiguration, use gate-level timing simulation
instead of functional simulation to verify the correct counter settings and phase shifts.
For non-zero PLL phase shifts, the frequency of the output clocks after a
reconfiguration is correct, but the phase may be incorrect. If the phase shift is
significant, use gate-level timing simulation to verify the timing behavior.

Functional Description—Implementing Multiple Reconfiguration Using an External ROM

The ALTPLL_RECONFIG megafunction allows you to reconfigure the PLL using an
external ROM with multiple configuration files. With this feature, you can perform
the following:

■ Specify an external ROM and feed its content to the ALTPLL_RECONFIG

megafunction.

■ Use the megafunction with multiple PLL configuration settings that are stored in

configuration files during user mode.

■ Use the megafunction with applications that require flexible dynamic-shifting of

PLL settings during user mode.

■ Reconfigure the initial PLL settings from a source other than an embedded

random-access memory (RAM), such as an off-chip flash device, which is useful in
HardCopy-type applications.

1 This feature is available for Stratix III, Stratix IV, Cyclone III, Cyclone IV,

HardCopy III, HardCopy IV, and Arria II GX devices only.

To support reconfiguration from multiple configuration files, the
ALTPLL_RECONFIG megafunction has three input ports and two output ports:

■ The

write_from_rom

input port signals the ALTPLL_RECONFIG megafunction

instantiation to write to the scan cache from the ROM.

■ The

■ The

rom_data_in

input port holds data from the ROM.

reset_rom_address

input port lets you restart the read process from the ROM.

The data arrives serially from the ROM, starting from bit 0.

■ The

rom_address_out

output bus holds the current address of the ROM data to be

written to the scan cache.

■ The

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

write_rom_ena

output port enables the intended ROM to be read out.

Functional Description—Implementing Multiple Reconfiguration Using an External ROM Page 7

The input and output ports to support reconfiguration using multiple configuration
files are shown in Figure 3, circled in red.

Figure 3. Ports to Support Reconfiguration Using Multiple Configuration Files

ALTPLL_RECONFIG

reconfig
read_param
write_param

data_in[8:0]
counter_type[3:0]

counter_param[2:0]
pll_scandataout

clock
reset

pll_areset_in

busy

data_out[8:0]

pll_scanclk

pll_scandata

pll_scanaclr

pll_areset

write_from_rom
rom_data_in
reset_rom_address

inst

rom_address_out

write_rom_ena

The reconfiguration feature using multiple configuration files allows you to feed data
from multiple ROMs to a multiplexer that feeds the
a sample design. In this scheme, the

write_rom_ena

rom_data_in

signal feeds back to the ROM as

the enable signal, which allows the ROM to be read out. The

port. Figure 4 shows

rom_address_out

bus

provides the intended ROM address, which determines the exact ROM data.

Figure 4. Typical Scheme for Reconfiguring PLLs from External ROMs

write_from_rom

ROM

altpll_reconfig

M
U

X

ROM

rom_data_in

write_rom_ena

rom_address_out

ROM

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 8 Functional Description—Implementing Multiple Reconfiguration Using an External ROM

To copy the data from a ROM to the ALTPLL_RECONFIG megafunction scan cache (a
memory location that stores the PLL reconfiguration settings), you must hold the

write_from_rom

signal on the first rising edge of the clock after the

signal high for 1 clock cycle. The megafunction asserts the busy

write_from_rom

signal goes high.

The busy signal remains asserted until all the bits are written into the scan cache.

On the second rising edge of the clock after the

write_from_rom

signal goes low

again, the intended ROM address for the write operation appears on the

rom_address_out
rom_address_out

megafunction instantiation. The
rising edge of the clock after the

port. The data of the ROM specified by the intended address on
is fed to the rom_

data_in

input port of the ALTPLL_RECONFIG

write_rom_ena
write_from_rom

signal is also asserted on the second

signal goes low again (refer to

Figure 5).

Figure 5. Beginning Write to the Scan Cache of the ALTPLL_RECONFIG Megafunction from the ROM

The writing-to-scan cache process continues until the address reaches the specific size
of the scan cache (234 for Stratix III device top and bottom PLL, 180 for Stratix III
device left and right PLL, and 144 for Cyclone III PLL). This process is completed
when the

busy

signal is deasserted. This means that the scan cache of the
ALTPLL_RECONFIG megafunction is written with the intended reconfiguration
settings from the ROM.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Functional Description—Implementing Multiple Reconfiguration Using an External ROM Page 9

After this, the

reconfig

signal can be asserted for 1 clock cycle to reconfigure the PLL
to the intended settings that have been written to the scan cache of the
ALTPLL_RECONFIG megafunction (refer to Figure 6).

Figure 6. Completing Write to the Scan Cache of the ALTPLL_RECONFIG Megafunction from the ROM

Note to Figure 6:

(1) This figure also shows the beginning of the reconfiguration process.

If you assert the
1 clock cycle and the
asserted, the write process then restarts from address

reset_rom_address

rom_address_out

signal, the

write_rom_ena

signal resets. When the

0

(refer to Figure 7).

signal is deasserted for

write_rom_ena

(1)

gets

Figure 7. Asserting the reset_rom_address Signal

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 10 Design Example

Design Example

You can download design examples for this megafunction from the following
locations:

■ On the Documentation: Quartus II Development Software page, in the Using

Megafunctions section under I/O

■ On the Documentation: User Guides webpage, with this user guide

The designs are simulated using the ModelSim
waveform display of the device behavior. For more information about the ModelSim­Altera software, refer to the ModelSim-Altera Software Support page on the Altera
website. The support page includes links to such topics as installation, usage, and
troubleshooting.

Frequency Division

This design example uses the ALTPLL_RECONFIG megafunction to change the clock
frequency of an enhanced PLL. This example demonstrates how to reconfigure the
counter using the ALTPLL_RECONFIG megafunction to vary the frequency of this
counter by changing the c value. Figure 8 shows the formula for changing the c value
for different PLL output frequencies.

®

-Altera software to generate a

c0

Figure 8. Frequency Division Formula

Divide-by value = c = (Fin * m)/(Fout * n)

Where:
c value = High time count = Low time count
Fin = Input frequency
m = m modulus value
n = n modulus value
Fout = Required output frequency

This example reconfigures the output frequency of

c0

from 100to50MHz by

changing the divide-by value from 3 to 6.

Generating the ALTPLL and ALTPLL_RECONFIG Megafunctions

To generate the ALTPLL and ALTPLL_RECONFIG megafunctions, follow these steps:

1. Open the altpll_reconfig_DesignExample_ex1.zip file and extract

pll_recon_ex1_1.1.qar.

2. In the Quartus II software, open the pll_recon_ex1_1.1.qar file and restore the

archive file into your working directory.

3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the

MegaWizard Plug-In Manager appears.

4. Select Create a new custom megafunction variation.

5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Design Example Page 11

6. In the MegaWizard Plug-In Manager pages, select or verify the configuration

settings listed in Tab le 2. Click Next to advance from one page to the next.

Table 2. Configuration Settings for the ALTPLL Megafunction (Part 1 of 2)

MegaWizard Plug-In

Manager Page

2a

Parameter Settings

(General/Modes)

Parameter Settings
(Scan/Inputs/Lock)

Output Clocks

(clk c0)

EDA Generate netlist Turned off

Settings Value

Megafunction Under the I/O category, select ALTPLL

Which device family will you be using? Stratix

Which type of output file do you want to
create?

VHDL

What name do you want for the output file? reconfig_pll

Return to this page for another create
operation

Turned on

Currently selected device family Stratix

Match project/default Turned on

Which device speed grade will you be
using?

Any

What is the frequency of inclk0 input 100 MHz

Which PLL type will you be using? Enhanced PLL

How will the PLL outputs be generated?

Which output clock will be compensated
for?

Create optional inputs for dynamic
reconfiguration

Long chain: All 6 core and 4 external clocks
are available

Create an ‘pllena’ input to selectively enable
the PLL

Create an ‘areset’ input to asynchronously
reset the PLL

Create an ‘pfdena’ input to selectively
enable the phase/frequency detector

Select Use the feedback path inside the PLL.
Select In normal mode

c0

Turned on

Selected

Turned off

Turned on

Turned off

Create ‘locked’ output Turned on

Create output file(s) using ‘Advanced’ PLL
parameters

Turned off

Use this clock Turned on

Enter output clock frequency 100 MHz

Clock phase shift 0 degrees

Clock duty cycle (%) 50

Create a clock enable input Turned off

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 12 Design Example

Table 2. Configuration Settings for the ALTPLL Megafunction (Part 2 of 2)

MegaWizard Plug-In

Manager Page

Summary

Variation file Turned on

PinPlanner ports PPF file Turned on

AHDL Include file Turned on

VHDL component declaration file Turned on

Quartus II symbol file Turned on

Instantiation template file Turned on

7. Click Finish. The

Settings Value

reconfig_pll

module is built.

8. Click OK. The MegaWizard Plug-In Manager resets to page 2a to allow you to

create a new custom megafunction variation.

9. In the MegaWizard Plug-In Manager pages, select or verify the configuration

settings listed in Tab le 3. Click Next to advance from one page to the next.

Table 3. Configuration Settings for the ALTPLL_RECONFIG Megafunction

MegaWizard Plug-In

Manager Page

2a

Parameter Settings

(General)

Parameter Settings

(General 2)

EDA Generate netlist Turned off

Summary

Megafunction

Which device family will you be using? Stratix

Which type of output file do you want to
create?

What name do you want for the output file? pll_reconfig

Return to this page for another create
operation

Currently selected device family Stratix

Match project/default Turned on

Which scan chain type will you be using Long chain

Do you want to specify initial value of the
scan chain?

File name pll_j1__clk0.mif

Do not use pre initialized RAM - initialize
from ROM instead

Variation file Turned on

AHDL Include file Turned on

VHDL component declaration file Turned on

Quartus II symbol file Turned on

Instantiation template file Turned on

Settings Value

Under the I/O category, select
ALTPLL_RECONFIG

VHDL

Turned off

Select Yes, use this file for the content data

Turned off

10. Click Finish. The

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

pll_reconfig

module is built.

Design Example Page 13

Compiling the ALTPLL and ALTPLL_RECONFIG Megafunctions

To add the ALTPLL megafunction to the ALTPLL_RECONFIG megafunction, and
then compile the design in the Quartus II software, follow these steps:

1. On the Project menu, click Add/Remove File in Project. The Settings dialog box

appears.

2. In the Category list, select Files.

3. Click Browse (...) after File name and select pll_recon_ex1.vhd from the project

folder. This file is the top-level module that contains the port-mapping between
the

pll_reconfig

4. Click Add to add the top-level file to the project.

5. Click OK.

6. On the File menu, click Save Project.

The top-level file is added to the project.

7. To compile the design, on the Processing menu, click Start Compilation.

8. When the Full Compilation was successful message box appears, click OK.

and

reconfig_pll

instances.

You have now created and compiled the complete design file, which can be viewed in
the RTL Viewer (Figure 9). To display the RTL Viewer, in the Tools menu, select
Netlist Viewers, and click on RTL Viewer.

Figure 9. RTL Viewer — Complete Design File

Simulating the Design Example

To simulate the design example using the ModelSim-Altera software, follow these
steps:

1. Unzip the altpll_reconfig_ex1_msim.zip file to any working directory on your

PC.

2. Browse to the folder in which you unzipped the files.

3. Open remote_update_ex2.do in a text editor.

4. In line 1 of the altpll_reconfig_ex1_msim.do file, ensure that the directory path of

the library files is correct. For example, C:/Modeltech_ae/altera/verilog/stratix.

5. On the File menu, click Save.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 14 Design Example

6. Launch the ModelSim-Altera software.

7. On the File menu, click Change Directory.

8. Select the folder in which you unzipped the files.

9. Click OK.

10. On the Tools menu, click Execute Macro.

11. Select the altpll_reconfig_ex1_msim.do file and click Open. This is a script file for

ModelSim-Altera software to automate all the necessary settings for the
simulation.

12. Verify the results shown in the Wave window.

You can rearrange, remove, and add signals, and change the radix by modifying the
script altpll_reconfig_ex1_msim.do.

Figure 10 and Figure 11 show the expected simulation results in the ModelSim-Altera

software. Figure 11 shows the change in

Figure 10. Simulation Results in the ModelSim-Altera Software (8.9 to 9.5 ms)

c0

frequency starting from 12.75 ms.

Figure 11. Simulation Results in the ModelSim-Altera Software (9.5 to 13.5 ms)

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation

Design Example Page 15

Duty cycle = (Ch/Ct) % high time count and (Cl/Ct) % low time count
with RSELODD = 0

Where:
Ch = High time count
Cl = Low time count
Ct = Total time

When you set RSELODD = 1, you subtract 0.5 cycles from the high time and
you add 0.5 cycles to the low time.

For example, if:
Ch = 2 cycles
Cl = 1 cycle
(Note: For odd division factors, the larger number is for the
Ch counter; the smaller number is for the CI counter.)

Setting RSELODD = 1 effectively changes the Ch and Cl to:
High time count = 1.5 cycles

Low time count = 1.5 cycles
Duty cycle = (1.5/3) % high time count and (1.5/3) % low time count

Pulse Width Variation

This design example uses the ALTPLL_RECONFIG megafunction to modify the pulse
width of an enhanced PLL. This example demonstrates how to reconfigure the
counter using the ALTPLL_RECONFIG megafunction to vary the pulse width of this
counter by changing the high-count and low-count values. The formula for changing
the duty cycle is shown in Figure 12.

Figure 12. Changing the Duty Cycle Formula

c1

In this example, the pulse width is programmed to change from 50% to 25% , and then
to 75% of the duty cycle.

Generating the ALTPLL and ALTPLL_RECONFIG Megafunctions

To generate the ALTPLL and ALTPLL_RECONFIG megafunctions, perform the
following steps:

1. Open ALTPLL_RECONFIG_DesignExample_ex2.zip and extract

pll_recon_ex2_1.1.qar.

2. In the Quartus II software, open pll_recon_ex2_1.1.qar and restore the archive file

into your working directory.

3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the

MegaWizard Plug-In Manager appears.

4. Select Create a new custom megafunction variation.

5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

Page 16 Design Example

6. In the MegaWizard Plug-In Manager pages, select or verify the configuration

settings listed in Tab le 4. Click Next to advance from one page to the next.

Table 4. Configuration Settings for the ALTPLL Megafunction (Part 1 of 2)

MegaWizard

Plug-In Manager

Settings Value

Page

Megafunction Under the I/O category, select ALTPLL

Which device family will you be using? Stratix

2a

Which type of output file do you want to
create?

VHDL

What name do you want for the output file? reconfig_pll

Return to this page for another create
operation

Tur n e d o n

Currently selected device family Stratix

Match project/default Turned on

Parameter Settings

(General/Modes)

Parameter Settings
(Scan/Inputs/Lock)

Which device speed grade will you be
using?

What is the frequency of inclk0 input 20 MHz

Which PLL type will you be using? Enhanced PLL

How will the PLL outputs be generated?

Which output clock will be compensated
for?

Create optional inputs for dynamic
reconfiguration

Long chain: All 6 core and 4 external clocks
are available

Create an ‘pllena’ input to selectively enable
the PLL

Create an ‘areset’ input to asynchronously
reset the PLL

Create an ‘pfdena’ input to selectively
enable the phase/frequency detector

Any

Select Use the feedback path inside the PLL.
Select In normal mode

c1

Tur n e d o n

Selected

Tur n e d o f f

Tur n e d o n

Tur n e d o f f

Create ‘locked’ output Turned on

Create output file(s) using ‘Advanced’ PLL
parameters

Tur n e d o f f

Use this clock Turned on

Output Clocks

(clk c1)

Enter output clock frequency 15 MHz

Clock phase shift 0 degrees

Clock duty cycle (%) 50

Create a clock enable input Turned off

EDA Generate netlist Turned off

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation