Altera Phase-Locked Loop User Manual
2015.05.04
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Altera Phase-Locked Loop (Altera PLL) IP Core User
Guide
UG-01087
Subscribe
Send Feedback
The Altera PLL megafunction IP core allows you to configure the settings of PLL.
Altera PLL IP core supports the following features:
• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buffer, and LVDS mode.
• Generates up to 18 clock output signals for the Arria® V and Stratix® V devices and nine clock output
signals for the Cyclone® V device.
• Switches between two reference input clocks.
• Supports both the adjacent PLL (adjpllin) and the C-Counter clock source (cclk) inputs to connect
with an upstream PLL in PLL cascading mode.
• Supports PLL output cascading.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
Related Information
• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.
• Operation Modes on page 9
• Output Clocks on page 9
• Reference Clock Switchover on page 10
• PLL-to-PLL Cascading on page 10
• PLL Output Counter Cascading on page 14
Device Family Support
The Altera PLL IP core supports the Arria V, Cyclone V, and Stratix V device families.
Altera PLL IP Core Parameters
The Altera PLL IP core parameter editor appears in the PLL category of the IP Catalog.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2
Altera PLL IP Core Parameters - General Tab
Altera PLL IP Core Parameters - General Tab
Table 1: Altera PLL IP Core Parameters - General Tab
Parameter Legal Value Description
UG-01087
2015.05.04
Device Speed Grade Stratix V: 1–4,
Arria V: 3–6,
Specifies the speed grade for a device. The lower the
number, the faster the speed grade.
Cyclone V: 6–
8
PLL Mode Integer-N PLL
or Fractional-
Specifies the mode used for the Altera PLL IP core. The
default mode is Integer-N PLL.
N PLL
Reference Clock Frequency — Specifies the input frequency for the input clock, refclk, in
MHz. The default value is 100.0 MHz. The minimum and
maximum value is dependent on the selected device. The
PLL reads only the numerals in the first six decimal places.
Altera Corporation
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback
UG-01087
2015.05.04
Altera PLL IP Core Parameters - General Tab
Parameter Legal Value Description
3
Operation Mode direct,
external
feedback,
normal,
source
synchronous,
zero delay
buffer, or lvds
Specifies the operation of the PLL. The default operation is
direct mode.
• If you select the direct mode, the PLL minimizes the
length of the feedback path to produce the smallest
possible jitter at the PLL output.The internal-clock and
external-clock outputs of the PLL are phase-shifted with
respect to the PLL clock input. In this mode, the PLL
does not compensate for any clock networks.
• If you select the normal mode, the PLL compensates for
the delay of the internal clock network used by the clock
output. If the PLL is also used to drive an external clock
output pin, a corresponding phase shift of the signal on
the output pin occurs.
• If you select the source synchronous mode, the clock
delay from pin to I/O input register matches the data
delay from pin to I/O input register.
• If you select the external feedback mode, you must
connect the fbclk input port to an input pin. A boardlevel connection must connect both the input pin and
external clock output port, fboutclk. The fbclk port is
aligned with the input clock.
• If you select the zero delay buffer mode, the PLL must
feed an external clock output pin and compensate for the
delay introduced by that pin. The signal observed on the
pin is synchronized to the input clock. The PLL clock
output connects to the altbidir port and drives
zdbfbclk as an output port. If the PLL also drives the
internal clock network, a corresponding phase shift of
that network occurs.
• If you select the lvds mode, the same data and clock
timing relationship of the pins at the internal SERDES
capture register is maintained. The mode compensates
for the delays in LVDS clock network, and between the
data pin and clock input pin to the SERDES capture
register paths.
Enable locked output port
Turn on or
Turn off
Enable physical output
clock parameters
Turn on or
Turn off
Number of Clocks Stratix V and
Arria V: 1–18,
Cyclone V: 1–
9
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback
Turn on to enable the locked port.
Turn on to enter physical PLL counter parameters instead of
specifying a desired output clock frequency.
Specifies the number of output clocks required for each
device in the PLL design. The requested settings for output
frequency, phase shift, and duty cycle are shown based on
the number of clocks selected.
Altera Corporation
4
Altera PLL IP Core Parameters - Clock Switchover Tab
Parameter Legal Value Description
Desired Frequency
(1)
— Specifies the output clock frequency of the corresponding
output clock port, outclk[], in MHz. The default value is
100.0 MHz. The minimum and maximum values depend on
the device used. The PLL only reads the numerals in the first
six decimal places.
Actual Frequency — Specifies the actual value for the output clock frequency.
Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output
clock port, outclk[], in picoseconds (ps) or degrees.
Phase Shift — Specifies the requested value for the phase shift. The default
value is 0 ps.
Actual Phase Shift — Specifies the actual value for the phase shift.
Duty Cycle 1–99 Specifies the duty cycle in percentage for the corresponding
output clock port, outclk[]. The default value is 50%.
Fractional carry out
(2)(3)
8, 16, 24, or 32 Specifies the fractional carry out (Fcout) for the Delta Sigma
Modulator (DSM) mode for PLL. The fractional carry out
determines the denominator in the equation K/2^Fcout.
DSM Order
(2)(3)
1st_order,
2nd_order,
Specifies the DSM order for shifting the fractional noise to
be filtered out by the PLL to high frequencies.
3rd_order, or
disable
UG-01087
2015.05.04
Multiply Factor (MCounter)
(3)
Fractional Multiply Factor
(2)(3)
(K)
Divide Factor (N-
Counter)
(3)
Make this a cascade
counter
(3)(4)
Divide Factor (CCounter)
(3)
1-512 Specifies the multiply factor of M-counter.
1 to (2^Fcout-1)Specifies the fractional multiply factor of DSM. Fcout is the
value of fractional carry out parameter.
1-512 Specifies the divide factor of N-counter.
Turn on or
Turn off
Turn on to cascade this counter into the next counter
output for larger division factor.
1-512 Specifies the divide factor for the output clock (C-counter)
Altera PLL IP Core Parameters - Clock Switchover Tab
Table 2: Altera PLL IP Core Parameters - Clock Switchover Tab
Parameter Legal Value Description
Create a second input clk
‘refclk1’
(1)
This parameter is only available when Enable physical output clock parameters is turned off.
(2)
This parameter is only available in Fractional-N PLL mode.
(3)
This parameter is only available when Enable physical output clock parameters is turned on.
(4)
This feature is only supported in Quartus® II version 13.1 and onwards.
Turn on or
Turn off
Turn on to provide a backup clock attached to your PLL
that can switch with your original reference clock.
Altera Corporation
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback
UG-01087
2015.05.04
Altera PLL IP Core Parameters - Clock Switchover Tab
Parameter Legal Value Description
5
Second Reference Clock
Frequency
Switchover Mode
—
Automatic
Switchover,
Manual
Switchover, or
Automatic
Switchover
with Manual
Override
Selects the frequency of the second input clock signal. The
default value is 100.0 MHz. The minimum and maximum
value is dependent on the device used. The PLL reads only
the numerals in the first six decimal places.
The PLL is automatically configured to satisfy its legality
requirements for the primary reference clock only. If the
second reference clock frequency is different, this may cause
an illegal VCO or PFD frequency error. To avoid this error,
you can turn on Enable physical output clock parameters
and manually configure the PLL such that the frequency is
legal for both refclk inputs.
Specifies the switchover mode for design application. The IP
supports three switchover modes:
• If you select the Automatic Switchover mode, the PLL
circuitry monitors the selected reference clock. If one
clock stops, the circuit automatically switches to the
backup clock in a few clock cycles and updates the status
signals, clkbad and activeclk.
• If you select the Manual Switchover mode, when the
control signal, extswitch, changes from logic low to
logic high, and stays high for at least three clock cycles,
the input clock switches to the other clock. The
extswitch can be generated from FPGA core logic or
input pin.
• If you select Automatic Switchover with Manual
Override mode, when the extswitch signal is high, it
overrides the automatic switch function. As long as
extswitch remains high, further switchover action is
blocked. To select this mode, your two clock sources
must be running and the frequency of the two clocks
cannot differ by more than 20%. If both clocks are not on
the same frequency, but their period difference is within
20%, the clock loss detection block will detect the lost
clock. The PLL most likely drops out of lock after the
PLL clock input switchover and needs time to lock again.
Switchover Delay
Create an ‘active_clk’ signal
to indicate the input clock
0–7 Adds a specific amount of cycle delay to the switchover
Turn on or
Turn off
in use
Create a ‘clkbad’ signal for
each of the input clocks
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback
Turn on or
Turn off
process. The default value is 0.
Turn on to create the activeclk output. The activeclk
output indicates the input clock which is in use by the PLL.
Output signal low indicates refclk and output signal high
indicates refclk1.
Turn on to creates two clkbad outputs, one for each input
clock. Output signal low indicates the clock is working and
output signal high indicates the clock is not working.
Altera Corporation
6
Altera PLL IP Core Parameters - Cascading Tab
Altera PLL IP Core Parameters - Cascading Tab
Table 3: Altera PLL IP Core Parameters - Cascading Tab
Parameter Legal Value Description
UG-01087
2015.05.04
Create a ‘cascade out’ signal
to connect with a
downstream PLL
Specifies which outclk to be
used as cascading source
Turn on or
Turn off
Stratix V and
Arria V: 1–18,
Turn on to create an output port, which indicates that this
PLL will be used as a source and it connects with a destina‐
tion (downstream) PLL.
Specifies the cascading source.
Cyclone V: 1–
9
Create an adjpllin or cclk
signal to connect with an
upstream PLL
PLL Cascading Mode Create an
Turn on or
Turn off
adjpllin signal
to connect
with an
upstream PLL
or Create a
cclk signal to
Turn on to create an input port, which indicates that this
PLL will be used as a destination and it connects with a
source (upstream) PLL.
• If you select Create an adjpllin signal to connect with
an upstream PLL, the adjpllin signal is created to
connect with an upstream PLL during cascading.
• If you select Create a cclk signal to connect with an
upstream PLL, the cclk
with an upstream PLL during cascading.
connect with
an upstream
PLL
Altera PLL IP Core Parameters - MIF Streaming Tab
(5)
signal is created to connect
Table 4: Altera PLL IP Core Parameters - MIF Streaming Tab
Parameter Legal Value Description
Generate MIF file Turn on or
Turn off
Turn on to generate the .mif for the current PLL profile. You
must turn on the Enable dynamic reconfiguration of PLL
parameter in the Settings tab before selecting this function.
The generated .mif contains a PLL profile, and a collection of
physical parameters—such as M, N, C, K, bandwidth, and
charge pump—that defines that PLL. You can then load
this .mif into the Altera PLL Reconfig IP core.
Enable Dynamic Phase
Shift for MIF Streaming
Turn on or
Turn off
Turn on to store dynamic phase shift properties for PLL
reconfiguration. You must turn on the Enable dynamic
reconfiguration of PLL parameter in the Settings tab
before selecting this function.
DPS Counter Selection C0–C17, All
Selects the counter to undergo dynamic phase shift.
C, or M
(5)
Not supported in Cyclone V devices.
Altera Corporation
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback
Loading...