Altera PCI Compiler User Manual

PCI Compiler

User Guide

c The PCI Compiler is scheduled for product obsolescence and discontinued support

as described in PDN1410. Therefore, Altera does not recommend use of this IP in
new designs. For more information about Altera’s current IP offering, refer to
Altera’s Intellectual Property website.

101 Innovation Drive
San Jose, CA 95134
www.altera.com

Compiler Version: 11.1
Document Date: October 2011

i–ii User Guide Version 11.1 Altera Corporation
PCI Compiler

Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,

ISO

9001:2008

Registered

Printed on recycled paper

specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted
otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names
are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap­plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in
accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service de­scribed herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest
version of device specifications before relying on any published information and before placing orders for products or services.

UG-PCICOMPILER-4.12

iii Altera Corporation
i–iv User Guide Version 11.1 Altera Corporation

PCI Compiler

Contents

About PCI Compiler

Introduction ................................................................................................................................................ 1

Release Information ................................................................................................................................... 2

Device Family Support ............................................................................................................................. 2

Features ....................................................................................................................................................... 3

Common Features .................................................................................................................................. 3

PCI Compiler with MegaWizard Plug-in Manager Flow ................................................................4

PCI Compiler with SOPC Builder Flow ..............................................................................................4

General Description ................................................................................................................................... 5

PCI MegaCore Functions ......................................................................................................................5

PCI Testbench .........................................................................................................................................6

PCI Compiler with MegaWizard Plug-in Manager Flow ................................................................6

PCI Compiler With SOPC Builder Flow .............................................................................................7

Selecting the Appropriate Flow for Your Design ................................................................................. 9

PCI Compiler With SOPC Builder Flow .............................................................................................9

PCI Compiler With MegaWizard Plug-in Manager Flow .............................................................. 10

Compliance Summary ............................................................................................................................ 10

Performance and Resource Utilization ................................................................................................. 11

PCI Compiler with MegaWizard Plug-in Manager Flow ..............................................................11

PCI Compiler with SOPC Builder Flow ............................................................................................13

Installation and Licensing ...................................................................................................................... 17

OpenCore Plus Evaluation.................................................................................................................. 19

OpenCore Plus Time-Out Behavior...................................................................................................19

Section I. PCI Compiler With MegaWizard Plug-In Manager Flow

Chapter 1. Getting Started

Design Flow ............................................................................................................................................ 1–1

PCI MegaCore Function Design Walkthrough ................................................................................. 1–2

Create a New Quartus II Project .................................................................................................... 1–2

Launch IP Toolbench ....................................................................................................................... 1–4

Step 1: Parameterize ......................................................................................................................... 1–5

Step 2: Set Up Simulation ................................................................................................................ 1–7

Step 3: Generate ................................................................................................................................ 1–7

Simulate the Design ............................................................................................................................... 1–9

Simulation in the Quartus II Software ........................................................................................ 1–11

The Quartus II Simulation Files ......................................................................................................... 1–12

Master Simulation Files ................................................................................................................. 1–13

Target Simulation Files .................................................................................................................. 1–15

Altera Corporation v

Contents

Compile the Design ............................................................................................................................. 1–16

Program a Device ................................................................................................................................ 1–18

PCI Timing Support ............................................................................................................................ 1–18

Using the Reference Designs .............................................................................................................. 1–19

pci_mt32 MegaCore Function Reference Design ....................................................................... 1–19

Synthesis & Compilation Instructions ................................................................................... 1–20

pci_mt64 MegaCore Function Reference Design ....................................................................... 1–21

synthesis & Compilation Instructions .................................................................................... 1–22

Chapter 2. Parameter Settings

Parameterize PCI Compiler ................................................................................................................. 2–1

PCI MegaCore Function Settings ........................................................................................................ 2–1

Read-Only PCI Configuration Registers ............................................................................................ 2–2

PCI Base Address Registers (BARs) .................................................................................................... 2–2

Advanced PCI MegaCore Function Features .................................................................................... 2–3

Optional Registers ....................................................................................................................... 2–3

Optional Interrupt Capabilities ................................................................................................. 2–4

Master Features ........................................................................................................................... 2–4

Variation File Parameters ..................................................................................................................... 2–7

Chapter 3. Functional Description

Functional Overview ............................................................................................................................. 3–1

Target Device Signals & Signal Assertion .................................................................................... 3–6

Master Device Signals & Signal Assertion .................................................................................... 3–9

PCI Bus Signals .................................................................................................................................... 3–11

Parameterized Configuration Register Signals .......................................................................... 3–15

Local Address, Data, Command, & Byte Enable Signals ......................................................... 3–16

Target Local-Side Signals .............................................................................................................. 3–20

Master Local-Side Signals ............................................................................................................. 3–24

PCI Bus Commands ............................................................................................................................ 3–27

Configuration Registers ...................................................................................................................... 3–28

Vendor ID Register ......................................................................................................................... 3–31

Device ID Register .......................................................................................................................... 3–31

Command Register ........................................................................................................................ 3–32

Status Register ................................................................................................................................ 3–33

Revision ID Register ...................................................................................................................... 3–34

Class Code Register ........................................................................................................................ 3–35

Cache Line Size Register ............................................................................................................... 3–35

Latency Timer Register .................................................................................................................. 3–36

Header Type Register .................................................................................................................... 3–36

Base Address Registers .................................................................................................................. 3–37

CardBus CIS Pointer Register ....................................................................................................... 3–40

Subsystem Vendor ID Register ....................................................................................................3–40

Subsystem ID Register ................................................................................................................... 3–41

Expansion ROM Base Address Register ..................................................................................... 3–41

Capabilities Pointer ........................................................................................................................ 3–42

Interrupt Line Register .................................................................................................................. 3–43

vi User Guide Version 11.1 Altera Corporation
PCI Compiler

Contents

Interrupt Pin Register .................................................................................................................... 3–43

Minimum Grant Register .............................................................................................................. 3–43

Maximum Latency Register .......................................................................................................... 3–44

Target Mode Operation ...................................................................................................................... 3–44

Target Read Transactions .............................................................................................................. 3–48

Memory Read Transactions ..................................................................................................... 3–48

I/O Read Transactions ............................................................................................................. 3–61

Configuration Read Transactions ........................................................................................... 3–62

Target Write Transactions ............................................................................................................. 3–63

Memory Write Transactions .................................................................................................... 3–63

I/O Write Transactions ............................................................................................................ 3–75

Configuration Write Transactions .......................................................................................... 3–76

Target Transaction Terminations .................................................................................................3–77

Retry ............................................................................................................................................ 3–77

Disconnect .................................................................................................................................. 3–79

Target Abort ............................................................................................................................... 3–86

Additional Design Guidelines for Target Transactions ............................................................ 3–88

Master Mode Operation ..................................................................................................................... 3–88

PCI Bus Parking .............................................................................................................................. 3–92

Design Consideration ............................................................................................................... 3–92

Master Read Transactions ............................................................................................................. 3–93

Memory Read Transactions ..................................................................................................... 3–93

I/O & Configuration Read Transactions ............................................................................. 3–107

Master Write Transactions .......................................................................................................... 3–108

Memory Write Transactions .................................................................................................. 3–108

I/O & Configuration Write Master Transactions ............................................................... 3–124

Abnormal Master Transaction Termination ............................................................................. 3–125

Latency Timer Expires ............................................................................................................ 3–125

Retry .......................................................................................................................................... 3–125

Disconnect Without Data ....................................................................................................... 3–126

Disconnect with Data ............................................................................................................. 3–126

Target Abort ............................................................................................................................. 3–126

Master Abort ............................................................................................................................ 3–126

Host Bridge Operation ...................................................................................................................... 3–127

Using the PCI MegaCore Function as a Host Bridge .............................................................. 3–127

PCI Configuration Read Transaction from the pci_mt64 Local Master Device to the Internal

Configuration Space ............................................................................................................... 3–127

PCI Configuration Write Transaction from the pci_mt64 Local Master Device to the Internal

Configuration Space ............................................................................................................... 3–129

64-Bit Addressing, Dual Address Cycle (DAC) ............................................................................ 3–131

Target Mode Operation ............................................................................................................... 3–131

64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction ................................ 3–132

Master Mode Operation .............................................................................................................. 3–134

64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction ............................ 3–134

Chapter 4. Testbench

General Description ............................................................................................................................... 4–1

Altera Corporation User Guide Version 11.1 vii

PCI Compiler

Contents

Features ................................................................................................................................................... 4–2

PCI Testbench Files ............................................................................................................................... 4–2

Testbench Specifications ....................................................................................................................... 4–6

Master Transactor (mstr_tranx) ...................................................................................................... 4–7

PROCEDURES and TASKS Sections ........................................................................................ 4–7

INITIALIZATION Section ......................................................................................................... 4–8

USER COMMANDS Section ..................................................................................................... 4–8

Target Transactor (trgt_tranx) ................................................................................................. 4–12

FILE IO section .......................................................................................................................... 4–13

PROCEDURES and TASKS sections ...................................................................................... 4–13

Bus Monitor (monitor) ................................................................................................................... 4–14

Clock Generator (clk_gen) ............................................................................................................ 4–14

Arbiter (arbiter) .............................................................................................................................. 4–15

Pull Up (pull_up) ........................................................................................................................... 4–15

Local Reference Design ....................................................................................................................... 4–15

Local Target ..................................................................................................................................... 4–17

DMA Engine ................................................................................................................................... 4–17

Local Master .................................................................................................................................... 4–19

lm_lastn Generator ......................................................................................................................... 4–19

Prefetch ............................................................................................................................................ 4–19

LPM RAM ........................................................................................................................................ 4–19

Simulation Flow ................................................................................................................................... 4–20

Section II. PCI Compiler With SOPC Builder Flow

Chapter 5. Getting Started

Design Flow ............................................................................................................................................ 5–1

PCI Compiler with SOPC Builder Flow Design Walkthrough ....................................................... 5–2

Create a New Quartus II Project .................................................................................................... 5–3

Set Up the PCI-Avalon Bridge ........................................................................................................ 5–5

Add the Remaining Components to the SOPC Builder System ................................................ 5–7

Complete the Connections in SOPC Builder ................................................................................ 5–8

Generate the SOPC Builder System ............................................................................................... 5–9

Files Generated by SOPC Builder ................................................................................................ 5–10

Simulate the Design ............................................................................................................................. 5–11

Compile the Design ............................................................................................................................. 5–13

Program a Device ................................................................................................................................ 5–14

Upgrading Systems from a Previous Version ................................................................................. 5–15

Chapter 6. Parameter Settings

System Options-1 ................................................................................................................................... 6–1

PCI Device Mode ........................................................................................................................ 6–1

PCI Target Performance ............................................................................................................. 6–3

PCI Master Performance ............................................................................................................ 6–5

Value of Multiple Pending Reads ....................................................................................................... 6–6

viii User Guide Version 11.1 Altera Corporation
PCI Compiler

Contents

System Options-2 ................................................................................................................................... 6–9

PCI Bus Speed .............................................................................................................................. 6–9

PCI Data Bus Width .................................................................................................................... 6–9

PCI Clock/Reset Settings ........................................................................................................... 6–9

PCI Bus Arbiter ......................................................................................................................... 6–10

PCI Configuration ............................................................................................................................... 6–11

PCI Base Address Registers ..................................................................................................... 6–11

PCI Read-Only Registers .........................................................................................................6–11

Setting the PCI Base Address Register Values ..................................................................... 6–11

Manual Setting of the BAR Size & Avalon Base Address ................................................... 6–14

Avalon Configuration ......................................................................................................................... 6–16

Chapter 7. Functional Description

Functional Overview ............................................................................................................................. 7–1

PCI-Avalon Bridge Blocks ............................................................................................................... 7–2

Avalon-MM Ports ....................................................................................................................... 7–3

Control/Status Register Module .............................................................................................. 7–5

PCI MegaCore Function ............................................................................................................. 7–5

PCI Bus Arbiter ........................................................................................................................... 7–6

Other PCI-Avalon Bridge Modules .......................................................................................... 7–6

PCI Operational Modes ................................................................................................................... 7–6

PCI Target-Only Peripheral Mode Operation ........................................................................ 7–6

PCI Master/Target Peripheral Mode Operation .................................................................... 7–8

PCI Host-Bridge Device Mode Operation ............................................................................. 7–10

Performance Profiles ...................................................................................................................... 7–11

Target Performance .................................................................................................................. 7–12

Master Performance .................................................................................................................. 7–12

Interface Signals ................................................................................................................................... 7–13

PCI Bus Arbiter Signals ................................................................................................................. 7–14

PCI Bus Commands ............................................................................................................................ 7–15

PCI Target Operation .......................................................................................................................... 7–15

Non-Prefetchable Operations ....................................................................................................... 7–17

Non-Prefetchable Write Operations ....................................................................................... 7–18

I/O Write Operations ............................................................................................................... 7–19

Non-Prefetchable Read Operations ........................................................................................ 7–19

Prefetchable Operations ................................................................................................................ 7–21

Prefetchable Write Operations ................................................................................................ 7–22

Prefetchable Read Operations ................................................................................................. 7–23

PCI-to-Avalon Address Translation ............................................................................................ 7–26

PCI Master Operation ......................................................................................................................... 7–27

Avalon-To-PCI Read & Write Operation .................................................................................... 7–28

Avalon-to-PCI Write Requests ................................................................................................ 7–31

Avalon-to-PCI Read Requests ................................................................................................. 7–32

Arbitration Among Pending PCI Master Requests .............................................................. 7–34

Avalon-to-PCI Address Translation ............................................................................................ 7–35

Ordering of Requests ..................................................................................................................... 7–38

Ordering of Avalon-to-PCI Operations ................................................................................. 7–39

Altera Corporation User Guide Version 11.1 ix

PCI Compiler

Contents

Ordering PCI-to-Avalon Operations ...................................................................................... 7–42

PCI Host-Bridge Operation ................................................................................................................ 7–45

Altera-Provided PCI Bus Arbiter ...................................................................................................... 7–45

Interrupts .............................................................................................................................................. 7–46

Generation of PCI Interrupts ................................................................................................... 7–46

Reception of PCI Interrupts .....................................................................................................7–46

Generation of Avalon-MM Interrupts ................................................................................... 7–47

Control & Status Registers ................................................................................................................. 7–47

PCI Interrupt Status Register ........................................................................................................ 7–49

PCI Interrupt Enable Register ...................................................................................................... 7–51

PCI Mailbox Register Access ........................................................................................................ 7–52

Avalon-to-PCI Address Translation Table ................................................................................. 7–53

Read-Only Configuration Registers ............................................................................................ 7–54

Avalon-MM Interrupt Status Register ........................................................................................ 7–56

Avalon-MM Interrupt Enable Register ....................................................................................... 7–60

Avalon Mailbox Register Access ..................................................................................................7–60

Chapter 8. Testbench

General Description ............................................................................................................................... 8–1

Features ................................................................................................................................................... 8–2

PCI Testbench Files ............................................................................................................................... 8–3

Testbench Specifications ....................................................................................................................... 8–4

Master Transactor (mstr_tranx) ...................................................................................................... 8–5

PROCEDURES and TASKS Sections ........................................................................................ 8–5

INITIALIZATION Section ......................................................................................................... 8–6

USER COMMANDS Section ..................................................................................................... 8–7

cfg_rd ............................................................................................................................................ 8–7

cfg_wr ........................................................................................................................................... 8–8

mem_wr_32 .................................................................................................................................. 8–8

mem_rd_32 .................................................................................................................................. 8–9

mem_wr_64 ................................................................................................................................ 8–10

mem_rd_64 ................................................................................................................................ 8–11

io_wr ........................................................................................................................................... 8–11

io_rd ............................................................................................................................................ 8–11

Target Transactor (trgt_tranx) ...................................................................................................... 8–12

FILE IO section .......................................................................................................................... 8–13

PROCEDURES and TASKS sections ...................................................................................... 8–13

Bus Monitor (monitor) ................................................................................................................... 8–13

Arbiter (arbiter) .............................................................................................................................. 8–14

Pull Up (pull_up) ........................................................................................................................... 8–14

Simulation Flow ................................................................................................................................... 8–15

Appendix A. Using PCI Constraint File Tcl Scripts

Introduction ........................................................................................................................................... A–1

PCI Constraint Files .............................................................................................................................. A–1

Simultaneous Switching Noise (SSN) Considerations .................................................................... A–2

Additional Options ............................................................................................................................... A–3

x User Guide Version 11.1 Altera Corporation
PCI Compiler

Contents

-speed ........................................................................................................................................... A–3

-no_compile ................................................................................................................................ A–7

-no_pinouts ................................................................................................................................. A–7

-pin_prefix ................................................................................................................................... A–7

-pin_suffix ................................................................................................................................... A–7

-help ............................................................................................................................................. A–8

Upgrading Assignments from a Previous Version of PCI Compiler ............................................ A–8

Upgrading PCI Assignments Containing Nondefault PCI Pin Names .................................. A–8

Additional Information

Revision History ............................................................................................................................... Info–i

How to Contact Altera .................................................................................................................... Info–ii

Typographic Conventions ............................................................................................................. Info–iii

Altera Corporation User Guide Version 11.1 xi

PCI Compiler

Contents

xii User Guide Version 11.1 Altera Corporation
PCI Compiler

About PCI Compiler

Introduction

The Altera® PCI Compiler provides many options for creating custom,
high-performance PCI bus interface designs. Whether your system’s top
priority is high bandwidth, high speed, or a combination of features, you
can use the PCI Compiler to meet your system requirements.

The PCI Compiler contains the pci_mt64, pci_mt32, pci_t64, and

®

pci_t32 MegaCore

functions, a Verilog HDL and VHDL testbench, and
reference designs. Altera also offers the following development kits as
PCI hardware prototyping platforms:

■ PCI High-Speed Development Kit, Stratix Professional Edition

■ PCI Development Kit, Cyclone II Edition

These kits include a PCI development board, a reference design, software
drivers, and a graphical user interface to help you evaluate the PCI
solution in a system.

You can create PCI systems using one of the following design flows in the

®

Quartus

■ MegaWizard

II software.

TM

Plug-in Manager flow

This option allows you to choose a specific PCI MegaCore function,
specify parameters, generate design files, and manually integrate the
parameterized PCI MegaCore function into your overall system.

■ SOPC Builder flow

This option allows you to build a complete PCI system—component­by-component—using an automatically-generated sytem
interconnect fabric. The SOPC Builder uses the PCI-Avalon®­Memory-Mapped (Avalon-MM) bridge to connect the PCI bus to the
interconnect, allowing you to easily create any system that includes
one or more of the Avalon-MM peripherals.

Altera Corporation User Guide Version 11.1 1
October 2011

Release Information

Release
Information

Device Family Support

Ta bl e 1 provides information about this release of the PCI Compiler.

Table 1. PCI Compiler User Guide Release Information

Item Description

Version 11.1
Release Date October 2011
Ordering Codes IP-PCI/MT64, IP-PCI/T64,

Product IDs

Vendor ID 6AF7

The MegaCore functions provide either final or preliminary support for
target Altera device families:

■ Final support means the core is verified with final timing models for

this device family. The core meets all functional and timing
requirements for the device family and can be used in production
designs.

■ Preliminary support means the core is verified with preliminary

timing models for this device family. The core meets all functional
requirements, but might still be undergoing timing analysis for the
device family. It can be used in production designs with caution.

■ HardCopy Compilation means the core is verified with final timing

models for the HardCopy
functional and timing requirements for the device family and can be
used in production designs.

■ HardCopy Companion means the core is verified with preliminary

timing models for the HardCopy companion device. The core meets
all functional requirements, but might still be undergoing timing
analysis for HardCopy device family. It can be used in production
designs with caution.

IP-PCI/MT32, IP-PCI/T32

pci_mt64 MegaCore function: 0011,
pci_t64 MegaCore function: 0025,
pci_mt32 MegaCore function: 0022,
pci_t32 MegaCore function: 0024

®

device family. The core meets all

2 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

About PCI Compiler

Ta bl e 2 shows the level of support offered by the User Guide MegaCore

functions for each Altera device family.

Table 2. Device Family Support

Device Family Support

Arria®GX
Arria II GX Final

®

Cyclone
Cyclone II Final
Cyclone III Final
Cyclone III LS Final
Cyclone IV (E, GX) Final
HardCopy II HardCopy Compilation
HardCopy III
HardCopy IV (E, GX)

®

II (1)

MAX

®

Stratix
Stratix GX Final
Stratix II Final
Stratix II GX Final
Stratix III Final

IV (E, GX)

Stratix
Other device families No support

Note to Ta b l e 2:

(1) MAX II devices are supported by the pci_mt32 and pci_t32 MegaCore

functions only.

Final

Final

Refer to the What’s New in Altera IP
page of the Altera website.

Final

Final

Final

Features

This section summarizes the features of the PCI Compiler.

Common Features

The following list outlines the common features of the PCI Compiler.

■ Fully compliant with the PCI Special Interest Group (PCI SIG)

PCI Local Bus Specification, Revision 3.0

■ Supports both 32-bit and 64-bit interfaces

■ Supports Master/Target and Target-Only modes

Altera Corporation User Guide Version 11.1 3
October 2011

Features

■ IP functional simulation models enable simulation of a register

transfer level (RTL) model of a PCI MegaCore function in VHDL and
Verilog HDL simulators

■ OpenCore Plus hardware evaluation feature enables testing of a

PCI MegaCore function in hardware prior to purchasing a license

■ Configuration registers:

● Parameterized registers: device ID, vendor ID, class code,

revision ID, BAR0 through BAR5, subsystem ID, subsystem­vendor ID, maximum latency, minimum grant, capabilities list
pointer, expansion ROM BAR

● Parameterized default or preset base address (available for all

six BARs) and expansion ROM base address

● Non-parameterized registers: command, status, header type 0,

latency timer, cache line size, interrupt pin, interrupt line

■ Host bridge application support

PCI Compiler with MegaWizard Plug-in Manager Flow

The following list outlines the features of the PCI Compiler with
MegaWizard Plug-in Manager flow.

■ IP Toolbench wizard-driven interface makes it easy to generate a

custom variation of a PCI MegaCore function

■ PCI target features:

● Capabilities list pointer support

● Expansion ROM BAR support

● Local-side requests for target abort, retry, or disconnect

● Local-side interrupt requests

■ PCI master features (pci_mt64 and pci_mt32 only):

● Allows on-chip arbitration logic

● Allows disabling latency timer

■ 64-bit PCI features (pci_mt64 and pci_t64 only):

● 64-bit addressing support as both master and target

● Initiates 64-bit addressing, using dual-address cycle (DAC)

● Initiates 64-bit memory transactions

● Dynamically negotiates 64-bit transactions and automatically

multiplexes data on the local 64-bit data bus

PCI Compiler with SOPC Builder Flow

The following list outlines the features of the PCI Compiler with SOPC
Builder flow.

■ SOPC Builder ready

■ PCI complexities, such as retry and disconnect are handled by the

PCI/Avalon Bridge logic and transparent to the user

4 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

About PCI Compiler

■ Hard-coded (fixed) or run-time configurable (dynamic) Avalon-to-

PCI address translation

■ Hard-coded or automatic PCI-to-Avalon address translation

■ Separate Avalon Memory-mapped (Avalon-MM) slave ports for PCI

bus access (PBA) and control register access (CRA)

■ Support for Avalon-MM burst mode

■ Option for independent or common PCI and Avalon clock domains

■ Option to increase PCI read performance by increasing the number

of pending reads and maximum read burst size.

■ Internal Arbiter in Host Bridge and Target/Master mode

General Description

This section provides a general description of the following:

■ PCI MegaCore Functions

■ PCI Testbench

■ PCI Compiler with MegaWizard Plug-in Manager Flow

■ PCI Compiler with SOPC Builder Flow

PCI MegaCore Functions

The PCI MegaCore functions are hardware-tested, high-performance,
flexible implementations of PCI interfaces. These functions handle the
PCI protocol and timing requirements internally. The back-end interface
is designed for easy integration, allowing you to focus your engineering
efforts on value-added custom development to significantly reduce time­to-market.

Optimized for Altera devices, the PCI MegaCore functions support
configuration, I/O, and memory transactions. The small size of the
functions, combined with the high density of Altera's devices, provides
ample resources for custom local logic to accompany the PCI interface.
The high performance of Altera's devices also enables these functions to
support unlimited cycles of zero wait state memory-burst transactions.
These functions can operate at either 33- or 66-MHz PCI bus clock speeds,
allowing them to achieve up to 132 Megabytes per second (MBytes/s)
throughput in a 32-bit 33-MHz PCI bus system and up to 528 MBytes/s
throughput in a 64-bit 66-MHz PCI bus system.

In the pci_mt64 and pci_mt32 functions, the master and target
interfaces can operate independently, allowing maximum throughput
and efficient usage of the PCI bus. For instance, while the target interface
is accepting zero wait state burst write data, the local logic may
simultaneously request PCI bus mastership, thus minimizing latency.

Altera Corporation User Guide Version 11.1 5
October 2011

General Description

To ensure timing and protocol compliance, the PCI MegaCore functions
have been rigorously hardware tested. Refer to “Compliance Summary”

on page 10 for more information on the hardware tests performed.

PCI Testbench

The PCI testbench, provided in Verilog HDL and VHDL, facilitates the
design and verification of systems that implement any of the PCI
MegaCore functions. You can build a PCI behavioral simulation
environment by using components of the PCI testbench, the IP functional
simulation model of your PCI MegaCore function variation, and the rest
of your Verilog HDL or VHDL design.

PCI Compiler with MegaWizard Plug-in Manager Flow

With this flow, you design to a low-level interface that allows custom PCI
transaction design. Because you are designing the logic to interface to the
PCI MegaCore function, you have more control of individual module
functionality.

1 This flow is recommended for users who have previously

designed with the PCI Compiler or whose highest priority is to
minimize design latency.

For example, if you are designing a PCI-to-DDR2 SDRAM controller
interface you need to do the following:

■ Specify the PCI MegaCore function parameters.

■ Design the ‘back end’ user design, including master control logic,

target control logic, data path first-in first-out (FIFO) buffers, and
direct memory access (DMA) engine.

■ Design the DDR2 SDRAM controller interface.

■ Specify the DDR2 SDRAM MegaCore function parameters.

■ Design internal PCI and DDR2 SDRAM logic blocks.

■ Write RTL code that connects the PCI and DDR2 SDRAM blocks.

6 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

Figure 1 shows a PCI-to-DDR2 SDRAM controller interface design using

Master

Control

Logic

Backend User Design

Altera

PCI

MegaCore

Function

PCI
Bus

Altera PCI MegaCore Function Local-Side, Low Level Interface

DDR2 SDRAM Memory Module

DMA

Engine

Tar ge t

Control

Logic

Data

Path

FIFOs

DDR2

SDRAM

Controller

Interface

Altera FPGA

Altera
DDR2

SDRAM

Controller

MegaCore

Function

the PCI Compiler with MegaWizard Plug-in Manager flow; shaded areas
represent user-customized blocks.

Figure 1. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With MegaWizard Flow

About PCI Compiler

f For more information about the PCI Compiler with MegaWizard flow,

refer to Chapter 1, Getting Started.

PCI Compiler With SOPC Builder Flow

With this flow, you specify system components and choose system
options from a rich set of features, and the SOPC Builder then
automatically generates the interconnect logic and simulation
environment. Thus, you define and generate a complete system in
dramatically less time than manually integrating separate IP blocks.

Altera Corporation User Guide Version 11.1 7
October 2011

1 This flow is recommended for users who are new to the PCI

Compiler or whose highest priority is to minimize design time.

General Description

PCI
Bus

PCI Master/Target

Component

DMA

Engine

Altera FPGA

DDR2
SDRAM
Memory

Module

Altera

DDR2

SDRAM

MegaCore

Function

System

Interconnect

Fabric

PCI-Avalon

Bridge

Logic

Altera

PCI

MegaCore

Function

For example, Figure 2 shows the PCI-to-DDR2 SDRAM design using the
PCI Compiler with SOPC Builder flow; the dashed-lines indicate
pre-existing components that are added to the design via the SOPC
Builder graphical user interface (GUI). When comparing Figure 1 with

Figure 2, you can see that the PCI Compiler with SOPC Builder flow

option requires far less user customization.

Figure 2. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With SOPC Builder Flow

f For more information about the PCI Compiler with SOPC Builder flow,

refer to Chapter 5, Getting Started.

8 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

For more information about SOPC Builder, refer to volume 4 of the
Quartus II Handbook.

About PCI Compiler

Selecting the Appropriate Flow for Your Design

Ta bl e 3 summarizes the guidelines for selecting a particular flow over

another. In most cases, the PCI Compiler with SOPC Builder flow is the
appropriate choice.

Table 3. PCI Compiler Parameterization Flow Selection Guidelines

SOPC Builder Flow MegaWizard Plug-in Manager Flow

● You would like to quickly integrate

multiple system blocks.

● You are creating a new PCI design.

● You have limited PCI bus protocol

experience.

● You are migrating a design that

uses a previous version of PCI
Compiler.

● You require features that are not

supported with the SOPC Builder
flow.

PCI Compiler With SOPC Builder Flow

This section lists the advantages and disadvantages of the PCI Compiler
with the SOPC Builder flow.

Advantages

■ Dramatically faster time-to-market

■ Requires minimal PCI bus protocol design expertise

■ Very short learning curve

■ Access to rich feature set

■ Uses simple and flexible GUI to create complete PCI system within

hours

■ Predesigned ‘back end’ and ‘local side’ interconnect

■ Uses an automatically-generated simulation environment

■ Create custom components and integrate them by using the

component wizard

■ All components are automatically interconnected

Disadvantages

■ Does not allow you to customize PCI transaction behavior

■ Some applications may have excessive overhead in size and

performance

Altera Corporation User Guide Version 11.1 9
October 2011

Compliance Summary

PCI Compiler With MegaWizard Plug-in Manager Flow

This section lists the advantages and disadvantages of the PCI Compiler
with MegaWizard Plug-in Manager flow.

Advantages

■ More control of the system feature set

■ Can design directly from the PCI interface to peripheral devices

■ Can access local-side interface to reduce clock cycles and achieve

higher bandwidth

Disadvantages

■ Requires manual integration of system modules

■ Cannot easily use existing SOPC Builder peripherals

■ Requires a register transfer level (RTL) file for each instantiation

■ Requires significant knowledge of the PCI bus protocol

Compliance
Summary

The MegaCore functions are compliant with the requirements specified in
the PCI SIG PCI Local Bus Specification, Revision 3.0 and Compliance
Checklist, Revision 3.0.

To ensure PCI compliance, Altera has performed extensive validation of
the PCI MegaCore functions. Validation includes both simulation and
hardware testing. The following simulations are covered by the
validation suite for the PCI MegaCore functions:

■ PCI-SIG checklist simulations

■ Applicable operating rules in Appendix C of the PCI Local Bus

Specification, Revision 3.0, including:

● Basic protocol

● Signal stability

● Master and target signals

● Data phases

● Arbitration

● Latency

● Device selection

● Parity

■ Local-side interface functionality

■ Corner cases of the PCI and local-side interface, such as random wait

state insertion

In addition to simulation, Altera performed extensive hardware testing
on the functions to ensure robustness and PCI compliance. The test
platforms include the Agilent E2928A PCI Bus Exerciser and Analyzer, an
Altera PCI development board with a device configured with a PCI
MegaCore function and a reference design, and PCI bus agents such as a

10 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

About PCI Compiler

host bridge, Ethernet network adapter, and video card. The Altera PCI
MegaCore functions were tested on the Stratix EP1S25F1020C5 and
EP1S60F1020C6 devices. Hardware testing ensures that the PCI
MegaCore functions operate flawlessly under the most stringent
conditions.

During hardware testing with the Agilent E2928A PCI Bus Exerciser and
Analyzer, various tests were performed to guarantee robustness and
strict compliance. These tests included the following:

■ Memory read/write

■ I/O read/write

■ Configuration read/write

The tests generate random transaction types and parameters at the PCI
and local sides. The Agilent E2928A PCI Bus Exerciser and Analyzer
simulated random behavior on the PCI bus by randomizing transactions
with variable parameters such as the following:

■ Bus commands

■ Burst length

■ Data types

■ Wait states

■ Terminations

■ Error conditions

The local side also emulated a variety of test conditions in which the PCI
MegaCore functions experienced random wait states and terminations.
During the tests, the Agilent E2928A PCI Bus Exerciser and Analyzer also
acted as a PCI protocol and data integrity checker as well as a logic
analyzer to aid in debugging. This testing ensures that the functions
operate under the most stringent conditions in your system.

f For more information on the Agilent E2928A PCI Bus Exerciser and

Analyzer, refer to the Agilent website at www.agilent.com.

Performance

This section lists the speed and approximate resource utilization of the
PCI MegaCore functions in supported Altera device families.

and Resource
Utilization

Altera Corporation User Guide Version 11.1 11
October 2011

PCI Compiler with MegaWizard Plug-in Manager Flow

The speed and resource utilization estimates are based on a PCI
MegaCore function using one BAR that reserves 1 MByte of memory.
Implementing additional BARs generates additional logic in the PCI

Performance and Resource Utilization

MegaCore function. Using different parameter options may result in
additional logic generated within the function. Results were generated
using the Quartus II software version 11.1.

Ta bl e 4 shows PCI MegaCore function resource utilization and

performance data for Stratix II devices.

Table 4. PCI MegaCore Function Performance in Stratix II Devices (1)

PCI Function

pci_mt64

pci_t64

pci_mt32

pci_t32

Notes to Ta b l e 4:

(1) This data was obtained by compiling each of the PCI MegaCore functions

(parameterized to use one BAR that reserves 1 MByte of memory) in the Stratix II
EP2S60F1020C5 device.

(2) The Utilization for Stratix II devices is based on the number of adaptive look-up

tables (ALUTs) used for the design as reported by the Quartus II software.

Utilization

(ALUTs) (2)

1,083 89 > 67

714 87 > 67
754 50 > 67
448 48 > 67

I/O Pins

f

MAX

(MHz)

Ta bl e 5 shows PCI MegaCore function resource utilization and

performance for Stratix, Stratix GX, and Cyclone devices.

Table 5. PCI MegaCore Function Performance in Stratix, Stratix GX &
Cyclone Devices (1)

PCI Function

pci_mt64

pci_t64

pci_mt32

pci_t32

Logic Elements

(LEs)

1,378 89 > 67

966 87 > 67

1007 50 > 67

661 48 > 67

I/O Pins

f

MAX

(MHz)

Note to Ta b l e 5:

(1) The PCI MegaCore functions use approximately the same number of LEs for the

Stratix, Stratix GX, and Cyclone device families. This data was obtained by
compiling each of the PCI MegaCore functions (parameterized to use one BAR
that reserves 1 MByte of memory) in the Stratix EP1S60F1020C6 device.

12 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

About PCI Compiler

Ta bl e 6 shows PCI MegaCore function resource utilization and

performance data for Cyclone II devices.

Table 6. PCI MegaCore Function Performance in Cyclone II Devices (1)

PCI Function

pci_mt64

pci_t64

pci_mt32

pci_t32

Note to Ta b l e 6:

(1) This data was obtained by compiling each of the PCI MegaCore functions

(parameterized to use one BAR that reserves 1 MByte of memory) in the
Cyclone II EP2C35F672C7 device.

Logic Elements

(LEs)

1,219 89 > 67

778 87 > 67
847 50 > 67
504 48 > 67

I/O Pins

f

MAX

(MHz)

Ta bl e 7 shows PCI MegaCore function resource utilization and

performance for MAX II devices.

Table 7. PCI MegaCore Function Performance in MAX II Devices (1), (2)

PCI Function

pci_mt32

pci_t32

Notes to Ta b l e 7:

(1) This data was obtained by compiling each of the PCI MegaCore functions

(parameterized to use one BAR that reserves 1 MByte of memory) in the MAX II
EPM2210F324C3 device.

(2) pci_mt64 and pci_t64 MegaCore functions are not supported in MAX II

devices.

Logic Elements

(LEs)

789 50 > 67
455 48 > 67

I/O Pins

f

MAX

(MHz)

PCI Compiler with SOPC Builder Flow

The speed and resource utilization estimates are for the supported
devices when operating in the PCI Target-Only, PCI Master/Target, and
PCI Host-Bridge device modes for each of the application-specific
performance settings.

1 Performance results will vary depending on the user-specified

parameters that are built into the system module.

Altera Corporation User Guide Version 11.1 13
October 2011

Performance and Resource Utilization

Ta bl e 8 lists memory utilization and performance data for Stratix II

devices.

Table 8. Memory Utilization & Performance Data for Stratix II Devices (4)

Performance Setting

as: (1)

PCI

Device

Mode

PCI
Target­Only

PCI
Master/
Target

Notes to Ta b l e 8:

(1) Min = Single-cycle transactions

Ty pi ca l = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads

(2) The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as

reported by the Quartus II software.

(3) In some compilations one M512 block was used, but it is not counted.
(4) The data was obtained by performing compilations on a Stratix II EP2S60F1020C5 device. Each of the device types

was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.

PCI Target

Min N/A 543 0 48 767 0 87 >67
Typical N/A 886 4 48 1,165 6 87 >67
Max N/A 1,240 4 48 1,556 68 87 >67
Min Typical 1,726 6 50 2,393 9 89 >67
Typical Typical 1,953 8 50 2,729 123 89 >67
Max Typical 2,321 8 50 3,114 12 89 >67
Min Max 2,532 9 50 3,665 15 89 >67
Typical Max 2,753 11 50 3,989 18 89 >67
Max Max 3,149 11 50 4,350 18 89 >67

PCI

Master

32-Bit PCI Interface 64-Bit PCI Interface

M4K

Utilization

ALUTs(2)

Memory

Blocks

I/O

Pins

Utilization

ALUTs(2)

Memory

(3)

M4K

Blocks

(3)

I/O

Pins

PCI

f

MAX

(MHz)

14 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

Ta bl e 9 lists memory utilization and performance data for Cyclone II

devices.

Table 9. Memory Utilization & Performance Data for Cyclone II Devices (2)

About PCI Compiler

Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface

I/O

PCI

f

MAX

(MHz)

PCI

Device

Mode

PCI Target PCI Master

Logic

Elements

(LEs)

PCI
Target­Only

PCI
Master/
Target

Notes to Ta b l e 9:

(1) Min = Single-cycle transactions

(2) The data was obtained by performing compilations on a Cyclone II EP2C35F672C7 device. Each of the device types

Min N/A 547 0 48 1,114 0 87 >67
Typical N/A 1,113 4 48 1,565 6 87 >67
Max N/A 1,605 4 48 2,051 6 87 >67
Min Typical 2,117 7 50 3,075 9 89 >67
Typical Typical 2,319 9 50 3,391 13 89 >67
Max Typical 2,806 9 50 3,915 13 89 >67
Min Max 3,096 7 50 4,655 9 89 >67
Typical Max 3,328 9 50 4,939 13 89 >67
Max Max 3,806 9 50 5,454 13 89 >67

Ty pi ca l = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads

was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.

M4K

Memory

Blocks

I/O

Pins

Logic

Elements

(LEs)

M4K

Memory

Blocks

Pins

Ta bl e 10 lists memory utilization and performance data for Stratix,

Stratix GX, and Cyclone devices.

Table 10. Memory Utilization & Performance Data for Stratix, Stratix GX & Cyclone Devices (3) (Part 1
of 2)

Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface

I/O

PCI

f

MAX

(MHz)

PCI

Device

Mode

PCI Target PCI Master

Logic

Elements

(LEs)

PCI
Target­Only

Altera Corporation User Guide Version 11.1 15
October 2011

Min N/A 852 0 48 1,186 0 87 >67
Typical N/A 1,460 4 48 1,949 6 87 >67
Max N/A 1,940 4 48 2,442 6 87 >67

M512

Memory

Blocks

(2)

I/O

Pins

Logic

Elements

(LEs)

M512

Memory

Blocks

(2)

Pins

Performance and Resource Utilization

Table 10. Memory Utilization & Performance Data for Stratix, Stratix GX & Cyclone Devices (3) (Part 2
of 2)

Performance Setting as: (1) 32-Bit PCI Interface 64-Bit PCI Interface

I/O

PCI

f

MAX

(MHz)

PCI

Device

Mode

PCI Target PCI Master

Logic

Elements

(LEs)

PCI
Master/
Target

Notes to Ta b l e 10 :

(1) Min = Single-cycle transactions

(2) In Cyclone devices, memory is implemented in M4K blocks, not M512 blocks.
(3) The data was obtained by performing compilations on a Cyclone EP1C20F400C7 device. Each of the device types

Min Typical 2,715 7 50 3,668 10 89 >67
Typical Typical 3,053 9 50 4,187 14 89 >67
Max Typical 3,540 9 50 4,682 14 89 >67
Min Max 3,728 10 50 5,138 16 89 >67
Typical Max 4,059 12 50 5,634 20 89 >67
Max Max 4,788 14 50 6,696 22 89 >67

Ty pi ca l = Burst transactions with a single pending read
Max = Burst transactions with multiple pending reads

was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI
Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side.

M512

Memory

Blocks

(2)

I/O

Pins

Logic

Elements

(LEs)

M512

Memory

Blocks

(2)

Pins

Ta bl e 11 lists memory utilization and performance data for MAX II

devices.

1 MAX II devices only support the PCI Target-Only peripheral

and the single-cycle performance setting.

Table 11. Memory Utilization & Performance Data for MAX II Devices (2)

Performance Setting as: (1) 32-Bit PCI Interface

PCI

Device

Mode

PCI
Target-Only

Notes to Ta b l e 11 :

(1) Min = Single-cycle transactions
(2) The data was obtained by performing compilations on a MAX II EPM2210F324C3 device. The device type was

parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side.

16 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011

PCI Target PCI Master

Min N/A 770 0 48 >67

Logic

Elements

(LEs)

Memory

Blocks

I/O Pins

PCI f

(MHz)

MAX

About PCI Compiler

Installation and Licensing

f For system requirements and installation instructions, refer to Altera

The User Guide is part of the MegaCore IP Library, which is distributed
with the Quartus II software and downloadable from the Altera website,

www.altera.com.

Software Installation and Licensing.

Figure 3 shows the directory structure after you install the PCI Compiler

User Guide, where <path> is the installation directory. The default
installation directory on Windows is c:\altera\<version>; on Linux it is
/opt/altera<version>.

Altera Corporation User Guide Version 11.1 17
October 2011

Installation and Licensing

Figure 3. Directory Structure

<path>

Installation directory.

ip

Contains the Altera MegaCore IP Library and third-party IP cores.

altera

Contains the Altera MegaCore IP Library.

common
Contains shared components.

ip_toolbench

Contains common IP Toolbench files.

pci_compiler

Contains the PCI Compiler files.

const_files

Contains constraint files that include all necessary assignments to meet your PCI timing requirements for
all supported Altera device families and development kits.

lib

Contains encrypted lower-level design files and other support files.
On Linux systems, you must add this directory as a user library in the Quartus II software.

megawizard_flow

Contains the files that are specific for PCI Compiler with MegaWizard flow.

sopc_flow

Contains the files that are specific for PCI Compiler with SOPC Builder.

ip_toolbench

Contains the necessary files for the parameterization wizard.

sopc_builder

Contains the necessary files for the SOPC Builder GUI. For Linux, this directory must be
added to the Component/Kit Library search path by choosing SOPC Builder Setup (File menu).

inc

Contains a header file that can be used in PCI Compiler with SOPC Builder flow. The header
file contains macros to access control and status registers inside the PCI-Avalon bridge.

qexamples

Contains example Quartus II projects and simulation waveforms for each of the PCI MegaCore functions.

ref_designs

Contains reference designs for common functions implemented with the PCI MegaCore functions.

testbench

Contains Verilog HDL and VHDL testbenches for simulating designs.

example

Contains example Quartus II projects using SOPC Builder.

testbench

Contains the Verilog HDL and VHDL testbenches for simulating designs that include the PCI-Avalon bridge.

18 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011