ALTERA PCG-01013-1.4 User Manual

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guidelines

The use of the pin connection guidelines for any particular desi gn should be verified for device operation, wit h the datasheet and Altera.

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Pin Connection Guidelines Agreement © 2012 Altera C orporation. All rights reserved.

Preliminary PCG-01013-1.4

© 2012 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized A ltera logo, speci fic device designat ions, and all other words and logos that are identified
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The pin connection guidel ines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a s pecification.

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®

programmable logic device-

Disclaimer Page 1 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

CLK[0:23][p:n] I/O, Clock

Dedicated positive and negative clock
input pins that can also be used for data
inputs. OCT Rd is supported on these
pins.

When you use the single-ended I/O
standard, only the CLK[0:23]p pins serve
as the dedicated input pins to the PLL.

When you do not use these pins, Altera recommends tying them to GND or leave them unconnected. If unconnected, use the Quartus II

FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUT0,

I/O, Clock

These pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias

FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUT1,

I/O, Clock

These pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias

FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUT2,

I/O, Clock

These pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias
FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUT3,

I/O, Clock

These pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias

MSEL[0:4] Input

Use these pins to set the configuration
scheme and POR delay.

These pins have an internal 25-kΩ pull-

down that is always active.

When you use these pins, tie them directly to VCCPGM or GND to get the combination for the configuration scheme as specified in the

AS_DATA0 / ASDO / DATA[0] Bidirectional

In a passive serial (PS) or fast passive
parallel (FPP) configuration scheme,
DATA[0] is a dedicated input data pin.

In an active serial (AS) x1 and AS x4
configuration schemes, AS_DATA0 and
ASDO are dedicated bidirectional data
pins.

When you do not use this pin, Altera recommends leaving the pin unconnected.

AS_DATA[1:3 ] / DATA[1:3] Bidirectional

In an AS configuration scheme,
AS_DATA[1:3] pins are used.

In an FPP x8 or FPP x16 configuration
scheme, the DATA[1:3] pins are used.

When you do not use this pin, Altera recommends leaving the pin unconnected.

nCSO/ DATA[4] Bidirectional

In an AS configuration scheme, the
nCSO pin is used. nCSO drives the
control signal from the Arria V device to
the EPCS or EPCQ device in the AS
configuration scheme.

In an FPP configuration scheme, the
DATA4 pin is used.

When you are not programming the device in the AS configuration scheme, the nCSO pin is not used. When you do not use this pin as an

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

Dual purpose I/O pins that can be used
Dual purpose I/O pins that can be used

one differential clock output pair or single

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Clock and PLL Pins

FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUTp,
FPLL_[BL,BC,BR,TL,TC,TR]_FB0

FPLL_[BL,BC,BR,TL,TC,TR]_CLKOUTn

FPLL_[BL,BC,BR,TL,TC,TR]_FBp,
FPLL_[BL,BC,BR,TL,TC,TR]_FB1

FPLL_[BL,BC,BR,TL,TC,TR]_FBn

Dedicated Configuration/JTAG Pins

Name

Pin Type (1st and

2nd Function)

Pin Description Connection Guidelines

as two single-ended clock output pins ,

ended feedback input pin.

as two single-ended outputs, differential
external feedback input pin or single
ended feedback input pin.

software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as
outputs driving GND.

these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

"Configuration, Design Security, and Remote System Upgrades in Arria V Devices" chapter in the Arria V Handbook.
These pins are not used in the JTAG configuration scheme. Tie the MSEL pins to GND if you are using the JTAG configuration scheme. Use
only MSEL pin settings defined in the Arria V device datasheet.

output pin, Altera recommends leaving the pin unconnected.

Pin Connection Guidelines Page 2 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

nCE Input

nCE is an active-low chip enable pin.
When nCE is low, the device is enabled.
When nCE is high, the device is
disabled.

In a multi-device configuration, the nCE pin of the first device is tied low while its nCEO pin drives the nCE pin of the next device in the chain.

nCONFIG Input

Pulling this pin low during configuration
and user mode causes the Arria V
device to lose its configuration data,
enter a reset state, and tri-states all I/O
pins.
A low-to-high logic initiates a
reconfiguration.

When you use the nCONFIG pin in a passive configuration scheme, connect the pin directly to the configuration controller.

CONF_DONE

Bidirectional

As a status output, the CONF_DONE pin
drives low before and during
configuration. After all configuration data
is received without error and the
initialization cycle starts, the
CONF_DONE pin is released.

As a status input, the CONF_DONE pin
goes high after all data is received. Then
the device initializes and enters user
mode.

This pin is not available as a user I/O
pin.

Connect an external 10-kΩ pull-up resistor to VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the

nCEO

I/O, Output

Dual-purpose open-drain output pin. This
pin drives low when device configuration
completes.

During multi-device configuration, this pin feeds the nCE pin of the next device in the chain. If this pin is not feeding the nCE pin of the next

nSTATUS

Bidirectional

The Arria V device drives the nSTATUS
pin low immediately after power-up and
releases it after the Arria V device exits
power-on reset (POR).

As a status output, the nSTATUS pin is
pulled low to indicate an error during
configuration.

As a status input, the device enters an
error state when the nSTATUS pin is
driven low by an external source during
configuration or initialization.

This pin is not available as a user I/O
pin.

Connect an external 10-kΩ pull-up resistor to VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Name

Pin Type (1st and

2nd Function)

(open-drain)

(open-drain)

(open-drain)

Pin Description Connection Guidelines

In a single-device configuration and JTAG programming, connect the nCE pin to GND.

When you use the nCONFIG pin in an AS configuration scheme, connect the pin through a 10-kΩ resis tor tied to VCCPGM.

When you do not use the nCONFIG pin, connect the pin directly or through a 10-kΩ res istor to VCCPGM.

During JTAG programming, the nCONFIG status is ignored.

device and the external host.

device, you can use this pin as a regular I/O pin.
In a single-device configuration, use this pin as a regular I/O pin. During single-device configuration, you may leave this pin floating. Connect

this pin to an external 10-kΩ pull-up resistor to VCCPGM.

device and the external host.

Pin Connection Guidelines Page 3 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

TCK Input

JTAG test clock input pin that clock input
to the boundary-scan testing (BST)
circuitry. Some operations occur at the
rising edge, while others occur at the
falling edge.
It is expected that the clock input
waveform have a nominal 50% duty
cycle.

This pin has an internal 25-kΩ pull-down

that is always active.

Connect this pin to a 1-kΩ pull-down resistor to GND.

TMS Input

JTAG test mode select input pin that
provides the control signal to determine
the transitions of the test access port
(TAP) controller state machine.

The TMS pin is evaluated on the rising
edge of the TCK pin. Transitions in the
state machine occur on the falling edge
of the TCK after the signal is applied to
the TMS pin.

This pin has an internal 25-kΩ pull-up

that is always active.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to the VCCPD in the dedicated I/O bank which the JTAG pin resides.

TDI Input

JTAG test data input pin for instructions
as well as test and programming data.
Data is shifted in on the rising edge of
the TCK pin.

This pin has an internal 25-kΩ pull-up

that is always active.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to VCCPD in the dedicated IO bank which the JTAG pin resides.

TDO Output

JTAG test data output pin for instructions
as well as test and programming data.
Data is shifted out on the falling edge of
the TCK pin. This pin is tri-stated if the
data is not being shifted out of the
device.

To disable the JTAG circuitry, leave the TDO pin unconnected.
In cases where the TDO pin uses VCCPD = 2.5 V to drive a 3.3 V JTAG interface, there may be leakage current in the TDI input buffer of the

Optional/Dual-Purpose Configuration

DCLK

Input (PS, FPP)

Dedicated bidirectional clock pin.

In the PS and FPP configuration
schemes, the DCLK pin is the clock input
used to clock configuration data from an
external source into the Arria V device.

In the AS configuration scheme, the
DCLK pin is an output clock to clock the
EPCS or EPCQ device.

Do not leave this pin floating. Drive this pin either high or low.

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Name

Pin Type (1st and

2nd Function)

Pin Description Connection Guidelines

To disable the JTAG circuitry, connect the TMS pin to VCCPD using a 1-kΩ resistor.

To disable the JTAG circuitry, connect the TDI pin to VCCPD using a 1-kΩ resistor.

interfacing devices. An external pull-up resistor tied to 3.3 V on their TDI pin may be used to eliminate the leakage current if needed.

Output (AS)

Pin Connection Guidelines Page 4 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

CRC_ERROR

I/O, Output

Optional output pin. This pin is an open­drain output pin by default and requires a

10-kΩ pull-up resistor. Active high signal

that indicates that the error detection
circuitry has detected errors in the
configuration SRAM bits. This pin is
optional and is used when the CRC error
detection circuitry is enabled.

When you use the dedicated CRC_ERROR pin configured as an open-dr ain output, connect this pin to an external 10-kΩ pull-up resistor to

DEV_CLRn I/O, Input

Optional input pin that allows you to
override all clears on all the device
registers. When this pin is driven low, all
registers are cleared. When this pin is
driven high (VCCPGM), all registers
behave as programmed.

When you do not use the dedicated input DEV_CLRn pin, and when this pin is not used as an I/O pin, Altera recommends connecting this

DEV_OE I/O, Input

Optional input pin that allows you to
override all tri-states on the device.
When this pin is driven low, all I/O pins
are tri-stated. When this pin is driven
high (VCCPGM), all I/O pins behave as
programmed.

When you do not use the dedicated input DEV_OE pin, and when this pin is not used as an I/O pin, Altera recommends connecting this pin

DATA[5:15] I/O, Input

Dual-purpose configuration data input
pins. These pins are required for the
FPP configuration scheme. Use DATA
[5:7] pins for FPP x8, DATA [5:15] pins
for FPP x16.
You can use the pins that are not
required for configuration as regular I/O
pins.

When you do not use the DATA[5:15] input pins, and when these pins are not used as I/O pins, Altera recommends leaving these pins

INIT_DONE

I/O, Output

This is a dual-purpose pin and can be
used as an I/O pin when not enabled as
an INIT_DONE pin in the Quartus II
software.
When this pin is enabled, a transition
from low to high on the pin indicates that
the device has entered user mode. If the
INIT_DONE output pin option is enabled
in the Quartus II software, the
INIT_DONE pin cannot be used as a
user I/O pin after configuration.

When you use the dedicated INIT_DONE pin configured as an open-drain output pin, connect this pin to an external 10-kΩ pull-up res istor to

CLKUSR I/O, Input

Optional user-supplied clock input.
Synchronizes the initialization of one or
more devices. If this pin is not enabled
for use as a user-supplied configuration
clock, it can be used as a user I/O pin.

When you do not use the CLKUSR pin as a configuration clock input pin, and when the pin is not used as an I/O pin, Altera recommends

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Name

Pin Type (1st and

2nd Function)

(open-drain)

(open-drain)

Pin Description Connection Guidelines

VCCPGM.
When you do not use the dedicated CRC_ERROR configured as an open-drain output, and when this pin is not used as an I/O pin, connect
this pin as defined in the Quartus II software.

pin to GND.

to GND.

unconnected.

VCCPGM.
In Active Serial (AS) multi-device configuration mode, Altera recommends that the INIT_DONE output pin option is enabled in the Quartus II
software for devices in the configuration chain. Do not tie INIT_DONE pins together between master and slave devices. Monitor the
INIT_DONE status for each device to ensure successful transition into user-mode.
When you do not use the dedicated INIT_DONE pin configured as open-drain output pin, and when this pin is not used as an I/O pin, Altera
recommends connecting this pin as defined in the Quartus II software.

connecting this pin to GND.

Pin Connection Guidelines Page 5 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

CvP_CONFDONE

I/O, Output

The CVP_CONFDONE pin is driven low
during configuration. When Configuration
via Protocol (CvP) is complete, this
signal is released and is pulled high by
an external pull-up resistor. Status of this
pin is only valid if the CONF_DONE pin
is high.

When you use the dedicated CvP_CONFDO NE pin configured as an open-drain output pin, connect this pin to an external 10-kΩ pull-up

nPERST[L0,R0] I/O, Input

Dedicated fundamental reset pins. These
pins are only available when you use

them together with the PCI Express
(PCIe

When these pins are low, the
transceivers are in reset.

When these pins are high, the
transceivers are out of reset.

When these pins are not used as the
fundamental reset, these pins may be
used as user I/O pins.

Connect these pins as defined in the Quartus II software.

PR_REQUEST I/O, Input

Partial reconfiguration request pin. Drive
this pin high to start partial
reconfiguration. Drive this pin low to end
reconfiguration.
This pin can only be used in partial
reconfiguration using the external host
mode in the FPP x16 configuration
scheme.

When you do not use the dedicated input PR_REQUEST pin, and when this pin is not used as an I/O pin, Altera recommends connecting
PR_READY

I/O, Output or Output

The partial reconfiguration ready pin is
driven low until the device is ready to
begin partial reconfiguration. When the
device is ready to start reconfiguration,
this signal is released and is pulled high
by an external pull-up resistor.

When you use the dedicated PR_READY pin configured as an open-drain output pin, connect this pin to an external 10- kΩ pull-up resistor to

PR_ERROR

I/O, Output or Output

The partial reconfiguration error pin is
driven low during partial reconfiguration
unless the device detects an error. If an
error is detected, this signal is released
and pulled high by an external pull-up
resistor.

When you use the dedicated PR_ERROR pin configured as an open-drain output pin, c onnect this pin to an external 10-kΩ pull-up resistor to

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Partial Reconfiguration Pins

Name

Pin Type (1st and

2nd Function)

(open-drain)

(open-drain)

Pin Description Connection Guidelines

resistor to VCCPGM.
When you do not use the dedicated CvP_CONFDONE pin configured as open-drain output pin, and when this pin is not used as an I/O pin,
Altera recommends connecting this pin as defined in the Quartus II software.

®

) hard IP.

®

this pin to GND.

VCCPGM.
When you do not use the dedicated PR_READY pin configured as open-drain output pin, and when this pin is not used as an I/O pin, Altera
recommends connecting this pin as defined in the Quartus II software.

(open-drain)

VCCPGM.
When you do not use the dedicated PR_ERROR pin configured as open-drain output pin, and when this pin is not used as an I/O pin, Altera
recommends connecting this pin as defined in the Quartus II software.

Pin Connection Guidelines Page 6 of 23

PCG-01013-1.4
Copyright © 2012 Altera Corp.

Arria® V Device Family Pin Connection Guide lines

Altera recommends that you create a Quartus® II design, enter your device I/O assignments, and compile the design. The Quartus II software will check your pin connections according to I /O assignment and placement rules.

PR_DONE

I/O, Output or Output

The partial reconfiguration done pin is
driven low until the partial reconfiguration
is complete. When the reconfiguration is
complete, this signal is released and is
pulled high by an external pull-up
resistor.

When you use the dedicated PR_DONE pin configured as an open-drain output pin, connec t this pin to an external 10-kΩ pull-up resistor to

DIFFIO_RX_[B,T][#:#]p,

I/O, RX channel

These are true LVDS receiver channels
on column I/O banks. Pins with a "p"
suffix carry the positive signal for the
differential channel. Pins with an "n"
suffix carry the negative signal for the
differential channel. If not used for
differential signaling, these pins are
available as user I/O pins. OCT Rd is
supported on all DIFFIO_RX pins.

Connect unused pins as defined in the Quartus II software.

DIFFIO_TX_[B,T][#:#]p,

I/O, TX channel

These are true LVDS transmitter
channels on column I/O banks. Pins with
a "p" suffix carry the positive signal for
the differential channel. Pins with an "n"
suffix carry the negative signal for the
differential channel. If not used for
differential signaling, these pins are
available as user I/O pins.

Connect unused pins as defined in the Quartus II software.

DIFFOUT_[B,T][#:#]p,

I/O, TX channel

These are emulated LVDS output
channels. All the user I/Os, including
I/Os with true LVDS input buffers, can be
configured as emulated LVDS output
buffers. External resistor network is
needed for emulated LVDS output
buffers.

Pins with a "p" suffix carry the positive
signal for the differential channel. Pins
with an "n" suffix carry the negative
signal for the differential channel. If not
used for differential signaling, these pins
are available as user I/O pins

Connect unused pins as defined in the Quartus II software.

DQS[#][B,T,R] I/O, bidirectional

Optional data strobe signal for use in
external memory interfacing. These pins
drive to dedicated DQS phase shift
circuitry. The shifted DQS signal can
also drive to internal logic.

Connect unused pins as defined in the Quartus II software.

Preliminary PCG-01013-1.4

The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other f actors that are not fully described in this document or the device handbook.

Arria V (transceiver-based device) Pin

Differential I/O Pins

DIFFIO_RX_[B,T][#:#]n

DIFFIO_TX_[B,T][#:#]n

DIFFOUT_[B,T][#:#]n

Name

Pin Type (1st and

2nd Function)

(open-drain)

Pin Description Connection Guidelines

VCCPGM.
When you do not use the dedicated PR_DONE pin configured as open-drain output pin, and when this pin is not used as an I/O pin, Altera
recommends connecting this pin as defined in the Quartus II software.

External Memory Interface Pins

Pin Connection Guidelines Page 7 of 23