ALTERA PCG-01007-1.5 User Manual

Arria® II Device Family Pin Connection Guidelines

PCG-01007-1.5

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These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Disclaimer Page 1 of 16

Arria II GX Pin Name Arria II GZ Pin Name

Pin Type (1st and 2nd Function)

Pin Description Connection Guidelines

CLK[4:15]

Clock, Input Single ended clock input pin. Connect unused pins to GND.

DIFFCLK[0:5]p

Clock, Input

Clock input pin for differential clock input. OCT Rd is not supported.

Connect unused pins to GND.

DIFFCLK[0:5]n

Clock, Input

Negative clock input for differential clock input. OCT Rd is not supported

Connect unused pins to GND.

PLL_[1:4]_CLKOUT1p NA I/O, Clock

When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. See Note 15.

PLL_[1:4]_CLKOUT1n NA I/O, Clock

When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II Software. See Note 15.

PLL_[1,3]_CLKOUT[2:3]p NA I/O, Clock

When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. See Notes 9 and 15.

PLL_[1,3]_CLKOUT[2:3]n NA I/O, Clock

When not using this pin as a clock output, this pin may be used as a user I/O. When not using these pins, connect them as defined in Quartus II software. See Notes 9 and 15.

NA CLK[1,3,8,10]p Clock, Input

Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these

Connect unused pins to GND.

NA CLK[1,3,8,10]n Clock, Input

Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on

Connect unused pins to GND.

NA CLK[0,2,9,11]p I/O, Clock

These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins.

These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

NA CLK[0,2,9,11]n I/O, Clock

These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins.

NA CLK[4:7,12:15]p I/O, Clock

These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins.

NA CLK[4:7,12:15]n I/O, Clock

These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins.

NA PLL_[L1,L4,R1,R4]_CLKp Clock, Input

Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. OCT Rd is not supported on these pins.

Connect unused pins to GND.

NA PLL_[L1,L4,R1,R4]_CLKn Clock, Input

Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively. OCT Rd is not supported on these pins.

Connect unused pins to GND.

PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n

I/O, Clock

PLL_[L1, L2, L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p

I/O, Clock

NA PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 I/O, Clock

NA PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 I/O, Clock

NA PLL_[T1,T2,B1,B2]_CLKOUT[3,4] I/O, Clock

These pins can be used as I/O pins or two single-ended clock output pins.

NA PLL_[T1,T2,B1,B2]_CLKOUT0p I/O, Clock

NA PLL_[T1,T2,B1,B2]_CLKOUT0n I/O, Clock

Arria® II Device Family Pin Connection Guidelines

PCG-01007-1.5

You should create a Quartus® II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments and other factors that are not fully described in this document or the device handbook.

Clock and PLL Pins

PLL1 and PLL3 in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 support 6 clock I/O pins, configured either as 3 single ended I/Os or 3 differential I/O pairs.

PLL[1:4]_CLKOUT1 (except PLL1 and PLL3 in EP2AGX125 and EP2AGX260) supports 2 clock I/O pins, configured either as one single ended I/O or one differential I/O pair. PLL1 and PLL3 in EP2AGX125 and EP2AGX260 support 6 clock I/O pins, configured either as 3 single ended I/Os or 3 differential I/O pairs.

Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin.

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin.

Configuration/JTAG Pins (See Note 16)

Pin Connection Guidelines Page 2 of 16

Arria II GX Pin Name Arria II GZ Pin Name

Pin Type (1st and 2nd Function)

Pin Description Connection Guidelines

Arria® II Device Family Pin Connection Guidelines

PCG-01007-1.5

nIO_PULLUP nIO_PULLUP Input

Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[1:7], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high (1.5 V, 1.8 V, 2.5 V, 3.0 V, or (3.3 V, Arria II GX only) turns off the weak pull-up, while a logic low turns them on.

nIO-PULLUP can be tied directly to (VCCIO3C for Arria II GX only), (VCCPGM for Arria II GZ only) using a 1kΩ pull-up resistor, or tied directly to GND depending on the desired functionality. Refer to the description column.

MSEL[0:3] MSEL[0:3] Input

Configuration input pins that set the FPGA device configuration scheme.

These pins are internally connected through a 5-kΩ resistor to GND. Do not leave these pins floating. When these pins are unused connect them to GND. Depending on the configuration scheme used these pins should be tied to (VCCPD3C for Arria II GX only), (VCCPGM for Arria II GZ only) or GND. Refer to the "„Configuration, Design Security, and Remote System Upgrades" chapter in the Arria II GX Handbook. If only JTAG configuration is used, connect these pins to ground.

nCE nCE Input

Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled.

In multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE should be connected to GND.

nCONFIG nCONFIG Input

Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/Opins. Returning this pin toa logic high level will initiate reconfiguration.

If the configuration scheme uses an enhanced configuration device or EPC2, nCONFIG can be tied directly to the nINIT_CONF pin of the configuration device. If this pin is not used, it requires a connection directly

or through a 10-kΩ resistor to (VCCIO3C for Arria II GX only), (VCCPGM for Arria II GZ only).

CONF_DONE CONF_DONE

Bidirectional (open-drain)

This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin.

Connect this pin to a 10-kΩ pull-up resistor to an acceptable voltage for all devices in the chain which satisfies the input voltage of the receiving device. If internal pull-up resistors on the enhanced

configuration device are used, external 10-kΩ pull-up resistors should not be used on t his pin.

nCEO nCEO

I/O, Output (open-drain)

Output that drives low when device configuration is complete. This pin can be used as regular I/O if not used for device configuration.

When not using this pin, you can leave it unconnected. During multi-device configuration, this pin feeds the nCE pin of a subsequent device. In this case, tie the 10-kΩ pull-up resistor to an acceptable voltage for all devices in the chain which satisfies the input voltage of the receiving device. During single device configuration, this pin can be used as a regular I/O.

nSTATUS nSTATUS

Bidirectional (open-drain)

This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as an user I/O pin.

Connect this pin to a 10-kΩ pull-up resistor to an acceptable voltage for all devices in the chain which satisfies the input voltage of the receiving device. The OE and nCE pins of the enhanced configuration devices and EPC2 devices have optional internal programmable pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external 10-kΩ pull-up should not be used on these pins. When not using external configuration devices, connect this pin to an external 10-kΩ pull-up resistor to (VCCIO3C for Arria II GX only), (VCCPGM for Arria II GZ only).

TCK TCK Input Dedicated JTAG test clock input pin. Connect this pin to a 1-kΩ pull-down resis tor to GND.

TMS TMS Input Dedicated JTAG test mode select input pin.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to VCCIO for Arria II GX or VCCPD for Arria II GZ. To

disable the JTAG circuitry connect TMS t o logic high via a 1-kΩ resistor.

TDI TDI Input Dedicated JTAG test data input pin.

Connect this pin to a 1-kΩ - 10-kΩ pull-up resistor to VCCIO for Arria II GX or VCCPD for Arria II GZ. To

disable the JTAG circuitry connect TDI to logic high via a 1-kΩ resistor.

TDO TDO Output Dedicated JTAG test data output pin. The JTAG circuitry can be disabled by leaving TDO unconnected.

NA TRST Input

Dedicated active low JTAG test reset input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit.

Utilization of TRST is optional. When using this pin ensure that TMS is held high or TCK is static when

TRST is changed from low to high. If not using TRST, tie this pin to a 1-kΩ to 10-kΩ pull-up resis tor to

VCCPD. To disable the JTAG circuitry, tie this pin to GND.

NA PORSEL Input

Dedicated input which selects between a POR time of 4 -12 ms or 100 - 300 ms. A logic high (1.8V, 2.5V, 3.0V) selects a POR time of 4 -12 ms and a logic low selects POR time of 100 - 300 ms.

The PORSEL pin should be tied directly to VCCPGM or GND.

nCSO nCSO Output

Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device.

When not programming the device in AS mode nCSO is not used. Also, when this pin is not used as an output then it is recommended to leave the pin unconnected.

ASDO ASDO Output

Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data.

When not programming the device in AS mode ASDO is not used. Also, when this pin is not used as an output then it is recommended to leave the pin unconnected.

Pin Connection Guidelines Page 3 of 16

Arria II GX Pin Name Arria II GZ Pin Name

Pin Type (1st and 2nd Function)

Pin Description Connection Guidelines

Arria® II Device Family Pin Connection Guidelines

PCG-01007-1.5

DCLK DCLK

I/O (PS, FPP) Output (AS)

Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface.

Do not leave this pin floating. Drive this pin either high or low.

CRC_ERROR CRC_ERROR

I/O, Output (open-drain)

Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. This pin can be used as regular I/O if not used for CRC

When using this pin connect it to an external 10-kΩ pull-up resistor to an acceptable voltage for alldevices in the chain which satisfies the input voltage of the receiving device. When not using this pin, it can be left floating.

DEV_CLRn DEV_CLRn I/O, Input

Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed.

When the dedicated input DEV_CLRn is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground.

DEV_OE DEV_OE I/O, Input

Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the

When the dedicated input DEV_OE is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground.

DATA0 DATA0 Input

DATA[0] is a dedicated pin that is used for both the passive and active configuration modes

When the dedicated input for DATA[0] is not used on Arria II GX, then it is recommended to tie this pin to GND. For Arria II GZ, connect this pin as defined in the Quartus II software.

DATA[7:1] DATA[7:1] I/O, Input

Dual-purpose configuration input data pins. The DATA[7:0] pins can be used for byte-wide configuration. DATA[7:1] pins can also be used as user I/O pins after configuration, but not DATA0.

When the dedicated inputs for DATA[7:1] are not used and these pins are not used as an I/O thenconnect them as defined in Quartus. (See Note 15).

INIT_DONE INIT_DONE

I/O, Output (open-drain)

This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

CLKUSR CLKUSR I/O, Input

Optional user-supplied clock input. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as an user I/O pin.

If the CLKUSR pin is not used as a configuration clock input and the pin is not used as an I/O then it is recommended to connect this pin to ground.

DIFFIO_RX_[T,B,R][##]p, DIFFIO_RX_[T,B,R][##]n

DIFFIO_RX_[T,B,L,R][##]p, DIFFIO_RX_[T,B,L,R][##]n

I/O, RX channel

Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

For Arria II GX, these are true LVDS receiver channels with OCT Rd support.

For Arria II GZ, only DIFFIO_RX_[L,R]* pins are true LVDS receiver channels with OCT Rd support.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

DIFFIO_TX_[T,B,R][##]p, DIFFIO_TX_[T,B,R][##]n

DIFFIO_TX_[L,R][##]p, DIFFIO_TX_[L,R][##]n

I/O, TX channel

These are true LVDS transmitter channels. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

For Arria II GX if not used as true LVDS transmitter channels, these pins can be configured as true LVDS receiver channels without OCT Rd support (DIFFIN_[T,B,R][##][p,n]).

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

DIFFIN_[T,B,R][##]p, DIFFIN_[T,B,R][##]n

I/O, RX channel

These are true LVDS receiver channels without OCT Rd support. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used as true LVDS receiver channels without OCT Rd support, these pins can be configured as true LVDS transmitter channels (DIFFIO_TX_[T,B,R][##][p,n]). If not used for differential signaling, these pins are available as user I/O pin.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

Differential I/O Pins (See Note 12)

Pin Connection Guidelines Page 4 of 16

Arria II GX Pin Name Arria II GZ Pin Name

Pin Type (1st and 2nd Function)

Pin Description Connection Guidelines

Arria® II Device Family Pin Connection Guidelines

PCG-01007-1.5

DIFFOUT_[T,B,R][##]p, DIFFOUT_[T,B,R][##]n

DIFFOUT_[T,B,L,R][##]p, DIFFOUT_[T,B,L,R][##]n

I/O, TX channel

These are emulated LVDS output channels. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

On Arria II GX I/O banks there are true LVDS input buffers but no true LVDS output buffers. However, all user I/Os, including I/Os with true LVDS input buffers, (DIFFIO_RX_[T,B,R][##][p,n] , DIFFIN_[T,B,R][##][p,n]) can be configured as emulated LVDS output buffers.

On Arria II GZ column I/O banks thereare true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

DQS[##][T,B,R] DQS[##][T,B,L,R] I/O, DQS

Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

DQSn[##][T,B,R] DQSn[##][T,B,L,R] I/O, DQSn

Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software. See Note 11.

DQ[##][T,B,R] DQ[##][T,B,L,R] I/O, DQ

Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

CQ[##][T,B,R] CQ[##][T,B,L,R] DQS

Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software.

CQn[##][T,B,R] CQn[##][T,B,L,R] DQS

Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks.

When these IO pins are not used they can be tied to GND. Connect unused pins as defined in Quartus II software. See Note 11.

RUP[0:2] RUP[1:8]A I/O, Input

Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin.

When the device does not use this dedicated input for the external precision resistor or as an I/O it is recommended that the pin be connected to the VCCIO of the bank in which the RUP pin resides or GND. When using OCT tie these pins to the required banks VCCIO through either a 25 W or 50 W resistor, depending on the desired I/O standard. Refer to the Arria II GX handbook for the desired resistor value for the I/O standard used.

RDN[0:2] RDN[1:8]A I/O, Input

Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin.

When the device does not use this dedicated input for the external precision resistor or as an I/O it is recommended that the pin be connected to GND. When using OCT tie these pins to GND through either a 25 W or 50 W resistor depending on the desired I/O standard. Refer to the Arria II GX handbook for the desired resistor value for the I/O standard used.

DNU DNU Do Not Use Do Not Use (DNU). Do not connect to power, ground or any other signal. These pins must be left floating.

NC NC No Connect Do not drive signals into these pins.

When designing for device migration these pins may be connected to power, ground, or a signal trace depending on the pin assignment of the devices selected for migration. However, if device migration is not a concern leave these pins floating.

VCC VCC Power VCC supplies power to the core and periphery.

All VCC pins require a 0.9 V supply. Use the Arria II GX or Arria II GZ Early Power Estimator to determine the current requirements for VCC and other power supplies. To successfully power-up and exit POR, fully power VCC before VCCAUX begins to ramp. Decoupling for these pins depends on the design decoupling requirements of the specific board. See Notes 3, 6 and 17.

For Arria II GX, with a proper isolation filter VCCD_PLL may be sourced from the same regulator as VCC. To support the startup current as reported by the Early Power Estimator (EPE) for Arria II GX devices, fully power VCC before VCCCB begins to ramp.

For Arria II GZ, these pins may be tied to the same 0.9V plane as VCCHIP_L. With a proper isolation filter VCCD_PLL may be sourced from the same regulator as VCC.

Reference Pins

Supply Pins (See Note 8 and 17)

External Memory Interface Pins (See Note 12)

Pin Connection Guidelines Page 5 of 16

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