ALTERA PCG-01003-1.0 User Guide

Cyclone® III Device Family Pin Connection Guidelines

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PCG-01003-1.0

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specification.
The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Pin Type (1st, 2nd, &

Connect VCCD_PLL[1..4] pins together. VCCD_PLL supply to the chip should be

Cyclone® III Device Family Pin Connection Guidelines

PCG-01003-1.0 (Note 1)

Pin Name

VCCINT Power These are internal logic array voltage supply pins.

VCCIO[1..8] Power

VREFB[1..8]N[0..2] (Note 2) I/O

VCCA[1..4] (Note 3) Power

3rd Function) Pin Description Connection Guidelines

Supply and Reference Pins

These are I/O supply voltage pins for banks 1 through 8. Each
bank can support a different voltage level. VCCIO supplies
power to the input and output buffers for all I/O standards.
VCCIO powers up the JTAG pins (TCK, TMS, TDI and TDO)
and the following configuration pins: nCONFIG, DCLK,
DATA[15..0], nCE, nCEO, nWE, nRESET, nOE, FLASH_nCE,
nCSO and CLKUSR.

Input reference voltage for each I/O bank. If a bank uses a
voltage-referenced I/O standard, then these pins are used as
the voltage-reference pins for the bank. If voltage reference
I/O standards are not used in the bank, the VREF pins are
available as user I/O pins. All of the VREF pins within a bank
are shorted together.

Supply (analog) voltage for PLLs[1..4] and other analog
circuits in the device.

All VCCINT pins must be connected to 1.2V supply. Decoupling depends on the
design decoupling requirements of the specific board. See

Decoupling depends on the design decoupling requirements of the specific
board. See Note (8)

If VREF pins are not used, the designer should connect them to either the
VCCIO in the bank in which the pin resides or GND. Decoupling depends on the
design decoupling requirements of the specific board. See Note (8)

The designer must connect these pins to 2.5V, even if the PLL is not used.
These pins must be powered up and powered down at the same time. Connect
VCCA[1..4] pins together. VCCA supply to the chip should be isolated. See

Note(9) for details. See Note(10) for recommended decoupling.

Note (8)

VCCD_PLL[1..4] (Note 3) Power Supply (digital) voltage for PLLs[1..4].

Reference pins for on-chip termination (OCT) block in I/O

RUP[1..4] I/O, Input

RDN[1..4] I/O, Input

GND Ground Device ground pins. All GND pins should be connected to the board GND plane.

banks 2, 4, 5 and 7. The external precision resistor Rup must
be connected to the designated RUP pin within the same
bank. If not required, this pin is a regular I/O pin.

Reference pins for on-chip termination (OCT) block in I/O
banks 2, 4, 5 and 7. The external precision resistor Rdn must
be connected to the designated RDN pin within the same
bank. If not required, this pin is a regular I/O pin.

The designer must connect these pins to 1.2V, even if the PLL is not used.

isolated. See Note(9) for details. See Note (11) for recommended decoupling.

When the device does not use this dedicated input for the external precision
resistor or as an I/O, it is recommended that the pin be connected to VCCIO of
the bank in which the RUP pin resides.

When the device does not use this dedicated input for the external precision
resistor or as an I/O, it is recommended that the pin be connected to GND.

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Pin Type (1st, 2nd, &

Cyclone® III Device Family Pin Connection Guidelines

DCLK should not be left floating. In JTAG configuration and schemes that use an

modes, bit-wide configuration data is received through this pin.

After AP configuration, DATA[0] is a dedicated bidirectional pin

Depending on the configuration scheme used, these pins should be tied to VCCA

during user-mode will cause the FPGA to lose its configuration

If you are using PS configuration scheme with a download cable, connect this pin

PCG-01003-1.0 (Note 1)

Pin Name

GNDA[1..4] (Note 3) Ground Ground for PLLs[1..4] and other analog circuits in the device.

NC No Connect No Connect Do not connect these pins to any signal.

DCLK

DATA[0]

MSEL[3..0] Input

3rd Function) Pin Description Connection Guidelines

The designer should connect these pins to an isolated analog ground plane on
the board.

Dedicated Configuration/JTAG Pins

Dedicated configuration clock pin. In PS and FPP

Input (PS,FPP)
Output (AS,AP)

Input (PS,FPP,AS)
Bidirectional open drain
(AP)

configuration, DCLK is used to clock configuration data from
an external source into the Cyclone III device. In AS and AP
mode, DCLK is an output from the Cyclone III device that
provides timing for the configuration interface.

Dedicated configuration data input pin. In serial configuration

In AS mode, DATA[0] has an internal pull-up resistor that is
always active. After AS configuration, DATA[0] is a dedicated
input pin with optional user control. After PS or PP
configuration, DATA[0] is available as a user I/O pin and the
state of this pin depends on the Dual-Purpose Pin settings.

with optional user control.

Configuration input pins that set the Cyclone III device
configuration scheme. Some of the smaller devices or
package options do not support the AP flash programming
and do not have the MSEL[3] pin.

external host, designer should drive it high or low, whichever is more convenient
on the board. In AS and AP mode, the DCLK has an internal pull-up resistor
(typically 25-kOhm) that is always active.

If you are using a serial configuration device in AS configuration mode, you must
connect a 25-Ohm series resistor at the near end of the serial configuration
device for the DATA[0]. If DATA[0] is not used, it should be driven high or low,
whichever is more convenient on the board.

These pins are internally connected to 5-kOhm resistor to GND. Do not leave
these pins floating. W hen these pins are unused connect them to GND.

or GND. Refer to Chapter 10 of Cyclone III Handbook: Configuring Cyclone III
Devices. If only JTAG configuration is used, then connect these pins to GND.

nCE Input

nCONFIG Input

Dedicated active-low chip enable. When nCE is low, the
device is enabled. W hen nCE is high, the device is disabled.

Dedicated configuration control input. Pulling this pin low

data, enter a reset state & tri-state all I/O pins. Returning this
pin to a logic high level will initiate reconfiguration. The input
buffer on this pin supports hysteresis using Schmitt trigger
circuitry.

In multi-device configuration, nCE of the first device is tied low while its nCEO
pin drives the nCE of the next device in the chain. In single device configuration
and JTAG programming, nCE is tied low.

through a 10-kOhm resistor to VCCA. For other configuration schemes, if this pin
is not used, this pin must be connected directly or through a 10-kOhm resistor to
VCCIO.

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