Cyclone® III Device Family Pin Connection Guidelines
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PCG-01003-1.0
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The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a
specification.
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Page 2
Pin Type (1st, 2nd, &
Connect VCCD_PLL[1..4] pins together. VCCD_PLL supply to the chip should be
Cyclone® III Device Family Pin Connection Guidelines
PCG-01003-1.0 (Note 1)
Pin Name
VCCINT Power These are internal logic array voltage supply pins.
VCCIO[1..8] Power
VREFB[1..8]N[0..2] (Note 2) I/O
VCCA[1..4] (Note 3) Power
3rd Function) Pin Description Connection Guidelines
Supply and Reference Pins
These are I/O supply voltage pins for banks 1 through 8. Each
bank can support a different voltage level. VCCIO supplies
power to the input and output buffers for all I/O standards.
VCCIO powers up the JTAG pins (TCK, TMS, TDI and TDO)
and the following configuration pins: nCONFIG, DCLK,
DATA[15..0], nCE, nCEO, nWE, nRESET, nOE, FLASH_nCE,
nCSO and CLKUSR.
Input reference voltage for each I/O bank. If a bank uses a
voltage-referenced I/O standard, then these pins are used as
the voltage-reference pins for the bank. If voltage reference
I/O standards are not used in the bank, the VREF pins are
available as user I/O pins. All of the VREF pins within a bank
are shorted together.
Supply (analog) voltage for PLLs[1..4] and other analog
circuits in the device.
All VCCINT pins must be connected to 1.2V supply. Decoupling depends on the
design decoupling requirements of the specific board. See
Decoupling depends on the design decoupling requirements of the specific
board. See Note (8)
If VREF pins are not used, the designer should connect them to either the
VCCIO in the bank in which the pin resides or GND. Decoupling depends on the
design decoupling requirements of the specific board. See Note (8)
The designer must connect these pins to 2.5V, even if the PLL is not used.
These pins must be powered up and powered down at the same time. Connect
VCCA[1..4] pins together. VCCA supply to the chip should be isolated. See
Note(9) for details. See Note(10) for recommended decoupling.
Note (8)
VCCD_PLL[1..4] (Note 3) Power Supply (digital) voltage for PLLs[1..4].
Reference pins for on-chip termination (OCT) block in I/O
RUP[1..4] I/O, Input
RDN[1..4] I/O, Input
GND Ground Device ground pins. All GND pins should be connected to the board GND plane.
banks 2, 4, 5 and 7. The external precision resistor Rup must
be connected to the designated RUP pin within the same
bank. If not required, this pin is a regular I/O pin.
Reference pins for on-chip termination (OCT) block in I/O
banks 2, 4, 5 and 7. The external precision resistor Rdn must
be connected to the designated RDN pin within the same
bank. If not required, this pin is a regular I/O pin.
The designer must connect these pins to 1.2V, even if the PLL is not used.
isolated. See Note(9) for details. See Note (11) for recommended decoupling.
When the device does not use this dedicated input for the external precision
resistor or as an I/O, it is recommended that the pin be connected to VCCIO of
the bank in which the RUP pin resides.
When the device does not use this dedicated input for the external precision
resistor or as an I/O, it is recommended that the pin be connected to GND.
Page 3
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
DCLK should not be left floating. In JTAG configuration and schemes that use an
modes, bit-wide configuration data is received through this pin.
After AP configuration, DATA[0] is a dedicated bidirectional pin
Depending on the configuration scheme used, these pins should be tied to VCCA
during user-mode will cause the FPGA to lose its configuration
If you are using PS configuration scheme with a download cable, connect this pin
PCG-01003-1.0 (Note 1)
Pin Name
GNDA[1..4] (Note 3) Ground Ground for PLLs[1..4] and other analog circuits in the device.
NC No Connect No Connect Do not connect these pins to any signal.
DCLK
DATA[0]
MSEL[3..0] Input
3rd Function) Pin Description Connection Guidelines
The designer should connect these pins to an isolated analog ground plane on
the board.
Dedicated Configuration/JTAG Pins
Dedicated configuration clock pin. In PS and FPP
Input (PS,FPP)
Output (AS,AP)
Input (PS,FPP,AS)
Bidirectional open drain
(AP)
configuration, DCLK is used to clock configuration data from
an external source into the Cyclone III device. In AS and AP
mode, DCLK is an output from the Cyclone III device that
provides timing for the configuration interface.
Dedicated configuration data input pin. In serial configuration
In AS mode, DATA[0] has an internal pull-up resistor that is
always active. After AS configuration, DATA[0] is a dedicated
input pin with optional user control. After PS or PP
configuration, DATA[0] is available as a user I/O pin and the
state of this pin depends on the Dual-Purpose Pin settings.
with optional user control.
Configuration input pins that set the Cyclone III device
configuration scheme. Some of the smaller devices or
package options do not support the AP flash programming
and do not have the MSEL[3] pin.
external host, designer should drive it high or low, whichever is more convenient
on the board. In AS and AP mode, the DCLK has an internal pull-up resistor
(typically 25-kOhm) that is always active.
If you are using a serial configuration device in AS configuration mode, you must
connect a 25-Ohm series resistor at the near end of the serial configuration
device for the DATA[0]. If DATA[0] is not used, it should be driven high or low,
whichever is more convenient on the board.
These pins are internally connected to 5-kOhm resistor to GND. Do not leave
these pins floating. W hen these pins are unused connect them to GND.
or GND. Refer to Chapter 10 of Cyclone III Handbook: Configuring Cyclone III
Devices. If only JTAG configuration is used, then connect these pins to GND.
nCE Input
nCONFIG Input
Dedicated active-low chip enable. When nCE is low, the
device is enabled. W hen nCE is high, the device is disabled.
Dedicated configuration control input. Pulling this pin low
data, enter a reset state & tri-state all I/O pins. Returning this
pin to a logic high level will initiate reconfiguration. The input
buffer on this pin supports hysteresis using Schmitt trigger
circuitry.
In multi-device configuration, nCE of the first device is tied low while its nCEO
pin drives the nCE of the next device in the chain. In single device configuration
and JTAG programming, nCE is tied low.
through a 10-kOhm resistor to VCCA. For other configuration schemes, if this pin
is not used, this pin must be connected directly or through a 10-kOhm resistor to
VCCIO.
Page 4
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
This is a dedicated configuration status pin. As a status output,
This pin is not available as a user I/O pin. CONF_DONE should be pulled high by
nSTATUS low immediately after power-up and releases it after
Dedicated JTAG input pin. The JTAG circuitry can be disabled
PCG-01003-1.0 (Note 1)
Pin Name
CONF_DONE
nSTATUS
TCK Input
TMS Input
TDI Input
3rd Function) Pin Description Connection Guidelines
Bidirectional
(open-drain)
Bidirectional
(open-drain)
the CONF_DONE pin drives low before and during
configuration. Once all configuration data is received without
error and the initialization cycle starts, CONF_DONE is
released. As a status input, CONF_DONE goes high after all
data is received. Then the device initializes and enters user
mode.
This is a dedicated configuration status pin. The FPGA drives
POR time. As a status output, the nSTATUS is pulled low if an
error occurs during configuration. As a status input, the device
enters an error state when nSTATUS is driven low by an
external source during configuration or initialization.
Dedicated JTAG input pin. The JTAG circuitry can be disabled
by connecting TCK to GND.
by connecting TMS to VCC.
Dedicated JTAG input pin. The JTAG circuitry can be disabled
by connecting TDI to VCC.
an external 10-kΩ pull-up resistor.
This pin is not available as a user I/O pin. nSTATUS should be pulled high by an
external 10-kΩ pull-up resistor.
Connect this pin to a 1-kOhm resistor to GND.
When interfacing with 2.5V/3.0V/3.3V configuration voltage standards, connect
this pin through a 1-kOhm resistor to VCCA. Otherwise, connect this pin through
a 1-kOhm resistor to VCCIO. See Note (4).
When interfacing with 2.5V/3.0V/3.3V configuration voltage standards, connect
this pin through a 1-kOhm resistor to VCCA. Otherwise, connect this pin through
a 1-kOhm resistor to VCCIO. See Note (4).
TDO Output Dedicated JTAG output pin. The JTAG circuitry can be disabled by leaving TDO unconnected.
CLK[0,2,4,6,9,11,13,15],
DIFFCLK_[0..7]p (Note 5)
CLK[1,3,5,7,8,10,12,14],
DIFFCLK_[0..7]n (Note 5)
PLL[1..4]_CLKOUTp (Note 3) I/O, Output
Clock, Input
Clock, Input
Dedicated global clock input pins that can also be used for the
positive terminal inputs for differential global clock input or
user input pins.
Dedicated global clock input pins that can also be used for the
negative terminal inputs for differential global clock input or
user input pins.
Optional positive terminal for external clock outputs from PLL
[1..4]. These pins can only use the differential I/O standard if it
is being fed by a PLL output.
Clock and PLL Pins
Connect unused pins to GND. See Note (12).
Connect unused pins to GND. See Note (12).
Connect unused pins to GND. See Note (12).
Page 5
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
PLL[1..4]. These pins can only use the differential I/O standard
In PS configuration scheme, DATA[1] functions as user I/O pin
After AP configuration, DATA[1] is a dedicated bidirectional pin
PCG-01003-1.0 (Note 1)
Pin Name
PLL[1..4]_CLKOUTn (Note 3) I/O, Output
nCEO I/O, Output Output that drives low when device configuration is complete.
FLASH_nCE, nCSO I/O, Output
3rd Function) Pin Description Connection Guidelines
Optional negative terminal for external clock outputs from
if it is being fed by a PLL output.
Optional/Dual-Purpose Configuration Pins
This pin functions as FLASH_nCE in AP mode, and nCSO in
AS mode. This pin has an internal pull-up resistor that is
always active.
nCSO: Output control signal from the Cyclone III device to the
serial configuration device in AS mode that enables the
configuration device.
FLASH_nCE: Output control signal from the Cyclone III device
to the parallel flash in AP mode that enables the flash.
This pin functions as DATA[1] in PS, FPP and AP modes, and
as ASDO in AS mode.
Connect unused pins to GND. See Note (12).
During multi-device configuration, this pin feeds a subsequent device’s nCE pin
and must be pulled high to VCCIO by an external 10-kOhm pull-up resistor.
During single device configuration and for the last device in multi-device
configuration, this pin can be left floating or used as a user I/O after
configuration.
When not programming the device in AS mode, nCSO is not used. Similarly,
FLASH_nCE is not used when not programming the device in AP mode. If the
pin is not used as an I/O then it is recommended to leave the pin unconnected.
Input (FPP)
DATA[1], ASDO
Output (AS)
Bidirectional open-drain
(AP)
DATA[1]: Data input in non-AS mode. Byte-wide or word-wide
configuration data is presented to the target device on
DATA[7..0] or DATA[15..0] respectively.
during configuration, which means it is tri-stated.
After FPP configuration, DATA[1] is available as a user I/O pin
and the state of this pin depends on the Dual-Purpose Pin
settings.
with optional user control.
ASDO: Control signal from the Cyclone III device to the serial
configuration device in AS mode used to read out
configuration data. In AS mode, this ASDO pin has an internal
pull-up resistor that is always active. After AS configuration,
this pin is a dedicated output pin with optional user control.
Page 6
When not programming the device in AS or AP mode, this pin is available as a
user I/O pin. If the pin is not used as an I/O then it is recommended to leave the
pin unconnected.
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
pin low resets the
When not programming the device in AP mode, nWE is not used and is available
PCG-01003-1.0 (Note 1)
Pin Name
PADD[23..0] Output
nRESET Output
nAVD Output
nOE Output
nWE Output
RDY Input
CRC_ERROR I/O, Output
3rd Function) Pin Description Connection Guidelines
24-bit address bus from the Cyclone III device to the parallel
flash in AP mode.
Active-low reset output. Driving the nRESET
parallel flash.
Active-low address valid output. Driving the nAVD pin low
during read or write operation indicates to the parallel flash
that valid address is present on the PADD[23..0] address bus.
Active-low output enable to the parallel flash. Driving the nOE
pin low during read operation enables the parallel flash
outputs (DATA[15..0] and RDY).
Active-low write enable to the parallel flash. Driving the nWE
pin low during write operation indicates to the parallel flash
that data on the DATA[15..0] bus is valid.
Control signal (WAIT) from the parallel flash is connected to
this pin in the Cyclone III device to indicate when synchronous
data is ready on the data bus.
Active high signal that indicates that the error detection circuit
has detected errors in the configuration SRAM bits. This pin is
optional and is used when the CRC error detection circuit is
enabled.
When not programming the device in AP mode, these pins are available as user
I/O pins. If these pins are not used as I/Os, then it is recommended to leave
these pins unconnected.
When not programming the device in AP mode, nRESET is not used and is
available as a user I/O pin. If the pin is not used as an I/O then it is
recommended to leave the pin unconnected.
When not programming the device in AP mode, nAVD is not used and is
available as a user I/O pin. If the pin is not used as an I/O then it is
recommended to leave the pin unconnected.
When not programming the device in AP mode, nOE is not used and is available
as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave
the pin unconnected.
as a user I/O pin. If the pin is not used as an I/O then it is recommended to leave
the pin unconnected.
The current implementation for AP configuration ignores the RDY pin. However it
is highly recommended to connect this pin to the AP flash.
When the output for CRC_ERROR is not used and this pin is not used as an I/O
then it is recommended to leave the pin unconnected.
Optional chip-wide reset pin that allows you to override all
clears on all device registers. When this pin is driven low, all
DEV_CLRn
DEV_OE
I/O (when option off),
Input (when option on)
I/O (when option off),
Input (when option on)
registers are cleared; when this pin is driven high, all registers
behave as programmed. The DEV_CLRn pin does not affect
JTAG boundary-scan or programming operations. This pin is
enabled by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated;
when this pin is driven high, all I/O pins behave as defined in
the design. This pin is enabled by turning on the Enable
device-wide output enable (DEV_OE) option in the Quartus II
software.
When the input DEV_CLRn is not used and this pin is not used as an I/O then it
is recommended to tie this pin to VCCIO or GND.
When the input DEV_OE is not used and this pin is not used as an I/O then it is
recommended to tie this pin to VCCIO or GND.
Page 7
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
transition from low to high at the pin indicates when the device
user-supplied start-up clock (CLKUSR) option in the Quartus II
When these I/O pins are not used they can be tied to the VCCIO of the bank they
asynchronous clears, presets and clock enables. It can also be
used as optional data strobe signal for use in external memory
When these I/O pins are not used they can be tied to the VCCIO of the bank they
PCG-01003-1.0 (Note 1)
Pin Name
INIT_DONE
CLKUSR I/O, Input
DIFFIO_[L,R,T,B][0..61][n,p]
(Note 6)
DQS[0..5][L,R,T,B]/CQ[1,3,5][
L,R,T,B][#],DPCLK[0..11]
(Note 7)
3rd Function) Pin Description Connection Guidelines
I/O, Output
(open-drain)
I/O, TX/RX channel
I/O, DQS/CQ,DPCLK
This is a dual-purpose status pin and can be used as an I/O
pin when not enabled as INIT_DONE. W hen enabled, a
has entered user mode. If the INIT_DONE output is enabled,
the INIT_DONE pin cannot be used as a user I/O pin after
configuration. This pin is enabled by turning on the Enable
INIT_DONE output option in the Quartus II software.
Optional user-supplied clock input. Synchronizes the
initialization of one or more devices. If this pin is not enabled
for use as a user-supplied configuration clock, it can be used
as a user I/O pin. This pin is enabled by turning on the Enable
software.
Dual-Purpose Differential & External Memory Interface Pins
Dual-purpose differential transmitter/receiver channels. These
channels can be used for transmitting/receiving LVDS
compatible signals. Pins with a "p" suffix carry the positive
signal for the differential channel. Pins with an "n" suffix carry
the negative signal for the differential channel. If not used for
differential signaling, these pins are available as user I/O pins.
Dual-purpose DPCLK/DQS pins can connect to the global
clock network for high fan-out control signals such as clocks,
interfacing. These pins drive to dedicated DQS phase shift
circuitry, which allows fine tune of the phase shift for input
clocks or strobes to properly align clock edges needed to
capture data.
Connect this pin to a 10-kOhm resistor to VCCIO.
If the CLKUSR pin is not used as a configuration clock input and the pin is not
used as an I/O then it is recommended to connect this pin to GND.
reside in or GND. See Note (12).
reside in or GND. See Note (12).
Page 8
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
block at a time. The other pin can be used as general-purpose
When these I/O pins are not used they can be tied to the VCCIO of the bank they
When these I/O pins are not used they can be tied to the VCCIO of the bank they
When these I/O pins are not used they can be tied to the VCCIO of the bank they
Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.
PCG-01003-1.0 (Note 1)
Pin Name
DQS[0..5][L,R,T,B]/CQ[1,3,5][
L,R,T,B][#],CDPCLK[0..7]
(Note 7)
DQ[0..5][L,R,T,B] (Note 7) I/O, DQ Optional data signal for use in external memory interface.
DM[0..5][L,R,B,T][0..1]/BWS#
[0..5][L,R,T,B]
Notes:
(1) This pin connection guideline is created based on the largest Cyclone III device (EP3C120F780).
(2) EP3C5 and EP3C10 only have VREFB[1..8]N0.
(3) EP3C5 and EP3C10 only have PLL(1 & 2). EP3C16 and other larger densities have PLL (1,2,3 & 4).
(4) You must follow specific requirements when interfacing Cyclone III devices with 2.5V/3.0V/3.3V configuration voltage standards. All I/O inputs must maintain a maximum AC voltage of 4.1V. Refer
to Configuration and JTAG Pin I/O Requirements of Chapter 10 in Cyclone III Handbook: Configuring Cyclone III Devices.
(5) The number of dedicated global clocks for each device density is different. EP3C5 and EP3C10 support four dedicated clock pins on the left and right sides of the device, that can drive a total of 10
global clock networks. EP3C16 and other larger densities support four dedicated clock pins on each side of the device that can drive a total of 20 global clock networks.
3rd Function) Pin Description Connection Guidelines
Dual-purpose CDPCLK/DQS pins can connect to the global
clock network for high fan-out control signals such as clocks,
asynchronous clears, presets and clock enables. Only one of
the two CDPCLK in each corner can feed the clock control
I/O, DQS/CQ,CDPCLK
I/O, DM/BWS#
I/O pin. The CDPCLK signals incur more delay to the clock
block control because they are multiplexed before driving into
the clock block control. It can also be used as optional data
strobe signal for use in external memory interfacing. These
pins drive to dedicated DQS phase shift circuitry, which allows
fine tune of the phase shift for input clocks or strobes to
properly align clock edges needed to capture data.
The data mask pins are only required when writing to DDR
SDRAM and DDR2 SDRAM devices. QDRII SRAM devices
use the BWS signal to select the byte to be written into
memory. A low signal on the DM/BWS# pin indicates that the
write is valid. Driving the DM/BWS# pin high results in the
memory masking the DQ signals.
reside in or GND. See Note (12).
reside in or GND. See Note (12).
reside in or GND. See Note (12).
(6) The differential TX/RX channels for each device density and package is different. Please refer to the Cyclone III Handbook Chapter 8: High-Speed Differential Interfaces in Cyclone III Devices.
(7) For details on the DQ and DQS bus modes support in different device densities, refer to the Cyclone III Handbook Chapter 9: External Memory Interfaces in Cyclone III Devices.
(8) Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled.
A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power plane should then be decoupled using the
appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques
such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
(9) Use a power island for VCCA and VCCD_PLL. PLL power supply may originate from another plane on the board but must be isolated using a ferrite bead or other equivalent methods. If using a
ferrite bead, choose an 0402 package with low DC resistance, higher current rating than the maximum steady state current for the supply it is connected to (VCCA or VCCD_PLL) and high impedance
at 100MHz.
Page 9
Pin Type (1st, 2nd, &
Cyclone® III Device Family Pin Connection Guidelines
PCG-01003-1.0 (Note 1)
Pin Name
(10) Decouple VCCA power island with a parallel combination of 1x47uF, 1x4.7uF, 1x0.1uF, 1x0.022uF, 1x0.01uF, 1x0.0047uF, 2x0.022uF, 1x0.001uF. Use 0402 package for 0.1uF and smaller
capacitors for lower mounting inductance. Place 0.1uF and smaller capacitors as close to the device as possible. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series
Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To minimize
impact on jitter, a 20mV ripple voltage was used in the analysis for VCCA decoupling. Refer to the figure on page 11 for decoupling capacitor placement guidelines. The figure on page 11 depicts
symbolic representation of decoupling scheme and not the exact layout.
(11) Decouple VCCD_PLL power island with a parallel combination of 1x470uF(low ESR Tantalum), 1x4.7uF, 5x0.1uF, 2x0.01uF, 1x0.0047uF, 1x0.0022uF. Use 0402 package for 0.1uF and smaller
capacitors for lower mounting inductance. Place 0.1uF and smaller capacitors as close to the device as possible. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series
Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To minimize
impact on jitter, a 20mV ripple voltage was used in the analysis for VCCD_PLL decoupling. Refer to the figure on page 11 for decoupling capacitor placement guidelines. The figure on page 11 depicts
symbolic representation of decoupling scheme and not the exact layout.
(12) The unused pins must be connected as specified in the Quartus II software settings. The default Quartus II setting for unused pins is 'As inputs tri-stated with weak pull-up resistors'. To change the
setting, go to 'Assignments', then 'Device'. Click on 'Device & Pin options' dialog box and go to 'Unused Pins' tab. You may choose the desired setting from the 'Reserve all unused pins' drop down list.
3rd Function) Pin Description Connection Guidelines
Page 10
1.2V Regulator/
Power supply
470uF
VCCD_PLL power island
1.2V power plane
Ferrite bead
0.0022uf
0.0047uf
0.01uf
0.01uf
0.1uf
0.1uf
0.1uf
0.1uf
0.1uF
Cyclone III Device
Ferrite bead
2.5V power plane
2.5V Regulator/
Power supply
0.1uf
VCCA power island
0.01uf
0.022uf
47uf
0.0047uf
0.0022uf
0.001uf4.7uf 4.7uF
0.0022uf
Cyclone® III Device Family Pin Connection Guidelines
Version 1.0
Version Number Date Changes Made
1.0 10/17/2007 Initial release to Altera Literature site
Page 12
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