ALTERA PCG-01002-1.1 User Manual

Arria® GX Device Family Pin Connection Guidelines

PCG-01002-1.1

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The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Disclaimer Page 1 of 8

Arria® GX Device Family Pin Connection Guidelines

PCG-01002-1.1

You should create a Quartus II design, enter your device I/O assignments and compile the design. Quartus II will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments and other factors that are not fully described in this document or the device handbook.

Pin Type (1st, 2nd, & 3rd

Pin Name

Supply and Reference Pins

VCCINT Power 1.2V internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the

VCCIO[1..4,7,8] Power I/O supply voltage pins for banks 1-4, 7 & 8. Each bank can support a different voltage level. Supported

VCCPD[1..4,7,8] Power Dedicated power pins. This 3.3V supply is used to power the I/O pre-drivers and the 3.3-V/2.5-V buffers o

GND Ground Device ground pins. All GND pins should be connected to the board GND plane.

VREFB[1..4,7,8]N[2..0] Input Input reference voltage for each I/O bank. If a bank is used for a voltage-referenced I/O standard, then

VCC_PLL5_OUT Power External clock output VCCIO power for PLL5 clock outputs PLL5_OUT[1..0]p, PLL5_OUT[1..0]n,

VCC_PLL6_OUT Power External clock output VCCIO power for PLL6 clock outputs PLL6_OUT[1..0]p, PLL6_OUT[1..0]n,

VCC_PLL11_OUT Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT[1..0]p, PLL11_OUT[1..0]n,

VCC_PLL12_OUT Power External clock output VCCIO power for PLL12 clock outputs PLL12_OUT[1..0]p, PLL12_OUT[1..0]n,

VCCA_PLL[1,2,5..8,11,12] Power 1.2V Analog power for PLLs[1,2,5..8,11,12]. The designer is required to connect these pins to 1.2 V, even if the PLL is not used. Use an isolated linear supply. Power on the PLLs

VCCD_PLL[1,2,5..8,11,12] Power 1.2V Digital power for PLLs[1,2,5..8,11,12]. The designer is required to connect these pins to 1.2 V, even if the PLL is not used. Power on the PLLs operating at the same

GNDA_PLL[1,2,5..8,11,12] Ground Analog ground for PLLs[1,2,5..8,11,12]. Connect these pins to the same GND plane used by the FPGA GND pins. See Note 4. NC No Connect No Connect Do not drive signals into these pins.

Dedicated Configuration/JTAG Pins

nIO_PULLUP Input Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins

VCCSEL Input Dedicated input that selects which input buffer is used on configuration input pins: nCONFIG, DCLK

Function) Pin Description Connection Guidelines

LVDS, LVPECL, differential HSTL, differential SSTL, HSTL, and SSTL I/O standards.

voltages are 1.5V, 1.8V, 2.5V, and 3.3V. VCCIO[4,7,8] also supports 1.2V for 1.2V HSTL operation. For specific I/O standards supported by Arria refer to the Arria GX Handbook .

the configuration input pins and JTAG pins. VCCPD powers the JTAG pins (TCK, TMS, TDI, and TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_Pullup, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS and CLKUSR.

these pins are used as the voltage-reference pins for that bank. All of the VREF pins within a bank are shorted together.

PLL5_FBp/OUT2p & PLL5_FBn/OUT2n.

PLL6_FBp/OUT2p & PLL6_FBn/OUT2n.

PLL11_FBp/OUT2p & PLL11_FBn/OUT2n.

PLL12_FBp/OUT2p & PLL12_FBn/OUT2n.

(nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high (1.5 V, 1.8 V, 2.5 V, or

3.3 V) turns off the weak pull-up, while a logic low turns them on.

(when used as an input), DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The 3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. A logic high (VCCPD) selects the 1.8-V/1.5-V input buffer, while a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX II device/microprocessor with flash memory.

All VCCINT pins require a 1.2V supply. Decoupling depends on the design decoupling requirements of the specific board. See Note

Decoupling depends on the design decoupling requirements of the specific board. See Note 8.

The VCCPD pins require 3.3 V and must ramp-up from 0 V to 3.3 V within 100ms to ensure successful configuration. For Secure Configuration this needs to power to 3.7V for no longer than one minute (on VCCPD[8] only). TDO buffer is powered by VCCIO not VCCPD. Decoupling depends on the design decoupling requirements of the specific board. See Note 8.

If VREF pins are not used, designers should connect them to either the VCCIO in the bank in which the pin resides or GND. Decoupling depends on the design decoupling requirements of the specific board. See Note 8.

This pin should be connected to the voltage level of the target device which PLL5 in bank 9 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. Decoupling depends on the design decoupling requirements of the specific board. See Note 8. This pin should be connected to the voltage level of the target device which PLL6 in bank 10 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. Decoupling depends on the design decoupling requirements of the specific board. See Note 8. This pin should be connected to the voltage level of the target device which PLL11 in bank 11 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. Decoupling depends on the design decoupling requirements of the specific board. See Notes 6 and 8. This pin should be connected to the voltage level of the target device which PLL12 in bank 12 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. Decoupling depends on the design decoupling requirements of the specific board. See Notes 6 and 8.

operating at the same frequency should be decoupled. Decoupling depends on the design decoupling requirements of the specific board. See Notes 4 and 8.

frequency should be decoupled. Decoupling depends on the design decoupling requirements of the specific board. See Notes 4 and

The nIO-PULLUP can be tied directly to VCCPD, or use a 1 kΩ pull-up resistor or tied directly to GND depending on the use desired for the device. Refer to the description column..

The VCCSEL input buffer is powered by VCCPD and must be hardwired to VCCPD in order to enable the 1.8V/1.5V input buffers for configuration. VCCSEL tied to GND will enable a 3.3V/2.5V POR trip point, which may be above 1.8V. Refer to the description column.

Page 2 of 8Pin Connection Guidelines

Arria® GX Device Family Pin Connection Guidelines

PCG-01002-1.1

Pin Type (1st, 2nd, & 3rd

Pin Name

DCLK Input (PS, FPP)

MSEL[3..0] Input Configuration input pins that set the Arria GX device configuration scheme. These pins are internally connected through a 5kΩ resistor to GND. Do not leave these pins floating. When these pins are unused

nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device

nCONFIG Input Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose

CONF_DONE Bidirectional

nCEO Output Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. During single device configuration, this pin is left

nSTATUS Bidirectional

PORSEL Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5-V, 1.8-V, 2.5-V,

Optional/Dual-Purpose Configuration Pins

nCSO I/O Output Output control signal from the Arria GX FPGA to the serial configuration device in AS mode that enables

ASDO I/O Output Control signal from the Arria GX FPGA to the serial configuration device in AS mode used to read out

CRC_ERROR I/O, Output Active high signal that indicates that the error detection circuit has detected errors in the configuration

DEV_CLRn I/O, Input Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all

DEV_OE I/O, Input Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins

DATA0 I/O, Input Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an

DATA[6..1] I/O, Input Dual-purpose configuration input data pins. The DATA[7..0] pins can be used for byte-wide configuration

DATA7 I/O, Bidirectional In the PPA configuration scheme, the DATA7 pin presents the RDYnBSY signal after the nRS signal has

INIT_DONE I/O, Output

Function) Pin Description Connection Guidelines

Output (AS)

(open-drain)

Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the Arria GX device. In AS mode, DCLK is an output from the Arria GX device that provides timing for the configuration interface.

is disabled.

its configuration data, enter a reset state and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. This is a dedicated configuration Done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin.

This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin.

3.3-V) selects a POR time of about 12 ms and a logic low selects POR time of about 100 ms.

the configuration device.

configuration data.

SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled.

registers are cleared; when this pin is driven high, all registers behave as programmed.

are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design.

I/O pin after configuration is complete.

or as regular I/O pins. These pins can also be used as user I/O pins after configuration.

been strobed low. This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

In PPA mode, DCLK should be tied to VCC to prevent this pin from floating.

connect them to GND. Depending on the configuration scheme used these pins should be tied to VCCPD or GND. Refer to chapter 2, "Configuring Stratix II & Stratix II GX Devices", of the Configuration Handbook. If only JTAG configuration is used then connect these pins to ground.

In multi-device configuration, nCE of the first device is tied directly to GND while its nCEO pin drives the nCE of the next device in the chain. In single device configuration and JTAG programming, nCE is tied directly to GND. When using an active serial programming header connect this pin to a 10-kΩ pull-down resistor. If the configuration scheme uses an enhanced configuration device or EPC2, nCONFIG can be tied directly the configuration device's nINIT_CONF pin. If this pin is not used this pin requires a connection directly or through a resistor to VCCPD.

If internal pull-up resistors on the enhanced configuration device are used, external 10-kΩ pull-up resistors should not be used on these pins. When using EPC2 devices, only external 10-kΩ pull-up resistors should be used.

floating. For recommendations on how to connect nCEO in a chain with multiple voltages across the devices in the chain, refer to the Configuring Arria GX Devices chapter in Volume 2 of the Arria GX Device Handbook. The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have optional internal programmable pull-up resistors. If internal pull-up resistors on the enhanced configuration device are used, external 10-kΩ pull-up resistors should not be used on these pins. When using EPC2 devices, only external 10-kΩ pull-up resistors should be used.

The PORSEL pin should be tied directly to VCCPD or GND.

When not programming the device in AS mode nCSO is not used. Also, when this pin is not used as an I/O then it is recommended to leave the pin unconnected. When not programming the device in AS mode ASDO is not used. Also, when this pin is not used as an I/O then it is recommended to leave the pin unconnected. When the dedicated output for CRC_ERROR is not used and this pin is not used as an I/O then it is recommended to leave the pin unconnected.

When the dedicated input DEV_CLR is not used and this pin is not used as an I/O then it is recommended to tie this pin to VCCPD or ground.

When the dedicated input DEV_OE is not used and this pin is not used as an I/O then it is recommended to tie this pin to VCCPD or ground.

When the dedicated inputs for DATA[7..0] are not used and these pins are not used as an I/O then it is recommended to leave these pins unconnected. When the dedicated inputs for DATA[7..0] are not used and these pins are not used as an I/O then it is recommended to leave these pins unconnected.

When the dedicated inputs for DATA[7..0] are not used and these pins are not used as an I/O then it is recommended to leave these pins unconnected. Connect this pin to a 10kΩ resistor to VCCIO3.

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