Altera Partial Reconfiguration IP Core User Manual

2015.05.04

CRCBLOCK PRBLOCK

CB Interface Controller

Freeze/Unfreeze Controller

Data Source Controller

JTAG Debug

Interface

PR Data
Interface

FPGA Control
Block (CB)
Interface Module

Main Controller
Module

(1)

PR Data Source
Interface Module

Note:

1. The main controller module handles all the handshaking signals of the
CB interface and processes the incoming data, as needed, before sending
to the PRBLOCK. It also handles the freeze/un-freeze PR interface.

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Partial Reconfiguration IP Core

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Partial reconfiguration (PR) is fully supported in the Stratix® V device family, which offers you the ability
to reconfigure part of the design's core logic such as LABs, MLABs, DSP, and RAM, while the remainder
of the design continues running. The PR IP core can be implemented through the Qsys Interface, or via
the Quartus II® IP Catalog.

Partial reconfiguration is performed through either an internal host residing in the core logic or as an
external host via dedicated PR pins. The advantage of the internal host is that you can store all the logic
needed for PR on the device, without the need for external devices.

Figure 1: PR IP core Components

When you instantiate the PR IP core, the Main Controller module which includes the Control Block
Interface Controller, Freeze/Unfreeze Controller, and the Data Source Controller are all instantiated. A
Data Source Interface module provides you with a JTAG Debug Interface and PR Data Interface. If you
choose to use the PR IP core as an internal host, it automatically instantiates the corresponding crcblock
and prblock WYSIWYG atom primitives.

If it is used as external host (placed in another FPGA or CPLD), the PR IP core provides the crcblock

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and prblock WYSIWYG atom primitive as interface ports so that you can connect to the dedicated PR
pins and CRC_ERROR pin on the target FPGA undergoing partial reconfiguration.

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9001:2008
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PR

IP Core

PR
Region

PR Bitstream

file (.rbf) in

external memory

PR Control
Block (CB)

External

Host

PR
Region

PR Bitstream

file (.rbf) in

external memory

2

Instantiating the Partial Reconfiguration IP Core in the Qsys Interface

Figure 2: Managing Partial Reconfiguration with an Internal or External Host

The figure shows how these blocks should be connected to the PR control block (CB). In your system, you
will have either the external host or the internal host, but not both. During PR, the PR Control Block (CB)
is in Passive Parallel x16 programming mode.

Related Information

• FPGA Control Block Interface on page 15

• Control Block Interface Controller on page 17

• Freeze and Unfreeze Controls on page 18

• Data Source Controller on page 18

• Standard Partial Reconfiguration Data Interface on page 18

• JTAG Debug Mode for Partial Reconfiguration on page 19

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Instantiating the Partial Reconfiguration IP Core in the Qsys Interface

Partial Reconfiguration(PR) is available as a Qsys component through the Qsys interface.You can choose
to instantiate the core as an internal host or an external host.

When instantiated with Qsys, PR is configured as a Conduit interface, or by enabling the Avalon
Memory Map Slave interface. If you use Qsys and want PR included as component, you must instantiate
the PR IP core in the Qsys interface.

To instantiate the PR IP core with Qsys:

1. Click Tools > Qsys

2. In the Qsys interface IP Catalog expand Basic Functions > Configuration and Programming and
select Partial Reconfiguration.

3. Configure your IP core variation using the settings appropriate to your design.

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Figure 3: Partial Reconfiguration IP Core in the Qsys Interface

Instantiating the Partial Reconfiguration IP Core in the Quartus II IP Catalog

3

4. Turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interface rather
than the Conduit interface.

5. Click Finish.

Related Information

• Instantiating the Partial Reconfiguration IP Core in the Quartus II IP Catalog on page 3

• Partial Reconfiguration IP Core Parameters on page 6

• Creating a System With Qsys

Instantiating the Partial Reconfiguration IP Core in the Quartus II IP
Catalog

Partial Reconfiguration(PR) is available from the IP Catalog.You can choose to instantiate the core as an
internal host or an external host.

If you are not using PR as a component of the Qsys interface, then you can instantiate PR with the
Quartus II IP Catalog.

The PR IP core can be instantiated as the internal host for Stratix V devices. When internal host is
specified, both prblock and crcblock WYSIWYG atom primitives are auto-instantiated as part of the

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Instantiating the Partial Reconfiguration IP Core in the Quartus II IP Catalog

design. You can instantiate the PR IP core as the external host on any supported Altera devices as
specified in the user selectable device family list.

1. Click Tools > IP Catalog.

2. Expand Installed IP > Library > Basic Functions > Configuration and Programming and select
Partial Reconfiguration.

3. In the Save IP Variation dialog box, name your partial reconfiguration IP variation. Choose whether
to use Verilog or VHDL. Click OK to save your variation.

4. Configure your IP core variation using the s appropriate to your design.

Figure 4: Partial Reconfiguration IP Core in the IP Catalog

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5. Turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interface rather

6. Click Finish.

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than the Conduit interface.

The IP Catalog instantiates your IP core variation and displays a completion dialog box.

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Static Region

PR Region

Persona A

PR Bitstream

Persona B

from Same

Design

PR Bitstream

Persona B

from Different

Design

Incompatible PRPOF

(Will Corrupt the design

and May Damage Device)

Compatible

PR Bitstream (.rbf)

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7. Click Exit.

Bitstream Compatibility Check

5

Related Information

• Instantiating the Partial Reconfiguration IP Core in the Qsys Interface on page 2

• Partial Reconfiguration IP Core Parameters on page 6

Bitstream Compatibility Check

Turn on the Enable bitstream compatibility check when instantiaing the PR IP core from either Qsys or
the IP Catalog to have the Quartus II software verify the partial reconfiguration PR Bitstream file (.rbf). If
an incompatible bitstream is detected, the PR operation aborts and the status output reports an error.

This prevents you from accidentally corrupting the static region of your design with a bitstream from an
incompatible .rbf and risking damage to the chip being programmed.

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Partial Reconfiguration IP Core Parameters

When Enable bitstream compatibility check is turned on, the PR IP core creates a PR bitstream ID and
displays it in the configuration dialog box.

Related Information

• Partial Reconfiguration IP Core Parameters on page 6

• Partial Reconfiguration IP Core Ports on page 8

Partial Reconfiguration IP Core Parameters

IP Core Option Value Default Description

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Use as PR Internal
Host

Enable JTAG debug
mode

Enable Avalon-MM
slave interface

On or Off

On or Off

On or Off

On

On

Off

Turn on this option to use the
PR IP core as an internal host.
Both prblock and crcblock
WYSIWYG atom primitives are
auto-instantiated as part of your
design. Disable this option to use
the PR IP core as an external
host. You must connect
additional interface signals to the
dedicated PR pins or the external

prblock and crcblock

WYSIWYG atom primitives
interface signals if the PR IP core
is used as an external host.

Turn on this option to access the
PR IP core with the Programmer
to perform partial reconfigura‐
tion.

Turn on this option to use the
Avalon Memory Map slave
interface

Enable bitstream
compatibility check

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On or Off

Off Turn on this option to check the

bitstream compatibility during
PR operations for External Host.
The bitstream compatibility
check feature is always enabled
for PR Internal Host. The PR
bitstream ID value must be
specified if this option is enabled
for PR External Host.

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Partial Reconfiguration IP Core Parameters

IP Core Option Value Default Description

7

PR bitstream ID -2147483648 to

2147483647

Input Data Width

Target device
familiy for partial
reconfiguration

1, 2, 4, 8, 16, or 32 16 Specifies the data width in bits.

"Arria V", "Arria V
GZ", "Cyclone V",
"Stratix V"

Clock-to-Data ratio 1, 2, or 4

0 Specifies a signed 32-bit integer

value of the PR bitstream ID for
External Host. This value must
match the PR bitstream ID
generated during compilation
for the target PR design. The PR
bitstream ID value of the target
PR design can be found in the
Assembler compilation report
(.asm.rpt).

This option affects the data[]
bus width.

"Stratix V" Select the target device family for

partial reconfiguration when the
PR megafunction is used as
External Host.

Note: This option is ignored

for PR Internal Host.

1

Specifies the ratio between PR
clock and PR data. Select '1' for
plain PR data, '2' for encrypted
PR data, or '4' for compressed PR
data (with or without
encryption)

Divide error
detection frequency
by

1, 2, 4, 8, 16, 32, 64,
128, or 256

1

Only available when the IP core
is used as an Internal Host where
the crcblock WYSIWYG atom
primitive is auto-instantiated as
part of the design.

Specifies the divide value of the
internal clock, which determines
the frequency of the error
detection CRC. The divide value
must be a power of two. Refer to
the device handbook to find the
frequency of the internal clock
for the selected device.

Related Information

• Using the Avalon Memory Mapped Slave Interface on page 13

• Avalon Memory Map Slave Interface Read and Write Transfer Timing on page 17
For more information on the timing specification for the Avalon Memory Mapped Slave interface.

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8

Partial Reconfiguration IP Core Ports

Partial Reconfiguration IP Core Ports

I/O Port List for PR IP Core

Table 1: Clock/Reset Ports

These options are always available.

Port Name Width Direction Function

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nreset

clk

1

1

Table 2: Conduit Interface

This option is always available.

Port Name Width Direction Function

freeze

1

Input Asynchronous reset for the PR

IP core. Set high to enable partial
reconfiguration. Set low to
prevent partial reconfiguration
and reset the state machine in
the PR IP core.

Input User input clock to the PR IP

core.
This signal is ignored during

JTAG debug operations.

Output Active high signal used to freeze

the PR interface signals of the
region undergoing partial
reconfiguration. De-assertion of
this signal indicates the end of
PR operation.

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Partial Reconfiguration IP Core Ports

Table 3: Conduit Interface

These options are available when Enable Avalon-MM slave interface parameter is turned Off.

Port Name Width Direction Function

9

pr_start

data[]

1

1, 2, 4, 8, 16, or 32

Input A signal arriving at this port

asserted high initiates a PR
event. You must assert this signal
high for a minimum of one clock
cycle and de-assert it low prior to
the end of the PR operation so
that the PR IP core is ready to
accept the next pr_start trigger
event when the freeze signal is
low.

This signal is ignored during
JTAG debug operations.

Input Selectable input PR data bus

width, either x1, x2, x4, x8, x16,
or x32.

Once a PR event is triggered, it is
synchronous with the rising edge
of the clk signal whenever the

data_valid signal is high and

the data_read signal is high.
This signal is ignored during

JTAG debug operations.

data_valid

data_ready

1

Input A signal arriving at this port

asserted high indicates the

data[] port contains valid data.

This signal is ignored during
JTAG debug operations.

1

Output A signal arriving at this port

asserted high indicates the PR IP
core is ready to read the valid
data on the data[] port
whenever the data_valid signal
is asserted high. The data sender
must stop sending valid data if
this port is low.

This signal deasserted low
during JTAG debug operations.

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